Module Definition
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Module : clkmgr_sec_cm_checker_assert
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_sec_cm_checker_assert 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : clkmgr_sec_cm_checker_assert
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
23 1 1


Cond Coverage for Module : clkmgr_sec_cm_checker_assert
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01Unreachable
10CoveredT4,T2,T19

Assert Coverage for Module : clkmgr_sec_cm_checker_assert
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllClkBypReqFalse_A 156814927 154062112 0 0
AllClkBypReqTrue_A 156814927 129133 0 0
IoClkBypReqFalse_A 156814927 153984385 0 2415
IoClkBypReqTrue_A 156814927 202110 0 0
LcClkBypAckFalse_A 156814927 154072494 0 0
LcClkBypAckTrue_A 156814927 118751 0 0


AllClkBypReqFalse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 154062112 0 0
T1 90338 90284 0 0
T2 18675 18464 0 0
T3 61641 61500 0 0
T4 11127 1684 0 0
T5 1314 1224 0 0
T6 1596 1436 0 0
T7 2289 2084 0 0
T18 1586 1491 0 0
T19 224206 223818 0 0
T20 1100 1073 0 0

AllClkBypReqTrue_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 129133 0 0
T1 90338 0 0 0
T2 18675 55 0 0
T3 61641 0 0 0
T4 11127 0 0 0
T6 1596 88 0 0
T7 2289 56 0 0
T11 0 1195 0 0
T12 0 421 0 0
T13 0 1395 0 0
T18 1586 0 0 0
T19 224206 0 0 0
T20 1100 0 0 0
T21 1579 0 0 0
T28 0 149 0 0
T35 0 167 0 0
T47 0 79 0 0
T94 0 190 0 0

IoClkBypReqFalse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 153984385 0 2415
T1 90338 90282 0 3
T2 18675 18269 0 3
T3 61641 61498 0 3
T4 11127 1670 0 3
T5 1314 1111 0 3
T6 1596 1331 0 3
T7 2289 1807 0 3
T18 1586 1360 0 3
T19 224206 223814 0 3
T20 1100 1071 0 3

IoClkBypReqTrue_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 202110 0 0
T1 90338 0 0 0
T2 18675 246 0 0
T3 61641 0 0 0
T4 11127 0 0 0
T5 1314 111 0 0
T6 1596 191 0 0
T7 2289 331 0 0
T11 0 2268 0 0
T18 1586 129 0 0
T19 224206 0 0 0
T20 1100 0 0 0
T23 0 49 0 0
T28 0 134 0 0
T31 0 73 0 0
T47 0 220 0 0

LcClkBypAckFalse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 154072494 0 0
T1 90338 90284 0 0
T2 18675 18356 0 0
T3 61641 61500 0 0
T4 11127 1684 0 0
T5 1314 1122 0 0
T6 1596 1445 0 0
T7 2289 2039 0 0
T18 1586 1457 0 0
T19 224206 223818 0 0
T20 1100 1073 0 0

LcClkBypAckTrue_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 118751 0 0
T1 90338 0 0 0
T2 18675 163 0 0
T3 61641 0 0 0
T4 11127 0 0 0
T5 1314 102 0 0
T6 1596 79 0 0
T7 2289 101 0 0
T11 0 1285 0 0
T18 1586 34 0 0
T19 224206 0 0 0
T20 1100 0 0 0
T23 0 45 0 0
T28 0 48 0 0
T31 0 1 0 0
T47 0 140 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%