Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1983883932	14852	0	0
TransStop_A	1983883932	7576	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1983883932	14852	0	0
T2	186756	45	0	0
T3	270952	0	0	0
T11	0	105	0	0
T12	0	69	0	0
T13	0	293	0	0
T18	6540	0	0	0
T19	828532	0	0	0
T20	18348	4	0	0
T21	5964	0	0	0
T22	15648	4	0	0
T23	6048	0	0	0
T28	12796	0	0	0
T29	135112	0	0	0
T95	0	35	0	0
T96	0	21	0	0
T97	0	6	0	0
T98	0	27	0	0
T99	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1983883932	7576	0	0
T2	186756	17	0	0
T3	270952	0	0	0
T11	0	43	0	0
T12	0	43	0	0
T13	0	155	0	0
T18	6540	0	0	0
T19	828532	0	0	0
T20	18348	4	0	0
T21	5964	0	0	0
T22	15648	4	0	0
T23	6048	0	0	0
T28	12796	0	0	0
T29	135112	0	0	0
T95	0	20	0	0
T96	0	7	0	0
T97	0	4	0	0
T98	0	16	0	0
T99	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	495970983	3709	0	0
TransStop_A	495970983	1906	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970983	3709	0	0
T2	46689	10	0	0
T3	67738	0	0	0
T11	0	30	0	0
T12	0	24	0	0
T13	0	74	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	0	0	0
T22	3912	1	0	0
T23	1512	0	0	0
T28	3199	0	0	0
T29	33778	0	0	0
T95	0	6	0	0
T96	0	6	0	0
T97	0	2	0	0
T98	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970983	1906	0	0
T2	46689	5	0	0
T3	67738	0	0	0
T11	0	10	0	0
T12	0	14	0	0
T13	0	35	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	0	0	0
T22	3912	1	0	0
T23	1512	0	0	0
T28	3199	0	0	0
T29	33778	0	0	0
T95	0	4	0	0
T96	0	2	0	0
T97	0	1	0	0
T98	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	495970983	3739	0	0
TransStop_A	495970983	1920	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970983	3739	0	0
T2	46689	13	0	0
T3	67738	0	0	0
T11	0	26	0	0
T12	0	18	0	0
T13	0	76	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	0	0	0
T22	3912	1	0	0
T23	1512	0	0	0
T28	3199	0	0	0
T29	33778	0	0	0
T95	0	11	0	0
T96	0	7	0	0
T98	0	9	0	0
T99	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970983	1920	0	0
T2	46689	4	0	0
T3	67738	0	0	0
T11	0	12	0	0
T12	0	11	0	0
T13	0	42	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	0	0	0
T22	3912	1	0	0
T23	1512	0	0	0
T28	3199	0	0	0
T29	33778	0	0	0
T95	0	7	0	0
T96	0	2	0	0
T98	0	5	0	0
T99	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	495970983	3733	0	0
TransStop_A	495970983	1905	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970983	3733	0	0
T2	46689	12	0	0
T3	67738	0	0	0
T11	0	21	0	0
T12	0	16	0	0
T13	0	73	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	0	0	0
T22	3912	1	0	0
T23	1512	0	0	0
T28	3199	0	0	0
T29	33778	0	0	0
T95	0	12	0	0
T96	0	4	0	0
T97	0	3	0	0
T98	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970983	1905	0	0
T2	46689	5	0	0
T3	67738	0	0	0
T11	0	11	0	0
T12	0	11	0	0
T13	0	39	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	0	0	0
T22	3912	1	0	0
T23	1512	0	0	0
T28	3199	0	0	0
T29	33778	0	0	0
T95	0	6	0	0
T96	0	1	0	0
T97	0	2	0	0
T98	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	495970983	3671	0	0
TransStop_A	495970983	1845	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970983	3671	0	0
T2	46689	10	0	0
T3	67738	0	0	0
T11	0	28	0	0
T12	0	11	0	0
T13	0	70	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	0	0	0
T22	3912	1	0	0
T23	1512	0	0	0
T28	3199	0	0	0
T29	33778	0	0	0
T95	0	6	0	0
T96	0	4	0	0
T97	0	1	0	0
T98	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970983	1845	0	0
T2	46689	3	0	0
T3	67738	0	0	0
T11	0	10	0	0
T12	0	7	0	0
T13	0	39	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	0	0	0
T22	3912	1	0	0
T23	1512	0	0	0
T28	3199	0	0	0
T29	33778	0	0	0
T95	0	3	0	0
T96	0	2	0	0
T97	0	1	0	0
T98	0	3	0	0