Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	156814927	20334566	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156814927	20334566	0	57
T1	90338	24831	0	1
T2	18675	5613	0	0
T3	61641	12074	0	1
T4	11127	0	0	0
T11	0	253953	0	0
T12	0	74620	0	0
T13	0	110787	0	0
T14	0	12281	0	1
T15	0	142082	0	0
T16	0	623802	0	0
T17	0	9725	0	1
T18	1586	0	0	0
T19	224206	0	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T100	0	0	0	1
T101	0	0	0	1
T102	0	0	0	1