Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	157786120	5259950	0	0
clk_enables_rd_A	157786120	39580	0	0
clk_hints_rd_A	157786120	35005	0	0
extclk_ctrl_rd_A	157786120	43194	0	0
extclk_ctrl_regwen_rd_A	157786120	32111	0	0
jitter_enable_rd_A	157786120	48889	0	0
jitter_regwen_rd_A	157786120	37213	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	5259950	0	0
T8	89208	0	0	0
T11	328042	152946	0	0
T12	417786	0	0	0
T13	255725	127311	0	0
T15	0	85977	0	0
T16	0	116108	0	0
T27	0	95092	0	0
T30	1297	0	0	0
T31	806	0	0	0
T32	36944	0	0	0
T33	54228	0	0	0
T34	0	78130	0	0
T35	1842	0	0	0
T36	841	0	0	0
T58	0	64416	0	0
T59	0	44715	0	0
T60	0	131377	0	0
T61	0	117003	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	39580	0	0
T15	181181	0	0	0
T41	0	3051	0	0
T99	2349	3	0	0
T121	0	1	0	0
T122	0	2875	0	0
T123	0	2	0	0
T124	0	3173	0	0
T125	0	5382	0	0
T126	0	4	0	0
T127	0	2	0	0
T128	0	2671	0	0
T129	1028	0	0	0
T130	2254	0	0	0
T131	1580	0	0	0
T132	2035	0	0	0
T133	1592	0	0	0
T134	22095	0	0	0
T135	9129	0	0	0
T136	1944	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	35005	0	0
T15	181181	0	0	0
T41	0	2823	0	0
T99	2349	2	0	0
T121	0	7	0	0
T122	0	2220	0	0
T123	0	2	0	0
T124	0	2670	0	0
T125	0	4418	0	0
T127	0	5	0	0
T129	1028	0	0	0
T130	2254	0	0	0
T131	1580	0	0	0
T132	2035	0	0	0
T133	1592	0	0	0
T134	22095	0	0	0
T135	9129	0	0	0
T136	1944	0	0	0
T137	0	1	0	0
T138	0	7	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	43194	0	0
T1	90338	0	0	0
T2	18675	0	0	0
T3	61641	0	0	0
T4	11127	0	0	0
T5	1314	7	0	0
T6	1596	16	0	0
T7	2289	0	0	0
T18	1586	22	0	0
T19	224206	0	0	0
T20	1100	0	0	0
T33	0	45	0	0
T103	0	13	0	0
T131	0	14	0	0
T139	0	11	0	0
T140	0	80	0	0
T141	0	20	0	0
T142	0	40	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	32111	0	0
T13	255725	0	0	0
T33	54228	37	0	0
T37	1044	0	0	0
T62	43299	0	0	0
T63	61150	0	0	0
T94	1981	0	0	0
T95	2975	0	0	0
T96	1701	0	0	0
T97	1361	0	0	0
T103	1690	0	0	0
T122	0	2200	0	0
T124	0	2440	0	0
T125	0	4747	0	0
T143	0	55	0	0
T144	0	83	0	0
T145	0	21	0	0
T146	0	29	0	0
T147	0	28	0	0
T148	0	88	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	48889	0	0
T15	181181	0	0	0
T99	2349	95	0	0
T121	0	106	0	0
T122	0	2709	0	0
T123	0	96	0	0
T124	0	3418	0	0
T125	0	5841	0	0
T126	0	84	0	0
T127	0	98	0	0
T129	1028	0	0	0
T130	2254	0	0	0
T131	1580	0	0	0
T132	2035	0	0	0
T133	1592	0	0	0
T134	22095	0	0	0
T135	9129	0	0	0
T136	1944	0	0	0
T137	0	63	0	0
T138	0	95	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	37213	0	0
T41	0	2921	0	0
T122	219299	2552	0	0
T124	0	3003	0	0
T125	0	5397	0	0
T128	0	2502	0	0
T149	0	2031	0	0
T150	0	2137	0	0
T151	0	3762	0	0
T152	0	3875	0	0
T153	0	3763	0	0
T154	1337	0	0	0
T155	463503	0	0	0
T156	1842	0	0	0
T157	1927	0	0	0
T158	60404	0	0	0
T159	2118	0	0	0
T160	894	0	0	0
T161	98956	0	0	0
T162	2135	0	0	0