SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.63 | 100.00 | 93.15 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.63 | 100.00 | 93.15 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T6,T2,T18 |
1 | 1 | Covered | T5,T6,T7 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 465364316 | 4367 | 0 | 0 |
g_div2.Div2Whole_A | 465364316 | 5096 | 0 | 0 |
g_div4.Div4Stepped_A | 231981661 | 4281 | 0 | 0 |
g_div4.Div4Whole_A | 231981661 | 4829 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 465364316 | 4367 | 0 | 0 |
T1 | 88492 | 0 | 0 | 0 |
T2 | 44820 | 8 | 0 | 0 |
T3 | 65027 | 0 | 0 | 0 |
T4 | 42729 | 0 | 0 | 0 |
T5 | 2575 | 3 | 0 | 0 |
T6 | 4259 | 4 | 0 | 0 |
T7 | 2290 | 3 | 0 | 0 |
T11 | 0 | 42 | 0 | 0 |
T12 | 0 | 21 | 0 | 0 |
T18 | 1570 | 1 | 0 | 0 |
T19 | 164284 | 0 | 0 | 0 |
T20 | 4404 | 0 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T28 | 0 | 6 | 0 | 0 |
T47 | 0 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 465364316 | 5096 | 0 | 0 |
T1 | 88492 | 0 | 0 | 0 |
T2 | 44820 | 8 | 0 | 0 |
T3 | 65027 | 0 | 0 | 0 |
T4 | 42729 | 0 | 0 | 0 |
T5 | 2575 | 3 | 0 | 0 |
T6 | 4259 | 4 | 0 | 0 |
T7 | 2290 | 8 | 0 | 0 |
T11 | 0 | 69 | 0 | 0 |
T18 | 1570 | 2 | 0 | 0 |
T19 | 164284 | 0 | 0 | 0 |
T20 | 4404 | 0 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T28 | 0 | 6 | 0 | 0 |
T31 | 0 | 1 | 0 | 0 |
T47 | 0 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 231981661 | 4281 | 0 | 0 |
T1 | 44234 | 0 | 0 | 0 |
T2 | 23106 | 8 | 0 | 0 |
T3 | 32501 | 0 | 0 | 0 |
T4 | 15301 | 0 | 0 | 0 |
T5 | 1345 | 3 | 0 | 0 |
T6 | 2248 | 4 | 0 | 0 |
T7 | 1161 | 2 | 0 | 0 |
T11 | 0 | 40 | 0 | 0 |
T12 | 0 | 20 | 0 | 0 |
T18 | 770 | 1 | 0 | 0 |
T19 | 82028 | 0 | 0 | 0 |
T20 | 2190 | 0 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T28 | 0 | 6 | 0 | 0 |
T47 | 0 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 231981661 | 4829 | 0 | 0 |
T1 | 44234 | 0 | 0 | 0 |
T2 | 23106 | 8 | 0 | 0 |
T3 | 32501 | 0 | 0 | 0 |
T4 | 15301 | 0 | 0 | 0 |
T5 | 1345 | 3 | 0 | 0 |
T6 | 2248 | 4 | 0 | 0 |
T7 | 1161 | 7 | 0 | 0 |
T11 | 0 | 53 | 0 | 0 |
T18 | 770 | 2 | 0 | 0 |
T19 | 82028 | 0 | 0 | 0 |
T20 | 2190 | 0 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T28 | 0 | 6 | 0 | 0 |
T31 | 0 | 1 | 0 | 0 |
T47 | 0 | 8 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T6,T2,T18 |
1 | 1 | Covered | T5,T6,T7 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 465364316 | 4367 | 0 | 0 |
g_div2.Div2Whole_A | 465364316 | 5096 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 465364316 | 4367 | 0 | 0 |
T1 | 88492 | 0 | 0 | 0 |
T2 | 44820 | 8 | 0 | 0 |
T3 | 65027 | 0 | 0 | 0 |
T4 | 42729 | 0 | 0 | 0 |
T5 | 2575 | 3 | 0 | 0 |
T6 | 4259 | 4 | 0 | 0 |
T7 | 2290 | 3 | 0 | 0 |
T11 | 0 | 42 | 0 | 0 |
T12 | 0 | 21 | 0 | 0 |
T18 | 1570 | 1 | 0 | 0 |
T19 | 164284 | 0 | 0 | 0 |
T20 | 4404 | 0 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T28 | 0 | 6 | 0 | 0 |
T47 | 0 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 465364316 | 5096 | 0 | 0 |
T1 | 88492 | 0 | 0 | 0 |
T2 | 44820 | 8 | 0 | 0 |
T3 | 65027 | 0 | 0 | 0 |
T4 | 42729 | 0 | 0 | 0 |
T5 | 2575 | 3 | 0 | 0 |
T6 | 4259 | 4 | 0 | 0 |
T7 | 2290 | 8 | 0 | 0 |
T11 | 0 | 69 | 0 | 0 |
T18 | 1570 | 2 | 0 | 0 |
T19 | 164284 | 0 | 0 | 0 |
T20 | 4404 | 0 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T28 | 0 | 6 | 0 | 0 |
T31 | 0 | 1 | 0 | 0 |
T47 | 0 | 8 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T6,T2,T18 |
1 | 1 | Covered | T5,T6,T7 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 231981661 | 4281 | 0 | 0 |
g_div4.Div4Whole_A | 231981661 | 4829 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 231981661 | 4281 | 0 | 0 |
T1 | 44234 | 0 | 0 | 0 |
T2 | 23106 | 8 | 0 | 0 |
T3 | 32501 | 0 | 0 | 0 |
T4 | 15301 | 0 | 0 | 0 |
T5 | 1345 | 3 | 0 | 0 |
T6 | 2248 | 4 | 0 | 0 |
T7 | 1161 | 2 | 0 | 0 |
T11 | 0 | 40 | 0 | 0 |
T12 | 0 | 20 | 0 | 0 |
T18 | 770 | 1 | 0 | 0 |
T19 | 82028 | 0 | 0 | 0 |
T20 | 2190 | 0 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T28 | 0 | 6 | 0 | 0 |
T47 | 0 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 231981661 | 4829 | 0 | 0 |
T1 | 44234 | 0 | 0 | 0 |
T2 | 23106 | 8 | 0 | 0 |
T3 | 32501 | 0 | 0 | 0 |
T4 | 15301 | 0 | 0 | 0 |
T5 | 1345 | 3 | 0 | 0 |
T6 | 2248 | 4 | 0 | 0 |
T7 | 1161 | 7 | 0 | 0 |
T11 | 0 | 53 | 0 | 0 |
T18 | 770 | 2 | 0 | 0 |
T19 | 82028 | 0 | 0 | 0 |
T20 | 2190 | 0 | 0 | 0 |
T23 | 0 | 1 | 0 | 0 |
T28 | 0 | 6 | 0 | 0 |
T31 | 0 | 1 | 0 | 0 |
T47 | 0 | 8 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |