Module Definition
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Module : clkmgr_pwrmgr_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_pwrmgr_sva_if 100.00 100.00



Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : clkmgr_pwrmgr_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IoStatusFall_A 156814927 145 0 0
IoStatusRise_A 156814927 145 0 0
MainStatusFall_A 156814927 148 0 0
MainStatusRise_A 156814927 148 0 0
UsbStatusFall_A 156814927 154 0 0
UsbStatusRise_A 156814927 154 0 0


IoStatusFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 145 0 0
T8 89208 0 0 0
T11 328042 0 0 0
T21 1579 5 0 0
T22 1917 0 0 0
T23 1511 0 0 0
T28 1536 0 0 0
T29 32426 0 0 0
T30 1297 0 0 0
T31 806 0 0 0
T36 0 2 0 0
T44 0 3 0 0
T47 1336 0 0 0
T160 0 6 0 0
T163 0 3 0 0
T164 0 2 0 0
T165 0 1 0 0
T166 0 3 0 0
T167 0 2 0 0
T168 0 1 0 0

IoStatusRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 145 0 0
T8 89208 0 0 0
T11 328042 0 0 0
T21 1579 5 0 0
T22 1917 0 0 0
T23 1511 0 0 0
T28 1536 0 0 0
T29 32426 0 0 0
T30 1297 0 0 0
T31 806 0 0 0
T36 0 2 0 0
T44 0 3 0 0
T47 1336 0 0 0
T160 0 6 0 0
T163 0 3 0 0
T164 0 2 0 0
T165 0 1 0 0
T166 0 3 0 0
T167 0 2 0 0
T168 0 1 0 0

MainStatusFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 148 0 0
T8 89208 0 0 0
T11 328042 0 0 0
T21 1579 5 0 0
T22 1917 0 0 0
T23 1511 0 0 0
T28 1536 0 0 0
T29 32426 0 0 0
T30 1297 0 0 0
T31 806 0 0 0
T36 0 3 0 0
T44 0 4 0 0
T47 1336 0 0 0
T160 0 5 0 0
T163 0 2 0 0
T164 0 1 0 0
T166 0 2 0 0
T167 0 2 0 0
T168 0 1 0 0
T169 0 3 0 0

MainStatusRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 148 0 0
T8 89208 0 0 0
T11 328042 0 0 0
T21 1579 5 0 0
T22 1917 0 0 0
T23 1511 0 0 0
T28 1536 0 0 0
T29 32426 0 0 0
T30 1297 0 0 0
T31 806 0 0 0
T36 0 3 0 0
T44 0 4 0 0
T47 1336 0 0 0
T160 0 5 0 0
T163 0 2 0 0
T164 0 1 0 0
T166 0 2 0 0
T167 0 2 0 0
T168 0 1 0 0
T169 0 3 0 0

UsbStatusFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 154 0 0
T8 89208 0 0 0
T11 328042 0 0 0
T21 1579 4 0 0
T22 1917 0 0 0
T23 1511 0 0 0
T28 1536 0 0 0
T29 32426 0 0 0
T30 1297 0 0 0
T31 806 0 0 0
T36 0 3 0 0
T44 0 3 0 0
T47 1336 0 0 0
T160 0 6 0 0
T163 0 3 0 0
T164 0 2 0 0
T166 0 4 0 0
T167 0 2 0 0
T168 0 1 0 0
T169 0 4 0 0

UsbStatusRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 154 0 0
T8 89208 0 0 0
T11 328042 0 0 0
T21 1579 4 0 0
T22 1917 0 0 0
T23 1511 0 0 0
T28 1536 0 0 0
T29 32426 0 0 0
T30 1297 0 0 0
T31 806 0 0 0
T36 0 3 0 0
T44 0 3 0 0
T47 1336 0 0 0
T160 0 6 0 0
T163 0 3 0 0
T164 0 2 0 0
T166 0 4 0 0
T167 0 2 0 0
T168 0 1 0 0
T169 0 4 0 0

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