Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T19
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48101	0	0
CgEnOn_A	2147483647	38602	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48101	0	0
T1	199088	3	0	0
T2	288642	26	0	0
T3	417240	3	0	0
T4	87042	21	0	0
T5	5876	3	0	0
T6	9758	3	0	0
T7	5173	3	0	0
T8	328463	0	0	0
T11	3419022	0	0	0
T18	10048	3	0	0
T19	1223921	6	0	0
T20	28237	7	0	0
T21	12142	30	0	0
T22	31761	1	0	0
T23	12268	0	0	0
T27	0	5	0	0
T28	26443	0	0	0
T29	265925	0	0	0
T30	10735	0	0	0
T31	17630	0	0	0
T36	0	13	0	0
T44	0	15	0	0
T47	23874	0	0	0
T163	0	15	0	0
T164	0	10	0	0
T165	0	5	0	0
T166	0	15	0	0
T167	0	10	0	0
T168	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38602	0	0
T2	288642	20	0	0
T3	417240	0	0	0
T8	328463	0	0	0
T11	3419022	241	0	0
T12	0	167	0	0
T13	0	335	0	0
T18	10048	0	0	0
T19	1223921	0	0	0
T20	28237	4	0	0
T21	15396	45	0	0
T22	40117	4	0	0
T23	15495	0	0	0
T27	0	4	0	0
T28	33560	0	0	0
T29	333063	0	0	0
T30	10735	31	0	0
T31	17630	0	0	0
T36	0	19	0	0
T44	0	15	0	0
T47	23874	0	0	0
T95	0	6	0	0
T96	0	6	0	0
T99	0	3	0	0
T160	0	6	0	0
T163	0	15	0	0
T164	0	10	0	0
T165	0	5	0	0
T166	0	15	0	0
T167	0	10	0	0
T168	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	231981232	154	0	0
CgEnOn_A	231981232	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231981232	154	0	0
T8	25763	0	0	0
T11	153602	0	0	0
T21	693	5	0	0
T22	1817	0	0	0
T23	701	0	0	0
T27	0	1	0	0
T28	1674	0	0	0
T29	12333	0	0	0
T30	1220	0	0	0
T31	2027	0	0	0
T36	0	2	0	0
T44	0	3	0	0
T47	2956	0	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231981232	154	0	0
T8	25763	0	0	0
T11	153602	0	0	0
T21	693	5	0	0
T22	1817	0	0	0
T23	701	0	0	0
T27	0	1	0	0
T28	1674	0	0	0
T29	12333	0	0	0
T30	1220	0	0	0
T31	2027	0	0	0
T36	0	2	0	0
T44	0	3	0	0
T47	2956	0	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115990036	154	0	0
CgEnOn_A	115990036	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115990036	154	0	0
T8	12882	0	0	0
T11	768003	0	0	0
T21	346	5	0	0
T22	908	0	0	0
T23	350	0	0	0
T27	0	1	0	0
T28	837	0	0	0
T29	6166	0	0	0
T30	610	0	0	0
T31	1013	0	0	0
T36	0	2	0	0
T44	0	3	0	0
T47	1477	0	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115990036	154	0	0
T8	12882	0	0	0
T11	768003	0	0	0
T21	346	5	0	0
T22	908	0	0	0
T23	350	0	0	0
T27	0	1	0	0
T28	837	0	0	0
T29	6166	0	0	0
T30	610	0	0	0
T31	1013	0	0	0
T36	0	2	0	0
T44	0	3	0	0
T47	1477	0	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	465363841	154	0	0
CgEnOn_A	465363841	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465363841	154	0	0
T8	85638	0	0	0
T11	308087	0	0	0
T21	1465	5	0	0
T22	3754	0	0	0
T23	1451	0	0	0
T27	0	1	0	0
T28	3070	0	0	0
T29	32426	0	0	0
T30	2493	0	0	0
T31	4074	0	0	0
T36	0	2	0	0
T44	0	3	0	0
T47	5347	0	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465363841	147	0	0
T8	85638	0	0	0
T11	308087	0	0	0
T21	1465	5	0	0
T22	3754	0	0	0
T23	1451	0	0	0
T28	3070	0	0	0
T29	32426	0	0	0
T30	2493	0	0	0
T31	4074	0	0	0
T36	0	2	0	0
T44	0	3	0	0
T47	5347	0	0	0
T160	0	6	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	495970562	152	0	0
CgEnOn_A	495970562	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970562	152	0	0
T8	89208	0	0	0
T11	326662	0	0	0
T21	1491	5	0	0
T22	3911	0	0	0
T23	1511	0	0	0
T28	3198	0	0	0
T29	33778	0	0	0
T30	2596	0	0	0
T31	4245	0	0	0
T36	0	3	0	0
T44	0	4	0	0
T47	5570	0	0	0
T160	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	1	0	0
T169	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970562	150	0	0
T8	89208	0	0	0
T11	326662	0	0	0
T21	1491	5	0	0
T22	3911	0	0	0
T23	1511	0	0	0
T28	3198	0	0	0
T29	33778	0	0	0
T30	2596	0	0	0
T31	4245	0	0	0
T36	0	3	0	0
T44	0	4	0	0
T47	5570	0	0	0
T160	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	1	0	0
T169	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115990036	154	0	0
CgEnOn_A	115990036	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115990036	154	0	0
T8	12882	0	0	0
T11	768003	0	0	0
T21	346	5	0	0
T22	908	0	0	0
T23	350	0	0	0
T27	0	1	0	0
T28	837	0	0	0
T29	6166	0	0	0
T30	610	0	0	0
T31	1013	0	0	0
T36	0	2	0	0
T44	0	3	0	0
T47	1477	0	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115990036	154	0	0
T8	12882	0	0	0
T11	768003	0	0	0
T21	346	5	0	0
T22	908	0	0	0
T23	350	0	0	0
T27	0	1	0	0
T28	837	0	0	0
T29	6166	0	0	0
T30	610	0	0	0
T31	1013	0	0	0
T36	0	2	0	0
T44	0	3	0	0
T47	1477	0	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	495970562	152	0	0
CgEnOn_A	495970562	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970562	152	0	0
T8	89208	0	0	0
T11	326662	0	0	0
T21	1491	5	0	0
T22	3911	0	0	0
T23	1511	0	0	0
T28	3198	0	0	0
T29	33778	0	0	0
T30	2596	0	0	0
T31	4245	0	0	0
T36	0	3	0	0
T44	0	4	0	0
T47	5570	0	0	0
T160	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	1	0	0
T169	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970562	150	0	0
T8	89208	0	0	0
T11	326662	0	0	0
T21	1491	5	0	0
T22	3911	0	0	0
T23	1511	0	0	0
T28	3198	0	0	0
T29	33778	0	0	0
T30	2596	0	0	0
T31	4245	0	0	0
T36	0	3	0	0
T44	0	4	0	0
T47	5570	0	0	0
T160	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	1	0	0
T169	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115990036	154	0	0
CgEnOn_A	115990036	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115990036	154	0	0
T8	12882	0	0	0
T11	768003	0	0	0
T21	346	5	0	0
T22	908	0	0	0
T23	350	0	0	0
T27	0	1	0	0
T28	837	0	0	0
T29	6166	0	0	0
T30	610	0	0	0
T31	1013	0	0	0
T36	0	2	0	0
T44	0	3	0	0
T47	1477	0	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115990036	154	0	0
T8	12882	0	0	0
T11	768003	0	0	0
T21	346	5	0	0
T22	908	0	0	0
T23	350	0	0	0
T27	0	1	0	0
T28	837	0	0	0
T29	6166	0	0	0
T30	610	0	0	0
T31	1013	0	0	0
T36	0	2	0	0
T44	0	3	0	0
T47	1477	0	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T36,T44
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	231981232	7908	0	0
CgEnOn_A	231981232	5542	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231981232	7908	0	0
T1	44233	1	0	0
T2	23105	5	0	0
T3	32501	1	0	0
T4	15300	7	0	0
T5	1344	1	0	0
T6	2248	1	0	0
T7	1160	1	0	0
T18	770	1	0	0
T19	82027	2	0	0
T20	2189	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231981232	5542	0	0
T2	23105	3	0	0
T3	32501	0	0	0
T11	0	71	0	0
T12	0	46	0	0
T13	0	85	0	0
T18	770	0	0	0
T19	82027	0	0	0
T20	2189	1	0	0
T21	693	5	0	0
T22	1817	1	0	0
T23	701	0	0	0
T28	1674	0	0	0
T29	12333	0	0	0
T30	0	10	0	0
T36	0	2	0	0
T99	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T36,T44
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115990036	7840	0	0
CgEnOn_A	115990036	5474	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115990036	7840	0	0
T1	22117	1	0	0
T2	11552	6	0	0
T3	16250	1	0	0
T4	7649	7	0	0
T5	671	1	0	0
T6	1123	1	0	0
T7	580	1	0	0
T18	385	1	0	0
T19	41014	2	0	0
T20	1095	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115990036	5474	0	0
T2	11552	4	0	0
T3	16250	0	0	0
T11	0	66	0	0
T12	0	48	0	0
T13	0	89	0	0
T18	385	0	0	0
T19	41014	0	0	0
T20	1095	1	0	0
T21	346	5	0	0
T22	908	1	0	0
T23	350	0	0	0
T28	837	0	0	0
T29	6166	0	0	0
T30	0	11	0	0
T36	0	2	0	0
T99	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T36,T44
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	465363841	7934	0	0
CgEnOn_A	465363841	5561	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465363841	7934	0	0
T1	88491	1	0	0
T2	44819	5	0	0
T3	65026	1	0	0
T4	42728	7	0	0
T5	2574	1	0	0
T6	4258	1	0	0
T7	2289	1	0	0
T18	1569	1	0	0
T19	164283	2	0	0
T20	4403	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465363841	5561	0	0
T2	44819	3	0	0
T3	65026	0	0	0
T11	0	74	0	0
T12	0	49	0	0
T13	0	87	0	0
T18	1569	0	0	0
T19	164283	0	0	0
T20	4403	1	0	0
T21	1465	5	0	0
T22	3754	1	0	0
T23	1451	0	0	0
T28	3070	0	0	0
T29	32426	0	0	0
T30	0	10	0	0
T36	0	2	0	0
T99	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T36,T44
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	238010522	7885	0	0
CgEnOn_A	238010522	5510	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238010522	7885	0	0
T1	44247	1	0	0
T2	22410	6	0	0
T3	32515	1	0	0
T4	21365	7	0	0
T5	1287	1	0	0
T6	2129	1	0	0
T7	1144	1	0	0
T18	784	1	0	0
T19	108065	2	0	0
T20	2202	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238010522	5510	0	0
T2	22410	4	0	0
T3	32515	0	0	0
T11	0	65	0	0
T12	0	47	0	0
T13	0	86	0	0
T18	784	0	0	0
T19	108065	0	0	0
T20	2202	1	0	0
T21	750	4	0	0
T22	1877	1	0	0
T23	725	0	0	0
T28	1536	0	0	0
T29	16213	0	0	0
T30	0	9	0	0
T36	0	3	0	0
T99	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T19
1	0	Covered	T2,T20,T22
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	495970562	3861	0	0
CgEnOn_A	495970562	3859	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970562	3861	0	0
T2	46689	10	0	0
T3	67737	0	0	0
T11	0	30	0	0
T12	0	24	0	0
T13	0	74	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	5	0	0
T22	3911	1	0	0
T23	1511	0	0	0
T28	3198	0	0	0
T29	33778	0	0	0
T36	0	3	0	0
T95	0	6	0	0
T96	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970562	3859	0	0
T2	46689	10	0	0
T3	67737	0	0	0
T11	0	30	0	0
T12	0	24	0	0
T13	0	74	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	5	0	0
T22	3911	1	0	0
T23	1511	0	0	0
T28	3198	0	0	0
T29	33778	0	0	0
T36	0	3	0	0
T95	0	6	0	0
T96	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T19
1	0	Covered	T2,T20,T22
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	495970562	3891	0	0
CgEnOn_A	495970562	3889	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970562	3891	0	0
T2	46689	13	0	0
T3	67737	0	0	0
T11	0	26	0	0
T12	0	18	0	0
T13	0	76	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	5	0	0
T22	3911	1	0	0
T23	1511	0	0	0
T28	3198	0	0	0
T29	33778	0	0	0
T36	0	3	0	0
T95	0	11	0	0
T96	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970562	3889	0	0
T2	46689	13	0	0
T3	67737	0	0	0
T11	0	26	0	0
T12	0	18	0	0
T13	0	76	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	5	0	0
T22	3911	1	0	0
T23	1511	0	0	0
T28	3198	0	0	0
T29	33778	0	0	0
T36	0	3	0	0
T95	0	11	0	0
T96	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T19
1	0	Covered	T2,T20,T22
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	495970562	3885	0	0
CgEnOn_A	495970562	3883	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970562	3885	0	0
T2	46689	12	0	0
T3	67737	0	0	0
T11	0	21	0	0
T12	0	16	0	0
T13	0	73	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	5	0	0
T22	3911	1	0	0
T23	1511	0	0	0
T28	3198	0	0	0
T29	33778	0	0	0
T36	0	3	0	0
T95	0	12	0	0
T96	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970562	3883	0	0
T2	46689	12	0	0
T3	67737	0	0	0
T11	0	21	0	0
T12	0	16	0	0
T13	0	73	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	5	0	0
T22	3911	1	0	0
T23	1511	0	0	0
T28	3198	0	0	0
T29	33778	0	0	0
T36	0	3	0	0
T95	0	12	0	0
T96	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T19
1	0	Covered	T2,T20,T22
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	495970562	3823	0	0
CgEnOn_A	495970562	3821	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970562	3823	0	0
T2	46689	10	0	0
T3	67737	0	0	0
T11	0	28	0	0
T12	0	11	0	0
T13	0	70	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	5	0	0
T22	3911	1	0	0
T23	1511	0	0	0
T28	3198	0	0	0
T29	33778	0	0	0
T36	0	3	0	0
T95	0	6	0	0
T96	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495970562	3821	0	0
T2	46689	10	0	0
T3	67737	0	0	0
T11	0	28	0	0
T12	0	11	0	0
T13	0	70	0	0
T18	1635	0	0	0
T19	207133	0	0	0
T20	4587	1	0	0
T21	1491	5	0	0
T22	3911	1	0	0
T23	1511	0	0	0
T28	3198	0	0	0
T29	33778	0	0	0
T36	0	3	0	0
T95	0	6	0	0
T96	0	4	0	0