Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T21
0	1	Covered	T2,T11,T30
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T22
1	0	Covered	T21,T36,T44
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1051347345	14324	0	0
GateOpen_A	1051347345	14324	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1051347345	14324	0	0
T2	101890	6	0	0
T3	146294	0	0	0
T11	0	182	0	0
T12	0	98	0	0
T13	0	232	0	0
T18	3510	0	0	0
T19	395391	0	0	0
T20	9892	4	0	0
T21	3257	19	0	0
T22	8358	4	0	0
T23	3229	0	0	0
T28	7119	0	0	0
T29	67141	0	0	0
T30	0	25	0	0
T36	0	9	0	0
T99	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1051347345	14324	0	0
T2	101890	6	0	0
T3	146294	0	0	0
T11	0	182	0	0
T12	0	98	0	0
T13	0	232	0	0
T18	3510	0	0	0
T19	395391	0	0	0
T20	9892	4	0	0
T21	3257	19	0	0
T22	8358	4	0	0
T23	3229	0	0	0
T28	7119	0	0	0
T29	67141	0	0	0
T30	0	25	0	0
T36	0	9	0	0
T99	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T21
0	1	Covered	T2,T11,T30
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T22
1	0	Covered	T21,T36,T44
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	115990449	3525	0	0
GateOpen_A	115990449	3525	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115990449	3525	0	0
T2	11553	2	0	0
T3	16251	0	0	0
T11	0	44	0	0
T12	0	24	0	0
T13	0	58	0	0
T18	385	0	0	0
T19	41014	0	0	0
T20	1095	1	0	0
T21	347	5	0	0
T22	909	1	0	0
T23	351	0	0	0
T28	838	0	0	0
T29	6166	0	0	0
T30	0	7	0	0
T36	0	2	0	0
T99	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115990449	3525	0	0
T2	11553	2	0	0
T3	16251	0	0	0
T11	0	44	0	0
T12	0	24	0	0
T13	0	58	0	0
T18	385	0	0	0
T19	41014	0	0	0
T20	1095	1	0	0
T21	347	5	0	0
T22	909	1	0	0
T23	351	0	0	0
T28	838	0	0	0
T29	6166	0	0	0
T30	0	7	0	0
T36	0	2	0	0
T99	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T21
0	1	Covered	T2,T11,T30
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T22
1	0	Covered	T21,T36,T44
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	231981661	3605	0	0
GateOpen_A	231981661	3605	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231981661	3605	0	0
T2	23106	1	0	0
T3	32501	0	0	0
T11	0	50	0	0
T12	0	23	0	0
T13	0	56	0	0
T18	770	0	0	0
T19	82028	0	0	0
T20	2190	1	0	0
T21	693	5	0	0
T22	1817	1	0	0
T23	702	0	0	0
T28	1674	0	0	0
T29	12334	0	0	0
T30	0	7	0	0
T36	0	2	0	0
T99	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231981661	3605	0	0
T2	23106	1	0	0
T3	32501	0	0	0
T11	0	50	0	0
T12	0	23	0	0
T13	0	56	0	0
T18	770	0	0	0
T19	82028	0	0	0
T20	2190	1	0	0
T21	693	5	0	0
T22	1817	1	0	0
T23	702	0	0	0
T28	1674	0	0	0
T29	12334	0	0	0
T30	0	7	0	0
T36	0	2	0	0
T99	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T21
0	1	Covered	T2,T11,T30
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T22
1	0	Covered	T21,T36,T44
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	465364316	3602	0	0
GateOpen_A	465364316	3602	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465364316	3602	0	0
T2	44820	1	0	0
T3	65027	0	0	0
T11	0	44	0	0
T12	0	26	0	0
T13	0	62	0	0
T18	1570	0	0	0
T19	164284	0	0	0
T20	4404	1	0	0
T21	1466	5	0	0
T22	3755	1	0	0
T23	1451	0	0	0
T28	3071	0	0	0
T29	32427	0	0	0
T30	0	6	0	0
T36	0	2	0	0
T99	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465364316	3602	0	0
T2	44820	1	0	0
T3	65027	0	0	0
T11	0	44	0	0
T12	0	26	0	0
T13	0	62	0	0
T18	1570	0	0	0
T19	164284	0	0	0
T20	4404	1	0	0
T21	1466	5	0	0
T22	3755	1	0	0
T23	1451	0	0	0
T28	3071	0	0	0
T29	32427	0	0	0
T30	0	6	0	0
T36	0	2	0	0
T99	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T21
0	1	Covered	T2,T11,T30
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T22
1	0	Covered	T21,T36,T44
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	238010919	3592	0	0
GateOpen_A	238010919	3592	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238010919	3592	0	0
T2	22411	2	0	0
T3	32515	0	0	0
T11	0	44	0	0
T12	0	25	0	0
T13	0	56	0	0
T18	785	0	0	0
T19	108065	0	0	0
T20	2203	1	0	0
T21	751	4	0	0
T22	1877	1	0	0
T23	725	0	0	0
T28	1536	0	0	0
T29	16214	0	0	0
T30	0	5	0	0
T36	0	3	0	0
T99	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238010919	3592	0	0
T2	22411	2	0	0
T3	32515	0	0	0
T11	0	44	0	0
T12	0	25	0	0
T13	0	56	0	0
T18	785	0	0	0
T19	108065	0	0	0
T20	2203	1	0	0
T21	751	4	0	0
T22	1877	1	0	0
T23	725	0	0	0
T28	1536	0	0	0
T29	16214	0	0	0
T30	0	5	0	0
T36	0	3	0	0
T99	0	1	0	0