Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	566337	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3277851

1

T5

14

T6

4

T26

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	946539	1			T5	13		T6	3		T26	32
values[0x0]	1333993	1			T5	12		T6	3		T26	9
values[0x1]	1563656	1			T5	15		T6	4		T26	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	313788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3530400

1

T5

16

T6

4

T26

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15508	1			T28	1		T4	6		T1	4
valid_sources[0x01]	16387	1			T1	17		T3	1		T11	215
valid_sources[0x02]	13975	1			T28	1		T4	2		T1	1
valid_sources[0x03]	14493	1			T28	1		T1	3		T22	1
valid_sources[0x04]	14967	1			T27	1		T4	1		T1	9
valid_sources[0x05]	16185	1			T27	1		T1	2		T22	1
valid_sources[0x06]	15766	1			T27	3		T1	17		T20	2
valid_sources[0x07]	17504	1			T4	1		T1	6		T22	1
valid_sources[0x08]	14769	1			T27	2		T28	2		T4	2
valid_sources[0x09]	14573	1			T28	1		T1	25		T24	1
valid_sources[0x0a]	14275	1			T5	1		T27	3		T4	2
valid_sources[0x0b]	13284	1			T28	2		T4	3		T1	10
valid_sources[0x0c]	15202	1			T28	1		T1	6		T35	1
valid_sources[0x0d]	14349	1			T4	1		T1	1		T22	1
valid_sources[0x0e]	14236	1			T27	3		T28	1		T1	10
valid_sources[0x0f]	14828	1			T27	1		T4	2		T1	8
valid_sources[0x10]	15231	1			T26	2		T4	2		T1	14
valid_sources[0x11]	15957	1			T1	10		T3	1		T11	240
valid_sources[0x12]	14176	1			T5	1		T28	2		T1	1
valid_sources[0x13]	15793	1			T6	2		T28	1		T1	4
valid_sources[0x14]	13642	1			T4	2		T1	8		T35	2
valid_sources[0x15]	15216	1			T4	1		T1	1		T24	2
valid_sources[0x16]	15869	1			T4	2		T1	5		T3	1
valid_sources[0x17]	15232	1			T5	3		T28	1		T4	1
valid_sources[0x18]	14492	1			T1	12		T3	1		T11	204
valid_sources[0x19]	13103	1			T26	6		T1	13		T3	2
valid_sources[0x1a]	16167	1			T28	2		T1	9		T20	5
valid_sources[0x1b]	15935	1			T28	1		T1	14		T22	1
valid_sources[0x1c]	13655	1			T26	10		T29	4		T1	5
valid_sources[0x1d]	16350	1			T4	2		T1	2		T22	1
valid_sources[0x1e]	14455	1			T27	2		T1	2		T22	1
valid_sources[0x1f]	14219	1			T26	2		T28	2		T4	2
valid_sources[0x20]	14146	1			T29	1		T4	1		T1	21
valid_sources[0x21]	14890	1			T28	1		T29	1		T1	13
valid_sources[0x22]	14482	1			T1	9		T22	1		T35	1
valid_sources[0x23]	13385	1			T1	3		T23	1		T24	1
valid_sources[0x24]	16012	1			T1	4		T35	1		T11	266
valid_sources[0x25]	15050	1			T29	2		T1	7		T3	2
valid_sources[0x26]	13672	1			T4	1		T1	4		T3	4
valid_sources[0x27]	13231	1			T28	1		T4	1		T1	1
valid_sources[0x28]	13713	1			T28	1		T4	2		T1	18
valid_sources[0x29]	16839	1			T4	2		T35	2		T3	1
valid_sources[0x2a]	15787	1			T1	7		T11	224		T36	2
valid_sources[0x2b]	14856	1			T28	2		T4	2		T1	4
valid_sources[0x2c]	14492	1			T4	1		T1	6		T35	1
valid_sources[0x2d]	15555	1			T28	1		T4	3		T1	5
valid_sources[0x2e]	16938	1			T28	1		T1	4		T22	1
valid_sources[0x2f]	15720	1			T1	4		T35	1		T3	4
valid_sources[0x30]	15139	1			T28	1		T1	13		T35	1
valid_sources[0x31]	15329	1			T27	1		T4	1		T1	8
valid_sources[0x32]	14783	1			T4	1		T1	3		T22	2
valid_sources[0x33]	13220	1			T28	1		T24	1		T35	1
valid_sources[0x34]	15268	1			T4	1		T1	4		T11	231
valid_sources[0x35]	16456	1			T27	2		T28	1		T4	1
valid_sources[0x36]	14986	1			T27	1		T28	1		T1	14
valid_sources[0x37]	14922	1			T1	6		T22	1		T24	2
valid_sources[0x38]	14073	1			T4	1		T1	7		T20	3
valid_sources[0x39]	14632	1			T4	1		T1	15		T22	1
valid_sources[0x3a]	14847	1			T28	1		T1	5		T35	1
valid_sources[0x3b]	15246	1			T1	6		T24	1		T35	2
valid_sources[0x3c]	15100	1			T28	1		T4	2		T1	1
valid_sources[0x3d]	15112	1			T26	1		T1	4		T11	192
valid_sources[0x3e]	15170	1			T1	15		T22	1		T35	1
valid_sources[0x3f]	15048	1			T28	1		T1	2		T3	1
valid_sources[0x40]	14045	1			T5	2		T4	1		T1	8
valid_sources[0x41]	15734	1			T4	1		T1	6		T24	3
valid_sources[0x42]	14465	1			T27	2		T28	2		T1	12
valid_sources[0x43]	13465	1			T1	7		T3	2		T11	224
valid_sources[0x44]	14739	1			T27	2		T1	8		T20	1
valid_sources[0x45]	14650	1			T28	1		T4	1		T1	5
valid_sources[0x46]	14430	1			T28	1		T1	4		T24	1
valid_sources[0x47]	13996	1			T27	2		T1	7		T3	4
valid_sources[0x48]	13325	1			T28	1		T1	3		T3	2
valid_sources[0x49]	14298	1			T27	2		T1	2		T35	3
valid_sources[0x4a]	14707	1			T1	1		T41	2		T42	6
valid_sources[0x4b]	15239	1			T27	1		T4	2		T1	15
valid_sources[0x4c]	13689	1			T4	1		T1	5		T11	199
valid_sources[0x4d]	15374	1			T4	1		T1	6		T20	3
valid_sources[0x4e]	15570	1			T28	1		T1	4		T42	2
valid_sources[0x4f]	15159	1			T1	2		T20	1		T3	2
valid_sources[0x50]	14544	1			T27	2		T4	2		T1	10
valid_sources[0x51]	16148	1			T26	1		T28	1		T1	3
valid_sources[0x52]	16300	1			T5	3		T1	2		T3	1
valid_sources[0x53]	14138	1			T1	4		T23	1		T35	1
valid_sources[0x54]	15410	1			T28	1		T20	9		T22	1
valid_sources[0x55]	15333	1			T1	4		T22	1		T24	1
valid_sources[0x56]	15056	1			T1	11		T42	7		T11	193
valid_sources[0x57]	14169	1			T5	2		T28	1		T4	1
valid_sources[0x58]	17129	1			T27	1		T29	4		T4	1
valid_sources[0x59]	15377	1			T5	1		T28	1		T4	3
valid_sources[0x5a]	14492	1			T27	1		T4	1		T1	5
valid_sources[0x5b]	15787	1			T1	2		T35	1		T3	4
valid_sources[0x5c]	14204	1			T1	12		T20	2		T22	3
valid_sources[0x5d]	13773	1			T27	2		T1	6		T20	3
valid_sources[0x5e]	14443	1			T1	17		T23	1		T3	5
valid_sources[0x5f]	14684	1			T28	1		T1	6		T11	188
valid_sources[0x60]	16532	1			T27	1		T3	1		T11	161
valid_sources[0x61]	12752	1			T28	1		T1	11		T24	1
valid_sources[0x62]	14383	1			T28	1		T29	1		T24	1
valid_sources[0x63]	15315	1			T4	2		T41	2		T11	224
valid_sources[0x64]	15343	1			T4	5		T1	8		T3	5
valid_sources[0x65]	15415	1			T26	3		T27	1		T28	1
valid_sources[0x66]	14772	1			T5	2		T27	1		T4	1
valid_sources[0x67]	14597	1			T1	1		T20	2		T22	1
valid_sources[0x68]	17040	1			T28	1		T1	4		T24	1
valid_sources[0x69]	15382	1			T1	2		T22	1		T35	1
valid_sources[0x6a]	14341	1			T27	1		T4	1		T3	1
valid_sources[0x6b]	14808	1			T6	1		T27	5		T4	2
valid_sources[0x6c]	16018	1			T1	11		T22	1		T3	1
valid_sources[0x6d]	15247	1			T28	1		T4	1		T1	15
valid_sources[0x6e]	15655	1			T27	1		T4	4		T1	7
valid_sources[0x6f]	14797	1			T5	2		T28	2		T4	1
valid_sources[0x70]	15467	1			T5	1		T1	9		T20	3
valid_sources[0x71]	14202	1			T1	3		T24	1		T3	8
valid_sources[0x72]	16310	1			T4	2		T1	3		T11	185
valid_sources[0x73]	18119	1			T5	1		T6	2		T4	1
valid_sources[0x74]	14519	1			T6	1		T27	3		T1	4
valid_sources[0x75]	14233	1			T28	1		T1	1		T20	4
valid_sources[0x76]	16036	1			T1	2		T22	1		T35	2
valid_sources[0x77]	14368	1			T5	3		T27	1		T1	10
valid_sources[0x78]	15481	1			T27	2		T1	5		T35	4
valid_sources[0x79]	15150	1			T1	1		T35	1		T3	4
valid_sources[0x7a]	16682	1			T4	1		T1	10		T3	2
valid_sources[0x7b]	16347	1			T27	1		T1	6		T22	1
valid_sources[0x7c]	15142	1			T29	8		T4	2		T1	3
valid_sources[0x7d]	15598	1			T4	1		T1	12		T24	1
valid_sources[0x7e]	14423	1			T4	2		T1	5		T24	2
valid_sources[0x7f]	16396	1			T4	1		T1	8		T22	1
valid_sources[0x80]	14790	1			T1	7		T23	1		T25	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

827242

1

T5

6

T6

3

T26

20

values[0x0]

all_enables

biggest_size

1247276

1

T5

6

T6

1

T26

2

values[0x1]

all_enables

biggest_size

1203333

1

T5

2

T26

2

T27

2