Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	725349870	77138	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725349870	77138	0	0
T1	680170	219	0	0
T2	563595	184	0	0
T3	0	360	0	0
T11	0	1288	0	0
T12	0	157	0	0
T13	0	2122	0	0
T14	0	180	0	0
T15	0	191	0	0
T16	0	330	0	0
T17	0	1090	0	0
T18	5000	0	0	0
T19	8605	0	0	0
T20	8275	0	0	0
T21	7295	0	0	0
T22	11910	0	0	0
T23	7220	0	0	0
T24	9575	0	0	0
T25	889865	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145069974	11149	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145069974	11149	0	0
T1	136034	34	0	0
T2	112719	24	0	0
T3	0	52	0	0
T11	0	170	0	0
T12	0	23	0	0
T13	0	271	0	0
T14	0	23	0	0
T15	0	28	0	0
T16	0	53	0	0
T17	0	175	0	0
T18	1000	0	0	0
T19	1721	0	0	0
T20	1655	0	0	0
T21	1459	0	0	0
T22	2382	0	0	0
T23	1444	0	0	0
T24	1915	0	0	0
T25	177973	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145069974	15462	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145069974	15462	0	0
T1	136034	44	0	0
T2	112719	37	0	0
T3	0	72	0	0
T11	0	253	0	0
T12	0	32	0	0
T13	0	425	0	0
T14	0	36	0	0
T15	0	40	0	0
T16	0	67	0	0
T17	0	216	0	0
T18	1000	0	0	0
T19	1721	0	0	0
T20	1655	0	0	0
T21	1459	0	0	0
T22	2382	0	0	0
T23	1444	0	0	0
T24	1915	0	0	0
T25	177973	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145069974	23929	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145069974	23929	0	0
T1	136034	63	0	0
T2	112719	63	0	0
T3	0	113	0	0
T11	0	425	0	0
T12	0	47	0	0
T13	0	695	0	0
T14	0	58	0	0
T15	0	62	0	0
T16	0	90	0	0
T17	0	310	0	0
T18	1000	0	0	0
T19	1721	0	0	0
T20	1655	0	0	0
T21	1459	0	0	0
T22	2382	0	0	0
T23	1444	0	0	0
T24	1915	0	0	0
T25	177973	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145069974	11110	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145069974	11110	0	0
T1	136034	34	0	0
T2	112719	23	0	0
T3	0	52	0	0
T11	0	186	0	0
T12	0	23	0	0
T13	0	307	0	0
T14	0	26	0	0
T15	0	23	0	0
T16	0	53	0	0
T17	0	173	0	0
T18	1000	0	0	0
T19	1721	0	0	0
T20	1655	0	0	0
T21	1459	0	0	0
T22	2382	0	0	0
T23	1444	0	0	0
T24	1915	0	0	0
T25	177973	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145069974	15488	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145069974	15488	0	0
T1	136034	44	0	0
T2	112719	37	0	0
T3	0	71	0	0
T11	0	254	0	0
T12	0	32	0	0
T13	0	424	0	0
T14	0	37	0	0
T15	0	38	0	0
T16	0	67	0	0
T17	0	216	0	0
T18	1000	0	0	0
T19	1721	0	0	0
T20	1655	0	0	0
T21	1459	0	0	0
T22	2382	0	0	0
T23	1444	0	0	0
T24	1915	0	0	0
T25	177973	0	0	0