Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22484 |
22484 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T26 |
28 |
28 |
0 |
0 |
T27 |
28 |
28 |
0 |
0 |
T28 |
28 |
28 |
0 |
0 |
T29 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
8487936 |
8473942 |
0 |
0 |
T4 |
384697 |
110637 |
0 |
0 |
T5 |
54596 |
51612 |
0 |
0 |
T6 |
71680 |
69236 |
0 |
0 |
T7 |
42063 |
38449 |
0 |
0 |
T18 |
37519 |
36594 |
0 |
0 |
T26 |
83621 |
80111 |
0 |
0 |
T27 |
296138 |
293833 |
0 |
0 |
T28 |
115753 |
113400 |
0 |
0 |
T29 |
125957 |
123844 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
870419844 |
854761686 |
0 |
14454 |
T1 |
816204 |
814620 |
0 |
18 |
T4 |
34062 |
6774 |
0 |
18 |
T5 |
12402 |
11646 |
0 |
18 |
T6 |
5736 |
5484 |
0 |
18 |
T7 |
9912 |
8982 |
0 |
18 |
T18 |
6000 |
5820 |
0 |
18 |
T26 |
8034 |
7638 |
0 |
18 |
T27 |
15456 |
15294 |
0 |
18 |
T28 |
11460 |
11184 |
0 |
18 |
T29 |
12024 |
11778 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2134300331 |
2107630829 |
0 |
16863 |
T1 |
2971144 |
2965358 |
0 |
21 |
T4 |
139376 |
27900 |
0 |
21 |
T5 |
14598 |
13706 |
0 |
21 |
T6 |
25646 |
24570 |
0 |
21 |
T7 |
11041 |
9948 |
0 |
21 |
T18 |
11643 |
11300 |
0 |
21 |
T26 |
29269 |
27857 |
0 |
21 |
T27 |
111609 |
110562 |
0 |
21 |
T28 |
40276 |
39331 |
0 |
21 |
T29 |
43787 |
42926 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2134300331 |
186878 |
0 |
0 |
T1 |
2971144 |
453 |
0 |
0 |
T4 |
139376 |
20 |
0 |
0 |
T5 |
14598 |
126 |
0 |
0 |
T6 |
25646 |
37 |
0 |
0 |
T7 |
11041 |
23 |
0 |
0 |
T18 |
11643 |
25 |
0 |
0 |
T19 |
0 |
151 |
0 |
0 |
T21 |
0 |
23 |
0 |
0 |
T22 |
0 |
155 |
0 |
0 |
T23 |
0 |
66 |
0 |
0 |
T26 |
29269 |
51 |
0 |
0 |
T27 |
111609 |
120 |
0 |
0 |
T28 |
40276 |
20 |
0 |
0 |
T29 |
43787 |
175 |
0 |
0 |
T40 |
0 |
16 |
0 |
0 |
T41 |
0 |
71 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
4700588 |
4693730 |
0 |
0 |
T4 |
211259 |
75768 |
0 |
0 |
T5 |
27596 |
26221 |
0 |
0 |
T6 |
40298 |
39143 |
0 |
0 |
T7 |
21110 |
19480 |
0 |
0 |
T18 |
19876 |
19435 |
0 |
0 |
T26 |
46318 |
44577 |
0 |
0 |
T27 |
169073 |
167938 |
0 |
0 |
T28 |
64017 |
62846 |
0 |
0 |
T29 |
70146 |
69101 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T29 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T29 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T29 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T29 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T29 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349742487 |
345650175 |
0 |
0 |
T1 |
503808 |
502808 |
0 |
0 |
T4 |
24778 |
4977 |
0 |
0 |
T5 |
2024 |
1903 |
0 |
0 |
T6 |
4594 |
4405 |
0 |
0 |
T7 |
1569 |
1421 |
0 |
0 |
T18 |
1871 |
1819 |
0 |
0 |
T26 |
5147 |
4902 |
0 |
0 |
T27 |
20605 |
20415 |
0 |
0 |
T28 |
7056 |
6894 |
0 |
0 |
T29 |
7699 |
7551 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349742487 |
345643323 |
0 |
2409 |
T1 |
503808 |
502790 |
0 |
3 |
T4 |
24778 |
4962 |
0 |
3 |
T5 |
2024 |
1900 |
0 |
3 |
T6 |
4594 |
4402 |
0 |
3 |
T7 |
1569 |
1418 |
0 |
3 |
T18 |
1871 |
1816 |
0 |
3 |
T26 |
5147 |
4899 |
0 |
3 |
T27 |
20605 |
20412 |
0 |
3 |
T28 |
7056 |
6891 |
0 |
3 |
T29 |
7699 |
7548 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349742487 |
26693 |
0 |
0 |
T1 |
503808 |
89 |
0 |
0 |
T4 |
24778 |
0 |
0 |
0 |
T5 |
2024 |
30 |
0 |
0 |
T6 |
4594 |
9 |
0 |
0 |
T7 |
1569 |
0 |
0 |
0 |
T18 |
1871 |
0 |
0 |
0 |
T19 |
0 |
76 |
0 |
0 |
T21 |
0 |
7 |
0 |
0 |
T22 |
0 |
53 |
0 |
0 |
T23 |
0 |
38 |
0 |
0 |
T26 |
5147 |
0 |
0 |
0 |
T27 |
20605 |
0 |
0 |
0 |
T28 |
7056 |
0 |
0 |
0 |
T29 |
7699 |
42 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
T41 |
0 |
33 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T29 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T29 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T29 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T29 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T29 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142460281 |
0 |
2409 |
T1 |
136034 |
135770 |
0 |
3 |
T4 |
5677 |
1129 |
0 |
3 |
T5 |
2067 |
1941 |
0 |
3 |
T6 |
956 |
914 |
0 |
3 |
T7 |
1652 |
1497 |
0 |
3 |
T18 |
1000 |
970 |
0 |
3 |
T26 |
1339 |
1273 |
0 |
3 |
T27 |
2576 |
2549 |
0 |
3 |
T28 |
1910 |
1864 |
0 |
3 |
T29 |
2004 |
1963 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
16477 |
0 |
0 |
T1 |
136034 |
50 |
0 |
0 |
T4 |
5677 |
0 |
0 |
0 |
T5 |
2067 |
13 |
0 |
0 |
T6 |
956 |
10 |
0 |
0 |
T7 |
1652 |
0 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
0 |
36 |
0 |
0 |
T21 |
0 |
12 |
0 |
0 |
T22 |
0 |
49 |
0 |
0 |
T23 |
0 |
16 |
0 |
0 |
T26 |
1339 |
0 |
0 |
0 |
T27 |
2576 |
0 |
0 |
0 |
T28 |
1910 |
0 |
0 |
0 |
T29 |
2004 |
35 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T41 |
0 |
23 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T29 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T29 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T29 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T29 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T29 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142460281 |
0 |
2409 |
T1 |
136034 |
135770 |
0 |
3 |
T4 |
5677 |
1129 |
0 |
3 |
T5 |
2067 |
1941 |
0 |
3 |
T6 |
956 |
914 |
0 |
3 |
T7 |
1652 |
1497 |
0 |
3 |
T18 |
1000 |
970 |
0 |
3 |
T26 |
1339 |
1273 |
0 |
3 |
T27 |
2576 |
2549 |
0 |
3 |
T28 |
1910 |
1864 |
0 |
3 |
T29 |
2004 |
1963 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
18707 |
0 |
0 |
T1 |
136034 |
58 |
0 |
0 |
T4 |
5677 |
0 |
0 |
0 |
T5 |
2067 |
27 |
0 |
0 |
T6 |
956 |
2 |
0 |
0 |
T7 |
1652 |
0 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
0 |
39 |
0 |
0 |
T21 |
0 |
4 |
0 |
0 |
T22 |
0 |
53 |
0 |
0 |
T23 |
0 |
12 |
0 |
0 |
T26 |
1339 |
0 |
0 |
0 |
T27 |
2576 |
0 |
0 |
0 |
T28 |
1910 |
0 |
0 |
0 |
T29 |
2004 |
30 |
0 |
0 |
T40 |
0 |
4 |
0 |
0 |
T41 |
0 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
371441121 |
0 |
0 |
T1 |
548817 |
548318 |
0 |
0 |
T4 |
25811 |
15242 |
0 |
0 |
T5 |
2110 |
2055 |
0 |
0 |
T6 |
4785 |
4730 |
0 |
0 |
T7 |
1542 |
1501 |
0 |
0 |
T18 |
1943 |
1917 |
0 |
0 |
T26 |
5361 |
5220 |
0 |
0 |
T27 |
21463 |
21380 |
0 |
0 |
T28 |
7350 |
7253 |
0 |
0 |
T29 |
8020 |
7937 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
371441121 |
0 |
0 |
T1 |
548817 |
548318 |
0 |
0 |
T4 |
25811 |
15242 |
0 |
0 |
T5 |
2110 |
2055 |
0 |
0 |
T6 |
4785 |
4730 |
0 |
0 |
T7 |
1542 |
1501 |
0 |
0 |
T18 |
1943 |
1917 |
0 |
0 |
T26 |
5361 |
5220 |
0 |
0 |
T27 |
21463 |
21380 |
0 |
0 |
T28 |
7350 |
7253 |
0 |
0 |
T29 |
8020 |
7937 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349742487 |
347692746 |
0 |
0 |
T1 |
503808 |
503330 |
0 |
0 |
T4 |
24778 |
14631 |
0 |
0 |
T5 |
2024 |
1972 |
0 |
0 |
T6 |
4594 |
4542 |
0 |
0 |
T7 |
1569 |
1531 |
0 |
0 |
T18 |
1871 |
1846 |
0 |
0 |
T26 |
5147 |
5012 |
0 |
0 |
T27 |
20605 |
20525 |
0 |
0 |
T28 |
7056 |
6963 |
0 |
0 |
T29 |
7699 |
7620 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349742487 |
347692746 |
0 |
0 |
T1 |
503808 |
503330 |
0 |
0 |
T4 |
24778 |
14631 |
0 |
0 |
T5 |
2024 |
1972 |
0 |
0 |
T6 |
4594 |
4542 |
0 |
0 |
T7 |
1569 |
1531 |
0 |
0 |
T18 |
1871 |
1846 |
0 |
0 |
T26 |
5147 |
5012 |
0 |
0 |
T27 |
20605 |
20525 |
0 |
0 |
T28 |
7056 |
6963 |
0 |
0 |
T29 |
7699 |
7620 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174074563 |
174074563 |
0 |
0 |
T1 |
252544 |
252544 |
0 |
0 |
T4 |
7317 |
7317 |
0 |
0 |
T5 |
1073 |
1073 |
0 |
0 |
T6 |
2498 |
2498 |
0 |
0 |
T7 |
766 |
766 |
0 |
0 |
T18 |
923 |
923 |
0 |
0 |
T26 |
2506 |
2506 |
0 |
0 |
T27 |
10263 |
10263 |
0 |
0 |
T28 |
3482 |
3482 |
0 |
0 |
T29 |
4317 |
4317 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174074563 |
174074563 |
0 |
0 |
T1 |
252544 |
252544 |
0 |
0 |
T4 |
7317 |
7317 |
0 |
0 |
T5 |
1073 |
1073 |
0 |
0 |
T6 |
2498 |
2498 |
0 |
0 |
T7 |
766 |
766 |
0 |
0 |
T18 |
923 |
923 |
0 |
0 |
T26 |
2506 |
2506 |
0 |
0 |
T27 |
10263 |
10263 |
0 |
0 |
T28 |
3482 |
3482 |
0 |
0 |
T29 |
4317 |
4317 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
87036675 |
87036675 |
0 |
0 |
T1 |
126270 |
126270 |
0 |
0 |
T4 |
3658 |
3658 |
0 |
0 |
T5 |
535 |
535 |
0 |
0 |
T6 |
1248 |
1248 |
0 |
0 |
T7 |
383 |
383 |
0 |
0 |
T18 |
462 |
462 |
0 |
0 |
T26 |
1253 |
1253 |
0 |
0 |
T27 |
5131 |
5131 |
0 |
0 |
T28 |
1741 |
1741 |
0 |
0 |
T29 |
2157 |
2157 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
87036675 |
87036675 |
0 |
0 |
T1 |
126270 |
126270 |
0 |
0 |
T4 |
3658 |
3658 |
0 |
0 |
T5 |
535 |
535 |
0 |
0 |
T6 |
1248 |
1248 |
0 |
0 |
T7 |
383 |
383 |
0 |
0 |
T18 |
462 |
462 |
0 |
0 |
T26 |
1253 |
1253 |
0 |
0 |
T27 |
5131 |
5131 |
0 |
0 |
T28 |
1741 |
1741 |
0 |
0 |
T29 |
2157 |
2157 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
179303053 |
178267366 |
0 |
0 |
T1 |
257677 |
257440 |
0 |
0 |
T4 |
12389 |
7316 |
0 |
0 |
T5 |
1012 |
986 |
0 |
0 |
T6 |
2297 |
2271 |
0 |
0 |
T7 |
770 |
751 |
0 |
0 |
T18 |
905 |
893 |
0 |
0 |
T26 |
2573 |
2506 |
0 |
0 |
T27 |
10303 |
10263 |
0 |
0 |
T28 |
3528 |
3481 |
0 |
0 |
T29 |
3849 |
3810 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
179303053 |
178267366 |
0 |
0 |
T1 |
257677 |
257440 |
0 |
0 |
T4 |
12389 |
7316 |
0 |
0 |
T5 |
1012 |
986 |
0 |
0 |
T6 |
2297 |
2271 |
0 |
0 |
T7 |
770 |
751 |
0 |
0 |
T18 |
905 |
893 |
0 |
0 |
T26 |
2573 |
2506 |
0 |
0 |
T27 |
10303 |
10263 |
0 |
0 |
T28 |
3528 |
3481 |
0 |
0 |
T29 |
3849 |
3810 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142460281 |
0 |
2409 |
T1 |
136034 |
135770 |
0 |
3 |
T4 |
5677 |
1129 |
0 |
3 |
T5 |
2067 |
1941 |
0 |
3 |
T6 |
956 |
914 |
0 |
3 |
T7 |
1652 |
1497 |
0 |
3 |
T18 |
1000 |
970 |
0 |
3 |
T26 |
1339 |
1273 |
0 |
3 |
T27 |
2576 |
2549 |
0 |
3 |
T28 |
1910 |
1864 |
0 |
3 |
T29 |
2004 |
1963 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142460281 |
0 |
2409 |
T1 |
136034 |
135770 |
0 |
3 |
T4 |
5677 |
1129 |
0 |
3 |
T5 |
2067 |
1941 |
0 |
3 |
T6 |
956 |
914 |
0 |
3 |
T7 |
1652 |
1497 |
0 |
3 |
T18 |
1000 |
970 |
0 |
3 |
T26 |
1339 |
1273 |
0 |
3 |
T27 |
2576 |
2549 |
0 |
3 |
T28 |
1910 |
1864 |
0 |
3 |
T29 |
2004 |
1963 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142460281 |
0 |
2409 |
T1 |
136034 |
135770 |
0 |
3 |
T4 |
5677 |
1129 |
0 |
3 |
T5 |
2067 |
1941 |
0 |
3 |
T6 |
956 |
914 |
0 |
3 |
T7 |
1652 |
1497 |
0 |
3 |
T18 |
1000 |
970 |
0 |
3 |
T26 |
1339 |
1273 |
0 |
3 |
T27 |
2576 |
2549 |
0 |
3 |
T28 |
1910 |
1864 |
0 |
3 |
T29 |
2004 |
1963 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142460281 |
0 |
2409 |
T1 |
136034 |
135770 |
0 |
3 |
T4 |
5677 |
1129 |
0 |
3 |
T5 |
2067 |
1941 |
0 |
3 |
T6 |
956 |
914 |
0 |
3 |
T7 |
1652 |
1497 |
0 |
3 |
T18 |
1000 |
970 |
0 |
3 |
T26 |
1339 |
1273 |
0 |
3 |
T27 |
2576 |
2549 |
0 |
3 |
T28 |
1910 |
1864 |
0 |
3 |
T29 |
2004 |
1963 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142460281 |
0 |
2409 |
T1 |
136034 |
135770 |
0 |
3 |
T4 |
5677 |
1129 |
0 |
3 |
T5 |
2067 |
1941 |
0 |
3 |
T6 |
956 |
914 |
0 |
3 |
T7 |
1652 |
1497 |
0 |
3 |
T18 |
1000 |
970 |
0 |
3 |
T26 |
1339 |
1273 |
0 |
3 |
T27 |
2576 |
2549 |
0 |
3 |
T28 |
1910 |
1864 |
0 |
3 |
T29 |
2004 |
1963 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142460281 |
0 |
2409 |
T1 |
136034 |
135770 |
0 |
3 |
T4 |
5677 |
1129 |
0 |
3 |
T5 |
2067 |
1941 |
0 |
3 |
T6 |
956 |
914 |
0 |
3 |
T7 |
1652 |
1497 |
0 |
3 |
T18 |
1000 |
970 |
0 |
3 |
T26 |
1339 |
1273 |
0 |
3 |
T27 |
2576 |
2549 |
0 |
3 |
T28 |
1910 |
1864 |
0 |
3 |
T29 |
2004 |
1963 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145069974 |
142467289 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369273632 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369266736 |
0 |
2409 |
T1 |
548817 |
547757 |
0 |
3 |
T4 |
25811 |
5170 |
0 |
3 |
T5 |
2110 |
1981 |
0 |
3 |
T6 |
4785 |
4585 |
0 |
3 |
T7 |
1542 |
1384 |
0 |
3 |
T18 |
1943 |
1886 |
0 |
3 |
T26 |
5361 |
5103 |
0 |
3 |
T27 |
21463 |
21263 |
0 |
3 |
T28 |
7350 |
7178 |
0 |
3 |
T29 |
8020 |
7863 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
31267 |
0 |
0 |
T1 |
548817 |
64 |
0 |
0 |
T4 |
25811 |
5 |
0 |
0 |
T5 |
2110 |
20 |
0 |
0 |
T6 |
4785 |
6 |
0 |
0 |
T7 |
1542 |
4 |
0 |
0 |
T18 |
1943 |
7 |
0 |
0 |
T26 |
5361 |
18 |
0 |
0 |
T27 |
21463 |
25 |
0 |
0 |
T28 |
7350 |
5 |
0 |
0 |
T29 |
8020 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369273632 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369273632 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369273632 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369266736 |
0 |
2409 |
T1 |
548817 |
547757 |
0 |
3 |
T4 |
25811 |
5170 |
0 |
3 |
T5 |
2110 |
1981 |
0 |
3 |
T6 |
4785 |
4585 |
0 |
3 |
T7 |
1542 |
1384 |
0 |
3 |
T18 |
1943 |
1886 |
0 |
3 |
T26 |
5361 |
5103 |
0 |
3 |
T27 |
21463 |
21263 |
0 |
3 |
T28 |
7350 |
7178 |
0 |
3 |
T29 |
8020 |
7863 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
31331 |
0 |
0 |
T1 |
548817 |
68 |
0 |
0 |
T4 |
25811 |
5 |
0 |
0 |
T5 |
2110 |
8 |
0 |
0 |
T6 |
4785 |
4 |
0 |
0 |
T7 |
1542 |
4 |
0 |
0 |
T18 |
1943 |
4 |
0 |
0 |
T26 |
5361 |
9 |
0 |
0 |
T27 |
21463 |
37 |
0 |
0 |
T28 |
7350 |
5 |
0 |
0 |
T29 |
8020 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369273632 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369273632 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369273632 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369266736 |
0 |
2409 |
T1 |
548817 |
547757 |
0 |
3 |
T4 |
25811 |
5170 |
0 |
3 |
T5 |
2110 |
1981 |
0 |
3 |
T6 |
4785 |
4585 |
0 |
3 |
T7 |
1542 |
1384 |
0 |
3 |
T18 |
1943 |
1886 |
0 |
3 |
T26 |
5361 |
5103 |
0 |
3 |
T27 |
21463 |
21263 |
0 |
3 |
T28 |
7350 |
7178 |
0 |
3 |
T29 |
8020 |
7863 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
31131 |
0 |
0 |
T1 |
548817 |
64 |
0 |
0 |
T4 |
25811 |
5 |
0 |
0 |
T5 |
2110 |
12 |
0 |
0 |
T6 |
4785 |
3 |
0 |
0 |
T7 |
1542 |
4 |
0 |
0 |
T18 |
1943 |
7 |
0 |
0 |
T26 |
5361 |
12 |
0 |
0 |
T27 |
21463 |
41 |
0 |
0 |
T28 |
7350 |
5 |
0 |
0 |
T29 |
8020 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369273632 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369273632 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369273632 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369266736 |
0 |
2409 |
T1 |
548817 |
547757 |
0 |
3 |
T4 |
25811 |
5170 |
0 |
3 |
T5 |
2110 |
1981 |
0 |
3 |
T6 |
4785 |
4585 |
0 |
3 |
T7 |
1542 |
1384 |
0 |
3 |
T18 |
1943 |
1886 |
0 |
3 |
T26 |
5361 |
5103 |
0 |
3 |
T27 |
21463 |
21263 |
0 |
3 |
T28 |
7350 |
7178 |
0 |
3 |
T29 |
8020 |
7863 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
31272 |
0 |
0 |
T1 |
548817 |
60 |
0 |
0 |
T4 |
25811 |
5 |
0 |
0 |
T5 |
2110 |
16 |
0 |
0 |
T6 |
4785 |
3 |
0 |
0 |
T7 |
1542 |
11 |
0 |
0 |
T18 |
1943 |
7 |
0 |
0 |
T26 |
5361 |
12 |
0 |
0 |
T27 |
21463 |
17 |
0 |
0 |
T28 |
7350 |
5 |
0 |
0 |
T29 |
8020 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369273632 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373604474 |
369273632 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |