Line Coverage for Module :
prim_generic_clock_div ( parameter Divisor=2,ResetValue=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
27 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
72 |
1 |
1 |
Line Coverage for Module :
prim_generic_clock_div ( parameter Divisor=4,ResetValue=0,gen_div.ToggleCnt=2,gen_div.CntWidth=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 12 | 12 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
ALWAYS | 85 | 7 | 7 | 100.00 |
ALWAYS | 97 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
27 |
1 |
1 |
81 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
98 |
1 |
1 |
100 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_div ( parameter Divisor=2,ResetValue=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 27
EXPRESSION (test_en_i ? '0 : step_down_req_i)
----1----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T26,T27 |
Cond Coverage for Module :
prim_generic_clock_div ( parameter Divisor=4,ResetValue=0,gen_div.ToggleCnt=2,gen_div.CntWidth=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 4 | 4 | 100.00 |
Logical | 4 | 4 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 27
EXPRESSION (test_en_i ? '0 : step_down_req_i)
----1----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T26,T27 |
LINE 81
EXPRESSION (((!step_down_req)) ? (1'((gen_div.ToggleCnt - 1))) : ((((gen_div.ToggleCnt / 2) == 2) ? '0 : 1'(((gen_div.ToggleCnt / 2) - 1)))))
---------1--------
-1- | Status | Tests |
0 | Covered | T5,T6,T29 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Module :
prim_generic_clock_div ( parameter Divisor=2,ResetValue=0 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
TERNARY |
27 |
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 27 (test_en_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T26,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Branch Coverage for Module :
prim_generic_clock_div ( parameter Divisor=4,ResetValue=0,gen_div.ToggleCnt=2,gen_div.CntWidth=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
27 |
2 |
2 |
100.00 |
TERNARY |
81 |
2 |
2 |
100.00 |
IF |
85 |
3 |
3 |
100.00 |
IF |
97 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 27 (test_en_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T26,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 81 ((!step_down_req)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T29 |
LineNo. Expression
-1-: 85 if ((!rst_ni))
-2-: 88 if ((gen_div.cnt >= gen_div.limit))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T5,T6,T7 |
0 |
1 |
Covered |
T5,T6,T7 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 97 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_generic_clock_div
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
DivEven_A |
1606 |
1606 |
0 |
0 |
DivEven_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1606 |
1606 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T4 |
2 |
2 |
0 |
0 |
T5 |
2 |
2 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T7 |
2 |
2 |
0 |
0 |
T18 |
2 |
2 |
0 |
0 |
T26 |
2 |
2 |
0 |
0 |
T27 |
2 |
2 |
0 |
0 |
T28 |
2 |
2 |
0 |
0 |
T29 |
2 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
27 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 27
EXPRESSION (test_en_i ? '0 : step_down_req_i)
----1----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T26,T27 |
Branch Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
TERNARY |
27 |
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 27 (test_en_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T26,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
DivEven_A |
803 |
803 |
0 |
0 |
DivEven_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 12 | 12 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
ALWAYS | 85 | 7 | 7 | 100.00 |
ALWAYS | 97 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
27 |
1 |
1 |
81 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
98 |
1 |
1 |
100 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 4 | 4 | 100.00 |
Logical | 4 | 4 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 27
EXPRESSION (test_en_i ? '0 : step_down_req_i)
----1----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T26,T27 |
LINE 81
EXPRESSION (((!step_down_req)) ? (1'((gen_div.ToggleCnt - 1))) : ((((gen_div.ToggleCnt / 2) == 2) ? '0 : 1'(((gen_div.ToggleCnt / 2) - 1)))))
---------1--------
-1- | Status | Tests |
0 | Covered | T5,T6,T29 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
27 |
2 |
2 |
100.00 |
TERNARY |
81 |
2 |
2 |
100.00 |
IF |
85 |
3 |
3 |
100.00 |
IF |
97 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 27 (test_en_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T26,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 81 ((!step_down_req)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T29 |
LineNo. Expression
-1-: 85 if ((!rst_ni))
-2-: 88 if ((gen_div.cnt >= gen_div.limit))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T5,T6,T7 |
0 |
1 |
Covered |
T5,T6,T7 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 97 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
DivEven_A |
803 |
803 |
0 |
0 |
DivEven_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
803 |
803 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |