Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T11

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	145069974	142334386	0	0
AllClkBypReqTrue_A	145069974	130619	0	0
IoClkBypReqFalse_A	145069974	142256522	0	2409
IoClkBypReqTrue_A	145069974	203915	0	0
LcClkBypAckFalse_A	145069974	142347115	0	0
LcClkBypAckTrue_A	145069974	117890	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145069974	142334386	0	0
T1	136034	135348	0	0
T4	5677	1139	0	0
T5	2067	1841	0	0
T6	956	916	0	0
T7	1652	1499	0	0
T18	1000	972	0	0
T26	1339	1275	0	0
T27	2576	2551	0	0
T28	1910	1866	0	0
T29	2004	1649	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145069974	130619	0	0
T1	136034	434	0	0
T4	5677	0	0	0
T5	2067	102	0	0
T6	956	0	0	0
T7	1652	0	0	0
T18	1000	0	0	0
T19	0	204	0	0
T22	0	137	0	0
T23	0	117	0	0
T26	1339	0	0	0
T27	2576	0	0	0
T28	1910	0	0	0
T29	2004	316	0	0
T40	0	15	0	0
T42	0	93	0	0
T43	0	34	0	0
T131	0	49	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145069974	142256522	0	2409
T1	136034	135133	0	3
T4	5677	1129	0	3
T5	2067	1838	0	3
T6	956	785	0	3
T7	1652	1497	0	3
T18	1000	970	0	3
T26	1339	1273	0	3
T27	2576	2549	0	3
T28	1910	1864	0	3
T29	2004	1503	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145069974	203915	0	0
T1	136034	637	0	0
T4	5677	0	0	0
T5	2067	103	0	0
T6	956	129	0	0
T7	1652	0	0	0
T18	1000	0	0	0
T19	0	329	0	0
T21	0	58	0	0
T22	0	248	0	0
T23	0	227	0	0
T26	1339	0	0	0
T27	2576	0	0	0
T28	1910	0	0	0
T29	2004	460	0	0
T40	0	40	0	0
T41	0	350	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145069974	142347115	0	0
T1	136034	135444	0	0
T4	5677	1139	0	0
T5	2067	1903	0	0
T6	956	830	0	0
T7	1652	1499	0	0
T18	1000	972	0	0
T26	1339	1275	0	0
T27	2576	2551	0	0
T28	1910	1866	0	0
T29	2004	1753	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145069974	117890	0	0
T1	136034	338	0	0
T4	5677	0	0	0
T5	2067	40	0	0
T6	956	86	0	0
T7	1652	0	0	0
T18	1000	0	0	0
T19	0	179	0	0
T21	0	20	0	0
T22	0	98	0	0
T23	0	83	0	0
T26	1339	0	0	0
T27	2576	0	0	0
T28	1910	0	0	0
T29	2004	212	0	0
T40	0	3	0	0
T41	0	83	0	0