Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1494419624	14330	0	0
TransStop_A	1494419624	7542	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494419624	14330	0	0
T1	2195268	24	0	0
T4	103244	0	0	0
T11	0	208	0	0
T18	7772	0	0	0
T19	28696	0	0	0
T20	27592	25	0	0
T21	6792	0	0	0
T24	0	4	0	0
T26	21448	14	0	0
T27	85856	28	0	0
T28	29404	4	0	0
T29	32080	0	0	0
T90	0	4	0	0
T132	0	20	0	0
T133	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494419624	7542	0	0
T1	2195268	12	0	0
T4	103244	0	0	0
T11	0	105	0	0
T18	7772	0	0	0
T19	28696	0	0	0
T20	27592	9	0	0
T21	6792	0	0	0
T22	2430	0	0	0
T24	0	4	0	0
T26	16086	4	0	0
T27	85856	15	0	0
T28	29404	4	0	0
T29	32080	0	0	0
T90	0	4	0	0
T132	0	14	0	0
T133	0	4	0	0
T134	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	373604906	3627	0	0
TransStop_A	373604906	1879	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604906	3627	0	0
T1	548817	6	0	0
T4	25811	0	0	0
T11	0	50	0	0
T18	1943	0	0	0
T19	7174	0	0	0
T20	6898	4	0	0
T21	1698	0	0	0
T24	0	1	0	0
T26	5362	4	0	0
T27	21464	7	0	0
T28	7351	1	0	0
T29	8020	0	0	0
T90	0	1	0	0
T132	0	6	0	0
T133	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604906	1879	0	0
T1	548817	3	0	0
T4	25811	0	0	0
T11	0	23	0	0
T18	1943	0	0	0
T19	7174	0	0	0
T20	6898	1	0	0
T21	1698	0	0	0
T24	0	1	0	0
T26	5362	2	0	0
T27	21464	3	0	0
T28	7351	1	0	0
T29	8020	0	0	0
T90	0	1	0	0
T132	0	4	0	0
T133	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	373604906	3530	0	0
TransStop_A	373604906	1871	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604906	3530	0	0
T1	548817	6	0	0
T4	25811	0	0	0
T11	0	51	0	0
T18	1943	0	0	0
T19	7174	0	0	0
T20	6898	6	0	0
T21	1698	0	0	0
T24	0	1	0	0
T26	5362	2	0	0
T27	21464	5	0	0
T28	7351	1	0	0
T29	8020	0	0	0
T90	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604906	1871	0	0
T1	548817	3	0	0
T4	25811	0	0	0
T11	0	29	0	0
T18	1943	0	0	0
T19	7174	0	0	0
T20	6898	2	0	0
T21	1698	0	0	0
T22	2430	0	0	0
T24	0	1	0	0
T27	21464	3	0	0
T28	7351	1	0	0
T29	8020	0	0	0
T90	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	373604906	3589	0	0
TransStop_A	373604906	1871	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604906	3589	0	0
T1	548817	6	0	0
T4	25811	0	0	0
T11	0	44	0	0
T18	1943	0	0	0
T19	7174	0	0	0
T20	6898	8	0	0
T21	1698	0	0	0
T24	0	1	0	0
T26	5362	4	0	0
T27	21464	8	0	0
T28	7351	1	0	0
T29	8020	0	0	0
T90	0	1	0	0
T132	0	6	0	0
T133	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604906	1871	0	0
T1	548817	3	0	0
T4	25811	0	0	0
T11	0	21	0	0
T18	1943	0	0	0
T19	7174	0	0	0
T20	6898	3	0	0
T21	1698	0	0	0
T24	0	1	0	0
T26	5362	1	0	0
T27	21464	4	0	0
T28	7351	1	0	0
T29	8020	0	0	0
T90	0	1	0	0
T132	0	5	0	0
T133	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	373604906	3584	0	0
TransStop_A	373604906	1921	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604906	3584	0	0
T1	548817	6	0	0
T4	25811	0	0	0
T11	0	63	0	0
T18	1943	0	0	0
T19	7174	0	0	0
T20	6898	7	0	0
T21	1698	0	0	0
T24	0	1	0	0
T26	5362	4	0	0
T27	21464	8	0	0
T28	7351	1	0	0
T29	8020	0	0	0
T90	0	1	0	0
T132	0	6	0	0
T133	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604906	1921	0	0
T1	548817	3	0	0
T4	25811	0	0	0
T11	0	32	0	0
T18	1943	0	0	0
T19	7174	0	0	0
T20	6898	3	0	0
T21	1698	0	0	0
T24	0	1	0	0
T26	5362	1	0	0
T27	21464	5	0	0
T28	7351	1	0	0
T29	8020	0	0	0
T90	0	1	0	0
T132	0	4	0	0
T133	0	1	0	0