Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	145069974	15468141	0	56

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145069974	15468141	0	56
T1	136034	16208	0	0
T2	112719	24518	0	1
T3	0	32127	0	1
T11	0	146168	0	0
T12	0	13348	0	1
T13	0	229771	0	0
T14	0	24649	0	0
T15	0	24136	0	1
T16	0	20843	0	1
T17	0	80152	0	0
T18	1000	0	0	0
T19	1721	0	0	0
T20	1655	0	0	0
T21	1459	0	0	0
T22	2382	0	0	0
T23	1444	0	0	0
T24	1915	0	0	0
T25	177973	0	0	0
T30	0	0	0	1
T32	0	0	0	1
T38	0	0	0	1
T135	0	0	0	1
T136	0	0	0	1