Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	146011266	4755205	0	0
clk_enables_rd_A	146011266	38895	0	0
clk_hints_rd_A	146011266	33763	0	0
extclk_ctrl_rd_A	146011266	45975	0	0
extclk_ctrl_regwen_rd_A	146011266	33551	0	0
jitter_enable_rd_A	146011266	47591	0	0
jitter_regwen_rd_A	146011266	36453	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146011266	4755205	0	0
T11	146588	68886	0	0
T12	116565	0	0	0
T13	0	112997	0	0
T17	0	125560	0	0
T36	77780	0	0	0
T37	81291	0	0	0
T47	0	168192	0	0
T81	0	101291	0	0
T82	0	130959	0	0
T83	0	94799	0	0
T84	0	47100	0	0
T85	0	88620	0	0
T86	0	81374	0	0
T87	1488	0	0	0
T88	1168	0	0	0
T89	875	0	0	0
T90	2354	0	0	0
T91	1809	0	0	0
T92	2698	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146011266	38895	0	0
T1	136034	0	0	0
T4	5677	0	0	0
T18	1000	0	0	0
T19	1721	0	0	0
T20	1655	0	0	0
T21	1459	0	0	0
T22	2382	0	0	0
T23	1444	0	0	0
T28	1910	4	0	0
T29	2004	0	0	0
T83	0	3747	0	0
T85	0	1954	0	0
T90	0	2	0	0
T148	0	5	0	0
T149	0	8	0	0
T150	0	6	0	0
T151	0	1	0	0
T152	0	2392	0	0
T153	0	1944	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146011266	33763	0	0
T46	1186	0	0	0
T83	0	3265	0	0
T85	0	1515	0	0
T148	0	3	0	0
T151	0	3	0	0
T152	0	1985	0	0
T153	0	1676	0	0
T154	2355	6	0	0
T155	0	23	0	0
T156	0	7	0	0
T157	0	4	0	0
T158	1273	0	0	0
T159	2305	0	0	0
T160	1781	0	0	0
T161	2085	0	0	0
T162	1127	0	0	0
T163	1039	0	0	0
T164	2284	0	0	0
T165	1837	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146011266	45975	0	0
T1	136034	0	0	0
T4	5677	0	0	0
T18	1000	0	0	0
T19	1721	0	0	0
T20	1655	0	0	0
T21	1459	0	0	0
T22	2382	0	0	0
T23	1444	19	0	0
T24	1915	0	0	0
T29	2004	48	0	0
T40	0	13	0	0
T41	0	43	0	0
T87	0	35	0	0
T91	0	15	0	0
T92	0	61	0	0
T166	0	30	0	0
T167	0	41	0	0
T168	0	76	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146011266	33551	0	0
T47	466178	0	0	0
T81	202272	0	0	0
T83	0	3364	0	0
T85	0	1675	0	0
T112	37595	32	0	0
T113	14169	0	0	0
T114	0	37	0	0
T129	0	35	0	0
T152	0	2109	0	0
T153	0	1628	0	0
T169	0	35	0	0
T170	0	9	0	0
T171	0	18	0	0
T172	1960	0	0	0
T173	874	0	0	0
T174	1325	0	0	0
T175	1674	0	0	0
T176	1707	0	0	0
T177	1878	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146011266	47591	0	0
T1	136034	0	0	0
T4	5677	0	0	0
T18	1000	0	0	0
T19	1721	0	0	0
T20	1655	0	0	0
T21	1459	0	0	0
T22	2382	0	0	0
T23	1444	0	0	0
T28	1910	124	0	0
T29	2004	0	0	0
T83	0	4481	0	0
T85	0	1923	0	0
T90	0	101	0	0
T148	0	103	0	0
T149	0	84	0	0
T150	0	88	0	0
T151	0	117	0	0
T152	0	3537	0	0
T154	0	105	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146011266	36453	0	0
T83	319194	3781	0	0
T85	0	1923	0	0
T148	2383	0	0	0
T152	0	2158	0	0
T153	0	1811	0	0
T178	0	3602	0	0
T179	0	897	0	0
T180	0	1713	0	0
T181	0	1954	0	0
T182	0	4488	0	0
T183	0	4871	0	0
T184	1081	0	0	0
T185	2568	0	0	0
T186	1206	0	0	0
T187	1414	0	0	0
T188	909	0	0	0
T189	1409	0	0	0
T190	1498	0	0	0
T191	1334	0	0	0