Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc
| Total | Covered | Percent |
Conditions | 15 | 13 | 86.67 |
Logical | 15 | 13 | 86.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T4,T11,T13 |
1 | 0 | Covered | T4,T1,T2 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1460112660 |
1454742 |
0 |
0 |
T1 |
1360340 |
2856 |
0 |
0 |
T2 |
1127190 |
1622 |
0 |
0 |
T3 |
0 |
2241 |
0 |
0 |
T4 |
56770 |
385 |
0 |
0 |
T11 |
0 |
20809 |
0 |
0 |
T12 |
0 |
2092 |
0 |
0 |
T18 |
10000 |
0 |
0 |
0 |
T19 |
17210 |
0 |
0 |
0 |
T20 |
16550 |
0 |
0 |
0 |
T21 |
14590 |
0 |
0 |
0 |
T22 |
23820 |
0 |
0 |
0 |
T23 |
14440 |
0 |
0 |
0 |
T24 |
19150 |
0 |
0 |
0 |
T25 |
0 |
2415 |
0 |
0 |
T35 |
0 |
305 |
0 |
0 |
T36 |
0 |
1347 |
0 |
0 |
T37 |
0 |
1348 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
3378232 |
3372362 |
0 |
0 |
T4 |
147906 |
32770 |
0 |
0 |
T5 |
13508 |
12790 |
0 |
0 |
T6 |
30844 |
29678 |
0 |
0 |
T7 |
10060 |
9140 |
0 |
0 |
T18 |
12208 |
11902 |
0 |
0 |
T26 |
33680 |
32270 |
0 |
0 |
T27 |
135530 |
134400 |
0 |
0 |
T28 |
46314 |
45386 |
0 |
0 |
T29 |
52084 |
51228 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1460112660 |
257177 |
0 |
0 |
T1 |
1360340 |
840 |
0 |
0 |
T2 |
1127190 |
200 |
0 |
0 |
T3 |
0 |
420 |
0 |
0 |
T4 |
56770 |
112 |
0 |
0 |
T11 |
0 |
2425 |
0 |
0 |
T12 |
0 |
380 |
0 |
0 |
T18 |
10000 |
0 |
0 |
0 |
T19 |
17210 |
0 |
0 |
0 |
T20 |
16550 |
0 |
0 |
0 |
T21 |
14590 |
0 |
0 |
0 |
T22 |
23820 |
0 |
0 |
0 |
T23 |
14440 |
0 |
0 |
0 |
T24 |
19150 |
0 |
0 |
0 |
T25 |
0 |
300 |
0 |
0 |
T35 |
0 |
100 |
0 |
0 |
T36 |
0 |
260 |
0 |
0 |
T37 |
0 |
260 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1460112660 |
1432950140 |
0 |
0 |
T1 |
1360340 |
1357880 |
0 |
0 |
T4 |
56770 |
11440 |
0 |
0 |
T5 |
20670 |
19440 |
0 |
0 |
T6 |
9560 |
9170 |
0 |
0 |
T7 |
16520 |
15000 |
0 |
0 |
T18 |
10000 |
9730 |
0 |
0 |
T26 |
13390 |
12760 |
0 |
0 |
T27 |
25760 |
25520 |
0 |
0 |
T28 |
19100 |
18670 |
0 |
0 |
T29 |
20040 |
19660 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
89046 |
0 |
0 |
T1 |
136034 |
210 |
0 |
0 |
T2 |
112719 |
101 |
0 |
0 |
T3 |
0 |
153 |
0 |
0 |
T4 |
5677 |
19 |
0 |
0 |
T11 |
0 |
1238 |
0 |
0 |
T12 |
0 |
148 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
150 |
0 |
0 |
T35 |
0 |
27 |
0 |
0 |
T36 |
0 |
94 |
0 |
0 |
T37 |
0 |
97 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
352096896 |
347819663 |
0 |
0 |
T1 |
503808 |
502808 |
0 |
0 |
T4 |
24778 |
4977 |
0 |
0 |
T5 |
2024 |
1903 |
0 |
0 |
T6 |
4594 |
4405 |
0 |
0 |
T7 |
1569 |
1421 |
0 |
0 |
T18 |
1871 |
1819 |
0 |
0 |
T26 |
5147 |
4902 |
0 |
0 |
T27 |
20605 |
20415 |
0 |
0 |
T28 |
7056 |
6894 |
0 |
0 |
T29 |
7699 |
7551 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
22918 |
0 |
0 |
T1 |
136034 |
84 |
0 |
0 |
T2 |
112719 |
20 |
0 |
0 |
T3 |
0 |
42 |
0 |
0 |
T4 |
5677 |
8 |
0 |
0 |
T11 |
0 |
238 |
0 |
0 |
T12 |
0 |
38 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T36 |
0 |
26 |
0 |
0 |
T37 |
0 |
26 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
143295014 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
129554 |
0 |
0 |
T1 |
136034 |
294 |
0 |
0 |
T2 |
112719 |
164 |
0 |
0 |
T3 |
0 |
226 |
0 |
0 |
T4 |
5677 |
27 |
0 |
0 |
T11 |
0 |
2009 |
0 |
0 |
T12 |
0 |
206 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
239 |
0 |
0 |
T35 |
0 |
30 |
0 |
0 |
T36 |
0 |
136 |
0 |
0 |
T37 |
0 |
135 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175205933 |
174137530 |
0 |
0 |
T1 |
252544 |
252281 |
0 |
0 |
T4 |
7317 |
2490 |
0 |
0 |
T5 |
1073 |
1038 |
0 |
0 |
T6 |
2498 |
2429 |
0 |
0 |
T7 |
766 |
711 |
0 |
0 |
T18 |
923 |
909 |
0 |
0 |
T26 |
2506 |
2451 |
0 |
0 |
T27 |
10263 |
10208 |
0 |
0 |
T28 |
3482 |
3447 |
0 |
0 |
T29 |
4317 |
4282 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
22918 |
0 |
0 |
T1 |
136034 |
84 |
0 |
0 |
T2 |
112719 |
20 |
0 |
0 |
T3 |
0 |
42 |
0 |
0 |
T4 |
5677 |
8 |
0 |
0 |
T11 |
0 |
238 |
0 |
0 |
T12 |
0 |
38 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T36 |
0 |
26 |
0 |
0 |
T37 |
0 |
26 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
143295014 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
211567 |
0 |
0 |
T1 |
136034 |
420 |
0 |
0 |
T2 |
112719 |
288 |
0 |
0 |
T3 |
0 |
369 |
0 |
0 |
T4 |
5677 |
38 |
0 |
0 |
T11 |
0 |
3513 |
0 |
0 |
T12 |
0 |
336 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
433 |
0 |
0 |
T35 |
0 |
39 |
0 |
0 |
T36 |
0 |
219 |
0 |
0 |
T37 |
0 |
218 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
87602365 |
87068292 |
0 |
0 |
T1 |
126270 |
126139 |
0 |
0 |
T4 |
3658 |
1244 |
0 |
0 |
T5 |
535 |
518 |
0 |
0 |
T6 |
1248 |
1214 |
0 |
0 |
T7 |
383 |
355 |
0 |
0 |
T18 |
462 |
455 |
0 |
0 |
T26 |
1253 |
1225 |
0 |
0 |
T27 |
5131 |
5103 |
0 |
0 |
T28 |
1741 |
1724 |
0 |
0 |
T29 |
2157 |
2140 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
22918 |
0 |
0 |
T1 |
136034 |
84 |
0 |
0 |
T2 |
112719 |
20 |
0 |
0 |
T3 |
0 |
42 |
0 |
0 |
T4 |
5677 |
8 |
0 |
0 |
T11 |
0 |
238 |
0 |
0 |
T12 |
0 |
38 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T36 |
0 |
26 |
0 |
0 |
T37 |
0 |
26 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
143295014 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
88227 |
0 |
0 |
T1 |
136034 |
210 |
0 |
0 |
T2 |
112719 |
97 |
0 |
0 |
T3 |
0 |
150 |
0 |
0 |
T4 |
5677 |
19 |
0 |
0 |
T11 |
0 |
1449 |
0 |
0 |
T12 |
0 |
143 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
149 |
0 |
0 |
T35 |
0 |
27 |
0 |
0 |
T36 |
0 |
93 |
0 |
0 |
T37 |
0 |
93 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376057082 |
371533629 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
22918 |
0 |
0 |
T1 |
136034 |
84 |
0 |
0 |
T2 |
112719 |
20 |
0 |
0 |
T3 |
0 |
42 |
0 |
0 |
T4 |
5677 |
8 |
0 |
0 |
T11 |
0 |
238 |
0 |
0 |
T12 |
0 |
38 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T36 |
0 |
26 |
0 |
0 |
T37 |
0 |
26 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
143295014 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
127607 |
0 |
0 |
T1 |
136034 |
294 |
0 |
0 |
T2 |
112719 |
158 |
0 |
0 |
T3 |
0 |
223 |
0 |
0 |
T4 |
5677 |
18 |
0 |
0 |
T11 |
0 |
2003 |
0 |
0 |
T12 |
0 |
210 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
235 |
0 |
0 |
T35 |
0 |
30 |
0 |
0 |
T36 |
0 |
134 |
0 |
0 |
T37 |
0 |
136 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
180480274 |
178311641 |
0 |
0 |
T1 |
257677 |
257178 |
0 |
0 |
T4 |
12389 |
2489 |
0 |
0 |
T5 |
1012 |
952 |
0 |
0 |
T6 |
2297 |
2203 |
0 |
0 |
T7 |
770 |
696 |
0 |
0 |
T18 |
905 |
879 |
0 |
0 |
T26 |
2573 |
2451 |
0 |
0 |
T27 |
10303 |
10208 |
0 |
0 |
T28 |
3528 |
3447 |
0 |
0 |
T29 |
3849 |
3775 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
22481 |
0 |
0 |
T1 |
136034 |
84 |
0 |
0 |
T2 |
112719 |
20 |
0 |
0 |
T3 |
0 |
42 |
0 |
0 |
T4 |
5677 |
4 |
0 |
0 |
T11 |
0 |
238 |
0 |
0 |
T12 |
0 |
38 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T36 |
0 |
26 |
0 |
0 |
T37 |
0 |
26 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
143295014 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T4,T11,T13 |
1 | 0 | Covered | T4,T1,T2 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
111279 |
0 |
0 |
T1 |
136034 |
210 |
0 |
0 |
T2 |
112719 |
105 |
0 |
0 |
T3 |
0 |
156 |
0 |
0 |
T4 |
5677 |
40 |
0 |
0 |
T11 |
0 |
1291 |
0 |
0 |
T12 |
0 |
143 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
152 |
0 |
0 |
T35 |
0 |
27 |
0 |
0 |
T36 |
0 |
94 |
0 |
0 |
T37 |
0 |
94 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
352096896 |
347819663 |
0 |
0 |
T1 |
503808 |
502808 |
0 |
0 |
T4 |
24778 |
4977 |
0 |
0 |
T5 |
2024 |
1903 |
0 |
0 |
T6 |
4594 |
4405 |
0 |
0 |
T7 |
1569 |
1421 |
0 |
0 |
T18 |
1871 |
1819 |
0 |
0 |
T26 |
5147 |
4902 |
0 |
0 |
T27 |
20605 |
20415 |
0 |
0 |
T28 |
7056 |
6894 |
0 |
0 |
T29 |
7699 |
7551 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
28687 |
0 |
0 |
T1 |
136034 |
84 |
0 |
0 |
T2 |
112719 |
20 |
0 |
0 |
T3 |
0 |
42 |
0 |
0 |
T4 |
5677 |
16 |
0 |
0 |
T11 |
0 |
247 |
0 |
0 |
T12 |
0 |
38 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T36 |
0 |
26 |
0 |
0 |
T37 |
0 |
26 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
143295014 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T4,T11,T13 |
1 | 0 | Covered | T4,T1,T2 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
162109 |
0 |
0 |
T1 |
136034 |
294 |
0 |
0 |
T2 |
112719 |
165 |
0 |
0 |
T3 |
0 |
223 |
0 |
0 |
T4 |
5677 |
55 |
0 |
0 |
T11 |
0 |
2066 |
0 |
0 |
T12 |
0 |
210 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
237 |
0 |
0 |
T35 |
0 |
28 |
0 |
0 |
T36 |
0 |
137 |
0 |
0 |
T37 |
0 |
134 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175205933 |
174137530 |
0 |
0 |
T1 |
252544 |
252281 |
0 |
0 |
T4 |
7317 |
2490 |
0 |
0 |
T5 |
1073 |
1038 |
0 |
0 |
T6 |
2498 |
2429 |
0 |
0 |
T7 |
766 |
711 |
0 |
0 |
T18 |
923 |
909 |
0 |
0 |
T26 |
2506 |
2451 |
0 |
0 |
T27 |
10263 |
10208 |
0 |
0 |
T28 |
3482 |
3447 |
0 |
0 |
T29 |
4317 |
4282 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
28677 |
0 |
0 |
T1 |
136034 |
84 |
0 |
0 |
T2 |
112719 |
20 |
0 |
0 |
T3 |
0 |
42 |
0 |
0 |
T4 |
5677 |
16 |
0 |
0 |
T11 |
0 |
247 |
0 |
0 |
T12 |
0 |
38 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T36 |
0 |
26 |
0 |
0 |
T37 |
0 |
26 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
143295014 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T4,T11,T13 |
1 | 0 | Covered | T4,T1,T2 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
264353 |
0 |
0 |
T1 |
136034 |
420 |
0 |
0 |
T2 |
112719 |
282 |
0 |
0 |
T3 |
0 |
365 |
0 |
0 |
T4 |
5677 |
75 |
0 |
0 |
T11 |
0 |
3662 |
0 |
0 |
T12 |
0 |
342 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
428 |
0 |
0 |
T35 |
0 |
41 |
0 |
0 |
T36 |
0 |
214 |
0 |
0 |
T37 |
0 |
213 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
87602365 |
87068292 |
0 |
0 |
T1 |
126270 |
126139 |
0 |
0 |
T4 |
3658 |
1244 |
0 |
0 |
T5 |
535 |
518 |
0 |
0 |
T6 |
1248 |
1214 |
0 |
0 |
T7 |
383 |
355 |
0 |
0 |
T18 |
462 |
455 |
0 |
0 |
T26 |
1253 |
1225 |
0 |
0 |
T27 |
5131 |
5103 |
0 |
0 |
T28 |
1741 |
1724 |
0 |
0 |
T29 |
2157 |
2140 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
28624 |
0 |
0 |
T1 |
136034 |
84 |
0 |
0 |
T2 |
112719 |
20 |
0 |
0 |
T3 |
0 |
42 |
0 |
0 |
T4 |
5677 |
16 |
0 |
0 |
T11 |
0 |
247 |
0 |
0 |
T12 |
0 |
38 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T36 |
0 |
26 |
0 |
0 |
T37 |
0 |
26 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
143295014 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T4,T11,T13 |
1 | 0 | Covered | T4,T1,T2 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
109927 |
0 |
0 |
T1 |
136034 |
210 |
0 |
0 |
T2 |
112719 |
101 |
0 |
0 |
T3 |
0 |
152 |
0 |
0 |
T4 |
5677 |
40 |
0 |
0 |
T11 |
0 |
1505 |
0 |
0 |
T12 |
0 |
142 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
148 |
0 |
0 |
T35 |
0 |
27 |
0 |
0 |
T36 |
0 |
92 |
0 |
0 |
T37 |
0 |
93 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376057082 |
371533629 |
0 |
0 |
T1 |
548817 |
547775 |
0 |
0 |
T4 |
25811 |
5185 |
0 |
0 |
T5 |
2110 |
1984 |
0 |
0 |
T6 |
4785 |
4588 |
0 |
0 |
T7 |
1542 |
1387 |
0 |
0 |
T18 |
1943 |
1889 |
0 |
0 |
T26 |
5361 |
5106 |
0 |
0 |
T27 |
21463 |
21266 |
0 |
0 |
T28 |
7350 |
7181 |
0 |
0 |
T29 |
8020 |
7866 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
28646 |
0 |
0 |
T1 |
136034 |
84 |
0 |
0 |
T2 |
112719 |
20 |
0 |
0 |
T3 |
0 |
42 |
0 |
0 |
T4 |
5677 |
16 |
0 |
0 |
T11 |
0 |
247 |
0 |
0 |
T12 |
0 |
38 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T36 |
0 |
26 |
0 |
0 |
T37 |
0 |
26 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
143295014 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T4,T11,T13 |
1 | 0 | Covered | T4,T1,T2 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T4,T1,T2 |
0 |
0 |
1 |
Covered |
T4,T1,T2 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
161073 |
0 |
0 |
T1 |
136034 |
294 |
0 |
0 |
T2 |
112719 |
161 |
0 |
0 |
T3 |
0 |
224 |
0 |
0 |
T4 |
5677 |
54 |
0 |
0 |
T11 |
0 |
2073 |
0 |
0 |
T12 |
0 |
212 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
244 |
0 |
0 |
T35 |
0 |
29 |
0 |
0 |
T36 |
0 |
134 |
0 |
0 |
T37 |
0 |
135 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
180480274 |
178311641 |
0 |
0 |
T1 |
257677 |
257178 |
0 |
0 |
T4 |
12389 |
2489 |
0 |
0 |
T5 |
1012 |
952 |
0 |
0 |
T6 |
2297 |
2203 |
0 |
0 |
T7 |
770 |
696 |
0 |
0 |
T18 |
905 |
879 |
0 |
0 |
T26 |
2573 |
2451 |
0 |
0 |
T27 |
10303 |
10208 |
0 |
0 |
T28 |
3528 |
3447 |
0 |
0 |
T29 |
3849 |
3775 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
28390 |
0 |
0 |
T1 |
136034 |
84 |
0 |
0 |
T2 |
112719 |
20 |
0 |
0 |
T3 |
0 |
42 |
0 |
0 |
T4 |
5677 |
12 |
0 |
0 |
T11 |
0 |
247 |
0 |
0 |
T12 |
0 |
38 |
0 |
0 |
T18 |
1000 |
0 |
0 |
0 |
T19 |
1721 |
0 |
0 |
0 |
T20 |
1655 |
0 |
0 |
0 |
T21 |
1459 |
0 |
0 |
0 |
T22 |
2382 |
0 |
0 |
0 |
T23 |
1444 |
0 |
0 |
0 |
T24 |
1915 |
0 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T36 |
0 |
26 |
0 |
0 |
T37 |
0 |
26 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146011266 |
143295014 |
0 |
0 |
T1 |
136034 |
135788 |
0 |
0 |
T4 |
5677 |
1144 |
0 |
0 |
T5 |
2067 |
1944 |
0 |
0 |
T6 |
956 |
917 |
0 |
0 |
T7 |
1652 |
1500 |
0 |
0 |
T18 |
1000 |
973 |
0 |
0 |
T26 |
1339 |
1276 |
0 |
0 |
T27 |
2576 |
2552 |
0 |
0 |
T28 |
1910 |
1867 |
0 |
0 |
T29 |
2004 |
1966 |
0 |
0 |