Module Definition
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Module : tlul_err
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_reg_if.u_err 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_reg_if.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.48 100.00 97.92 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_err
Line No.TotalCoveredPercent
TOTAL2626100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5311100.00
ALWAYS561717100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
42 1 1
53 1 1
56 1 1
57 1 1
58 1 1
60 1 1
61 1 1
63 1 1
64 1 1
65 1 1
69 1 1
71 1 1
73 1 1
77 1 1
78 1 1
79 1 1
89 1 1
90 1 1
91 1 1
95 1 1


Cond Coverage for Module : tlul_err
TotalCoveredPercent
Conditions3535100.00
Logical3535100.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T26

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T26

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T26

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT5,T6,T26
001CoveredT11,T13,T17
010CoveredT11,T13,T17
100CoveredT18,T20,T21

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01CoveredT11,T13,T17
10CoveredT18,T20,T21
11CoveredT5,T6,T26

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000CoveredT11,T13,T17
001CoveredT5,T6,T26
010CoveredT5,T6,T26
100CoveredT5,T6,T26

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T26

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T26

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T26

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT5,T6,T26
1CoveredT5,T26,T27

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT5,T6,T26
1CoveredT5,T26,T27

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT11,T13,T17
101CoveredT11,T13,T17
110CoveredT11,T13,T17
111CoveredT5,T6,T26

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT18,T20,T21
001CoveredT5,T6,T26
010CoveredT5,T26,T27
100CoveredT5,T26,T27

Branch Coverage for Module : tlul_err
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 8 8 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if (tl_i.a_valid) -2-: 61 case (tl_i.a_size) -3-: 71 (tl_i.a_address[1]) ? -4-: 73 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T5,T6,T26
1 'h1 1 - Covered T5,T26,T27
1 'h1 0 - Covered T5,T6,T26
1 'h1 - 1 Covered T5,T26,T27
1 'h1 - 0 Covered T5,T6,T26
1 'h00000002 - - Covered T5,T6,T26
1 default - - Covered T11,T13,T17
0 - - - Covered T5,T6,T26


Assert Coverage for Module : tlul_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 1008 1008 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1008 1008 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T18 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%