Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T1
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	46840	0	0
CgEnOn_A	2147483647	37708	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46840	0	0
T1	5568363	73	0	0
T4	246077	15	0	0
T5	4644	3	0	0
T6	10637	3	0	0
T7	16224	37	0	0
T11	0	10	0	0
T18	19999	21	0	0
T19	59335	0	0	0
T20	56183	4	0	0
T24	0	1	0	0
T26	55057	7	0	0
T27	221341	10	0	0
T28	75668	7	0	0
T29	84629	3	0	0
T33	0	13	0	0
T34	0	2	0	0
T192	0	30	0	0
T193	0	15	0	0
T194	0	15	0	0
T195	0	5	0	0
T196	0	5	0	0
T197	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37708	0	0
T1	5568363	61	0	0
T4	246077	0	0	0
T7	16224	38	0	0
T11	0	259	0	0
T18	19999	22	0	0
T19	75311	0	0	0
T20	71023	10	0	0
T24	0	5	0	0
T26	55057	6	0	0
T27	221341	12	0	0
T28	75668	5	0	0
T29	84629	0	0	0
T33	0	25	0	0
T34	0	6	0	0
T37	0	32	0	0
T89	0	4	0	0
T133	0	3	0	0
T192	0	37	0	0
T193	0	17	0	0
T194	0	18	0	0
T195	0	6	0	0
T196	0	5	0	0
T197	0	7	0	0
T198	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	174074563	152	0	0
CgEnOn_A	174074563	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174074563	152	0	0
T1	252544	0	0	0
T4	7317	0	0	0
T7	766	4	0	0
T11	0	2	0	0
T18	923	2	0	0
T19	3765	0	0	0
T20	3271	0	0	0
T26	2506	0	0	0
T27	10263	0	0	0
T28	3482	0	0	0
T29	4317	0	0	0
T33	0	2	0	0
T192	0	6	0	0
T193	0	3	0	0
T194	0	3	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174074563	152	0	0
T1	252544	0	0	0
T4	7317	0	0	0
T7	766	4	0	0
T11	0	2	0	0
T18	923	2	0	0
T19	3765	0	0	0
T20	3271	0	0	0
T26	2506	0	0	0
T27	10263	0	0	0
T28	3482	0	0	0
T29	4317	0	0	0
T33	0	2	0	0
T192	0	6	0	0
T193	0	3	0	0
T194	0	3	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	87036675	152	0	0
CgEnOn_A	87036675	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87036675	152	0	0
T1	126270	0	0	0
T4	3658	0	0	0
T7	383	4	0	0
T11	0	2	0	0
T18	462	2	0	0
T19	1882	0	0	0
T20	1636	0	0	0
T26	1253	0	0	0
T27	5131	0	0	0
T28	1741	0	0	0
T29	2157	0	0	0
T33	0	2	0	0
T192	0	6	0	0
T193	0	3	0	0
T194	0	3	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87036675	152	0	0
T1	126270	0	0	0
T4	3658	0	0	0
T7	383	4	0	0
T11	0	2	0	0
T18	462	2	0	0
T19	1882	0	0	0
T20	1636	0	0	0
T26	1253	0	0	0
T27	5131	0	0	0
T28	1741	0	0	0
T29	2157	0	0	0
T33	0	2	0	0
T192	0	6	0	0
T193	0	3	0	0
T194	0	3	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	349742487	152	0	0
CgEnOn_A	349742487	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349742487	152	0	0
T1	503808	0	0	0
T4	24778	0	0	0
T7	1569	4	0	0
T11	0	2	0	0
T18	1871	2	0	0
T19	6886	0	0	0
T20	6622	0	0	0
T26	5147	0	0	0
T27	20605	0	0	0
T28	7056	0	0	0
T29	7699	0	0	0
T33	0	2	0	0
T192	0	6	0	0
T193	0	3	0	0
T194	0	3	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349742487	142	0	0
T1	503808	0	0	0
T4	24778	0	0	0
T7	1569	4	0	0
T11	0	1	0	0
T18	1871	2	0	0
T19	6886	0	0	0
T20	6622	0	0	0
T26	5147	0	0	0
T27	20605	0	0	0
T28	7056	0	0	0
T29	7699	0	0	0
T33	0	2	0	0
T192	0	6	0	0
T193	0	3	0	0
T194	0	3	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	373604474	155	0	0
CgEnOn_A	373604474	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604474	155	0	0
T1	548817	0	0	0
T4	25811	0	0	0
T7	1542	2	0	0
T18	1943	2	0	0
T19	7173	0	0	0
T20	6897	0	0	0
T26	5361	0	0	0
T27	21463	0	0	0
T28	7350	0	0	0
T29	8020	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T192	0	7	0	0
T193	0	2	0	0
T194	0	3	0	0
T195	0	1	0	0
T197	0	2	0	0
T198	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604474	152	0	0
T1	548817	0	0	0
T4	25811	0	0	0
T7	1542	2	0	0
T18	1943	2	0	0
T19	7173	0	0	0
T20	6897	0	0	0
T26	5361	0	0	0
T27	21463	0	0	0
T28	7350	0	0	0
T29	8020	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T192	0	7	0	0
T193	0	2	0	0
T194	0	3	0	0
T195	0	1	0	0
T197	0	2	0	0
T198	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	87036675	152	0	0
CgEnOn_A	87036675	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87036675	152	0	0
T1	126270	0	0	0
T4	3658	0	0	0
T7	383	4	0	0
T11	0	2	0	0
T18	462	2	0	0
T19	1882	0	0	0
T20	1636	0	0	0
T26	1253	0	0	0
T27	5131	0	0	0
T28	1741	0	0	0
T29	2157	0	0	0
T33	0	2	0	0
T192	0	6	0	0
T193	0	3	0	0
T194	0	3	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87036675	152	0	0
T1	126270	0	0	0
T4	3658	0	0	0
T7	383	4	0	0
T11	0	2	0	0
T18	462	2	0	0
T19	1882	0	0	0
T20	1636	0	0	0
T26	1253	0	0	0
T27	5131	0	0	0
T28	1741	0	0	0
T29	2157	0	0	0
T33	0	2	0	0
T192	0	6	0	0
T193	0	3	0	0
T194	0	3	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	373604474	155	0	0
CgEnOn_A	373604474	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604474	155	0	0
T1	548817	0	0	0
T4	25811	0	0	0
T7	1542	2	0	0
T18	1943	2	0	0
T19	7173	0	0	0
T20	6897	0	0	0
T26	5361	0	0	0
T27	21463	0	0	0
T28	7350	0	0	0
T29	8020	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T192	0	7	0	0
T193	0	2	0	0
T194	0	3	0	0
T195	0	1	0	0
T197	0	2	0	0
T198	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604474	152	0	0
T1	548817	0	0	0
T4	25811	0	0	0
T7	1542	2	0	0
T18	1943	2	0	0
T19	7173	0	0	0
T20	6897	0	0	0
T26	5361	0	0	0
T27	21463	0	0	0
T28	7350	0	0	0
T29	8020	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T192	0	7	0	0
T193	0	2	0	0
T194	0	3	0	0
T195	0	1	0	0
T197	0	2	0	0
T198	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	87036675	152	0	0
CgEnOn_A	87036675	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87036675	152	0	0
T1	126270	0	0	0
T4	3658	0	0	0
T7	383	4	0	0
T11	0	2	0	0
T18	462	2	0	0
T19	1882	0	0	0
T20	1636	0	0	0
T26	1253	0	0	0
T27	5131	0	0	0
T28	1741	0	0	0
T29	2157	0	0	0
T33	0	2	0	0
T192	0	6	0	0
T193	0	3	0	0
T194	0	3	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87036675	152	0	0
T1	126270	0	0	0
T4	3658	0	0	0
T7	383	4	0	0
T11	0	2	0	0
T18	462	2	0	0
T19	1882	0	0	0
T20	1636	0	0	0
T26	1253	0	0	0
T27	5131	0	0	0
T28	1741	0	0	0
T29	2157	0	0	0
T33	0	2	0	0
T192	0	6	0	0
T193	0	3	0	0
T194	0	3	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T18,T33
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	174074563	7706	0	0
CgEnOn_A	174074563	5436	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174074563	7706	0	0
T1	252544	24	0	0
T4	7317	5	0	0
T5	1073	1	0	0
T6	2498	1	0	0
T7	766	5	0	0
T18	923	3	0	0
T26	2506	1	0	0
T27	10263	1	0	0
T28	3482	2	0	0
T29	4317	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174074563	5436	0	0
T1	252544	18	0	0
T4	7317	0	0	0
T7	766	4	0	0
T11	0	84	0	0
T18	923	2	0	0
T19	3765	0	0	0
T20	3271	0	0	0
T24	0	1	0	0
T26	2506	0	0	0
T27	10263	0	0	0
T28	3482	1	0	0
T29	4317	0	0	0
T33	0	2	0	0
T37	0	11	0	0
T89	0	1	0	0
T133	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T18,T33
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	87036675	7658	0	0
CgEnOn_A	87036675	5388	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87036675	7658	0	0
T1	126270	21	0	0
T4	3658	5	0	0
T5	535	1	0	0
T6	1248	1	0	0
T7	383	5	0	0
T18	462	3	0	0
T26	1253	1	0	0
T27	5131	1	0	0
T28	1741	2	0	0
T29	2157	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87036675	5388	0	0
T1	126270	15	0	0
T4	3658	0	0	0
T7	383	4	0	0
T11	0	85	0	0
T18	462	2	0	0
T19	1882	0	0	0
T20	1636	0	0	0
T24	0	1	0	0
T26	1253	0	0	0
T27	5131	0	0	0
T28	1741	1	0	0
T29	2157	0	0	0
T33	0	2	0	0
T37	0	10	0	0
T89	0	2	0	0
T133	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T18,T33
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	349742487	7739	0	0
CgEnOn_A	349742487	5459	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349742487	7739	0	0
T1	503808	22	0	0
T4	24778	5	0	0
T5	2024	1	0	0
T6	4594	1	0	0
T7	1569	5	0	0
T18	1871	3	0	0
T26	5147	1	0	0
T27	20605	1	0	0
T28	7056	2	0	0
T29	7699	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349742487	5459	0	0
T1	503808	16	0	0
T4	24778	0	0	0
T7	1569	4	0	0
T11	0	81	0	0
T18	1871	2	0	0
T19	6886	0	0	0
T20	6622	0	0	0
T24	0	1	0	0
T26	5147	0	0	0
T27	20605	0	0	0
T28	7056	1	0	0
T29	7699	0	0	0
T33	0	2	0	0
T37	0	11	0	0
T89	0	1	0	0
T133	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T18,T33
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	179303053	7717	0	0
CgEnOn_A	179303053	5433	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179303053	7717	0	0
T1	257677	23	0	0
T4	12389	5	0	0
T5	1012	1	0	0
T6	2297	1	0	0
T7	770	4	0	0
T18	905	2	0	0
T26	2573	1	0	0
T27	10303	1	0	0
T28	3528	2	0	0
T29	3849	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179303053	5433	0	0
T1	257677	17	0	0
T4	12389	0	0	0
T7	770	3	0	0
T11	0	78	0	0
T18	905	1	0	0
T19	3443	0	0	0
T20	3311	0	0	0
T24	0	1	0	0
T26	2573	0	0	0
T27	10303	0	0	0
T28	3528	1	0	0
T29	3849	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T89	0	2	0	0
T133	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T1
1	0	Covered	T26,T27,T28
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	373604474	3782	0	0
CgEnOn_A	373604474	3779	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604474	3782	0	0
T1	548817	6	0	0
T4	25811	0	0	0
T7	1542	2	0	0
T18	1943	2	0	0
T19	7173	0	0	0
T20	6897	4	0	0
T24	0	1	0	0
T26	5361	4	0	0
T27	21463	7	0	0
T28	7350	1	0	0
T29	8020	0	0	0
T33	0	3	0	0
T34	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604474	3779	0	0
T1	548817	6	0	0
T4	25811	0	0	0
T7	1542	2	0	0
T18	1943	2	0	0
T19	7173	0	0	0
T20	6897	4	0	0
T24	0	1	0	0
T26	5361	4	0	0
T27	21463	7	0	0
T28	7350	1	0	0
T29	8020	0	0	0
T33	0	3	0	0
T34	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T1
1	0	Covered	T26,T27,T28
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	373604474	3685	0	0
CgEnOn_A	373604474	3682	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604474	3685	0	0
T1	548817	6	0	0
T4	25811	0	0	0
T7	1542	2	0	0
T18	1943	2	0	0
T19	7173	0	0	0
T20	6897	6	0	0
T24	0	1	0	0
T26	5361	2	0	0
T27	21463	5	0	0
T28	7350	1	0	0
T29	8020	0	0	0
T33	0	3	0	0
T34	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604474	3682	0	0
T1	548817	6	0	0
T4	25811	0	0	0
T7	1542	2	0	0
T18	1943	2	0	0
T19	7173	0	0	0
T20	6897	6	0	0
T24	0	1	0	0
T26	5361	2	0	0
T27	21463	5	0	0
T28	7350	1	0	0
T29	8020	0	0	0
T33	0	3	0	0
T34	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T1
1	0	Covered	T26,T27,T28
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	373604474	3744	0	0
CgEnOn_A	373604474	3741	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604474	3744	0	0
T1	548817	6	0	0
T4	25811	0	0	0
T7	1542	2	0	0
T18	1943	2	0	0
T19	7173	0	0	0
T20	6897	8	0	0
T24	0	1	0	0
T26	5361	4	0	0
T27	21463	8	0	0
T28	7350	1	0	0
T29	8020	0	0	0
T33	0	3	0	0
T34	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604474	3741	0	0
T1	548817	6	0	0
T4	25811	0	0	0
T7	1542	2	0	0
T18	1943	2	0	0
T19	7173	0	0	0
T20	6897	8	0	0
T24	0	1	0	0
T26	5361	4	0	0
T27	21463	8	0	0
T28	7350	1	0	0
T29	8020	0	0	0
T33	0	3	0	0
T34	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T1
1	0	Covered	T26,T27,T28
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	373604474	3739	0	0
CgEnOn_A	373604474	3736	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604474	3739	0	0
T1	548817	6	0	0
T4	25811	0	0	0
T7	1542	2	0	0
T18	1943	2	0	0
T19	7173	0	0	0
T20	6897	7	0	0
T24	0	1	0	0
T26	5361	4	0	0
T27	21463	8	0	0
T28	7350	1	0	0
T29	8020	0	0	0
T33	0	3	0	0
T34	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373604474	3736	0	0
T1	548817	6	0	0
T4	25811	0	0	0
T7	1542	2	0	0
T18	1943	2	0	0
T19	7173	0	0	0
T20	6897	7	0	0
T24	0	1	0	0
T26	5361	4	0	0
T27	21463	8	0	0
T28	7350	1	0	0
T29	8020	0	0	0
T33	0	3	0	0
T34	0	2	0	0