Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T28,T1
0	1	Covered	T1,T11,T37
1	0	Covered	T5,T7,T26

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T24
1	0	Covered	T7,T18,T33
1	1	Covered	T5,T7,T26

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	790158413	14218	0	0
GateOpen_A	790158413	14218	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790158413	14218	0	0
T1	1140300	30	0	0
T4	48144	0	0	0
T7	3488	15	0	0
T11	0	194	0	0
T18	4164	7	0	0
T19	15978	0	0	0
T20	14842	0	0	0
T24	0	4	0	0
T26	11481	0	0	0
T27	46305	0	0	0
T28	15808	4	0	0
T29	18025	0	0	0
T33	0	8	0	0
T34	0	2	0	0
T37	0	20	0	0
T89	0	6	0	0
T133	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790158413	14218	0	0
T1	1140300	30	0	0
T4	48144	0	0	0
T7	3488	15	0	0
T11	0	194	0	0
T18	4164	7	0	0
T19	15978	0	0	0
T20	14842	0	0	0
T24	0	4	0	0
T26	11481	0	0	0
T27	46305	0	0	0
T28	15808	4	0	0
T29	18025	0	0	0
T33	0	8	0	0
T34	0	2	0	0
T37	0	20	0	0
T89	0	6	0	0
T133	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T28,T1
0	1	Covered	T1,T11,T37
1	0	Covered	T5,T7,T26

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T24
1	0	Covered	T7,T18,T33
1	1	Covered	T5,T7,T26

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	87037074	3507	0	0
GateOpen_A	87037074	3507	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87037074	3507	0	0
T1	126271	7	0	0
T4	3659	0	0	0
T7	383	4	0	0
T11	0	48	0	0
T18	462	2	0	0
T19	1883	0	0	0
T20	1636	0	0	0
T24	0	1	0	0
T26	1254	0	0	0
T27	5132	0	0	0
T28	1741	1	0	0
T29	2158	0	0	0
T33	0	2	0	0
T37	0	6	0	0
T89	0	2	0	0
T133	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87037074	3507	0	0
T1	126271	7	0	0
T4	3659	0	0	0
T7	383	4	0	0
T11	0	48	0	0
T18	462	2	0	0
T19	1883	0	0	0
T20	1636	0	0	0
T24	0	1	0	0
T26	1254	0	0	0
T27	5132	0	0	0
T28	1741	1	0	0
T29	2158	0	0	0
T33	0	2	0	0
T37	0	6	0	0
T89	0	2	0	0
T133	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T28,T1
0	1	Covered	T1,T11,T37
1	0	Covered	T5,T7,T26

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T24
1	0	Covered	T7,T18,T33
1	1	Covered	T5,T7,T26

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	174074972	3576	0	0
GateOpen_A	174074972	3576	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174074972	3576	0	0
T1	252544	7	0	0
T4	7318	0	0	0
T7	766	4	0	0
T11	0	47	0	0
T18	924	2	0	0
T19	3765	0	0	0
T20	3272	0	0	0
T24	0	1	0	0
T26	2507	0	0	0
T27	10263	0	0	0
T28	3482	1	0	0
T29	4318	0	0	0
T33	0	2	0	0
T37	0	8	0	0
T89	0	1	0	0
T133	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174074972	3576	0	0
T1	252544	7	0	0
T4	7318	0	0	0
T7	766	4	0	0
T11	0	47	0	0
T18	924	2	0	0
T19	3765	0	0	0
T20	3272	0	0	0
T24	0	1	0	0
T26	2507	0	0	0
T27	10263	0	0	0
T28	3482	1	0	0
T29	4318	0	0	0
T33	0	2	0	0
T37	0	8	0	0
T89	0	1	0	0
T133	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T28,T1
0	1	Covered	T1,T11,T37
1	0	Covered	T5,T7,T26

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T24
1	0	Covered	T7,T18,T33
1	1	Covered	T5,T7,T26

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	349742922	3576	0	0
GateOpen_A	349742922	3576	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349742922	3576	0	0
T1	503808	8	0	0
T4	24778	0	0	0
T7	1569	4	0	0
T11	0	51	0	0
T18	1872	2	0	0
T19	6886	0	0	0
T20	6622	0	0	0
T24	0	1	0	0
T26	5147	0	0	0
T27	20606	0	0	0
T28	7056	1	0	0
T29	7699	0	0	0
T33	0	2	0	0
T37	0	6	0	0
T89	0	1	0	0
T133	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349742922	3576	0	0
T1	503808	8	0	0
T4	24778	0	0	0
T7	1569	4	0	0
T11	0	51	0	0
T18	1872	2	0	0
T19	6886	0	0	0
T20	6622	0	0	0
T24	0	1	0	0
T26	5147	0	0	0
T27	20606	0	0	0
T28	7056	1	0	0
T29	7699	0	0	0
T33	0	2	0	0
T37	0	6	0	0
T89	0	1	0	0
T133	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T28,T1
0	1	Covered	T1,T11,T37
1	0	Covered	T5,T7,T26

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T24
1	0	Covered	T7,T18,T33
1	1	Covered	T5,T7,T26

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	179303445	3559	0	0
GateOpen_A	179303445	3559	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179303445	3559	0	0
T1	257677	8	0	0
T4	12389	0	0	0
T7	770	3	0	0
T11	0	48	0	0
T18	906	1	0	0
T19	3444	0	0	0
T20	3312	0	0	0
T24	0	1	0	0
T26	2573	0	0	0
T27	10304	0	0	0
T28	3529	1	0	0
T29	3850	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T89	0	2	0	0
T133	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179303445	3559	0	0
T1	257677	8	0	0
T4	12389	0	0	0
T7	770	3	0	0
T11	0	48	0	0
T18	906	1	0	0
T19	3444	0	0	0
T20	3312	0	0	0
T24	0	1	0	0
T26	2573	0	0	0
T27	10304	0	0	0
T28	3529	1	0	0
T29	3850	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T89	0	2	0	0
T133	0	1	0	0