Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	623236	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3701846

1

T7

7

T8

14

T24

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1060412	1			T8	20		T24	28		T25	8
values[0x0]	1500798	1			T7	15		T8	12		T24	6
values[0x1]	1763872	1			T7	12		T8	13		T24	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	339901	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3985181

1

T7

9

T8

17

T24

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16431	1			T24	1		T18	3		T2	11
valid_sources[0x01]	15868	1			T2	18		T20	1		T4	10
valid_sources[0x02]	15648	1			T1	9		T2	4		T19	3
valid_sources[0x03]	17603	1			T2	11		T19	1		T4	7
valid_sources[0x04]	17276	1			T1	2		T2	22		T22	1
valid_sources[0x05]	16590	1			T2	8		T30	4		T64	1
valid_sources[0x06]	16319	1			T2	6		T20	2		T21	1
valid_sources[0x07]	17727	1			T2	12		T40	2		T30	2
valid_sources[0x08]	17573	1			T1	2		T2	13		T4	2
valid_sources[0x09]	16683	1			T2	7		T20	1		T4	2
valid_sources[0x0a]	16342	1			T25	1		T19	2		T21	1
valid_sources[0x0b]	17238	1			T1	6		T2	9		T4	1
valid_sources[0x0c]	15807	1			T2	5		T4	1		T40	2
valid_sources[0x0d]	16726	1			T2	6		T4	7		T30	5
valid_sources[0x0e]	16512	1			T24	1		T2	11		T21	1
valid_sources[0x0f]	15980	1			T2	7		T21	1		T30	3
valid_sources[0x10]	17911	1			T8	25		T24	1		T2	14
valid_sources[0x11]	17987	1			T2	13		T4	5		T30	4
valid_sources[0x12]	15868	1			T1	7		T2	25		T40	1
valid_sources[0x13]	17004	1			T2	8		T21	1		T4	4
valid_sources[0x14]	16609	1			T20	1		T21	1		T40	2
valid_sources[0x15]	17519	1			T7	1		T2	13		T30	6
valid_sources[0x16]	16425	1			T2	7		T21	2		T4	3
valid_sources[0x17]	16865	1			T2	5		T23	1		T4	3
valid_sources[0x18]	17156	1			T8	1		T2	9		T20	1
valid_sources[0x19]	18055	1			T2	5		T23	3		T4	4
valid_sources[0x1a]	16642	1			T7	3		T24	2		T2	20
valid_sources[0x1b]	17489	1			T2	22		T4	3		T30	3
valid_sources[0x1c]	17290	1			T2	9		T21	1		T4	4
valid_sources[0x1d]	16329	1			T24	1		T2	10		T20	1
valid_sources[0x1e]	17274	1			T2	6		T20	1		T22	1
valid_sources[0x1f]	16827	1			T2	5		T19	9		T4	3
valid_sources[0x20]	16486	1			T1	5		T2	24		T4	3
valid_sources[0x21]	17324	1			T1	3		T2	16		T20	1
valid_sources[0x22]	16684	1			T2	12		T20	1		T40	1
valid_sources[0x23]	17236	1			T25	1		T2	6		T20	3
valid_sources[0x24]	16251	1			T2	19		T4	3		T30	2
valid_sources[0x25]	16230	1			T2	7		T30	2		T11	13
valid_sources[0x26]	15884	1			T2	16		T4	5		T30	10
valid_sources[0x27]	17710	1			T25	5		T2	6		T20	3
valid_sources[0x28]	16671	1			T24	1		T1	16		T2	18
valid_sources[0x29]	16706	1			T24	1		T2	4		T4	6
valid_sources[0x2a]	16292	1			T24	1		T25	1		T4	5
valid_sources[0x2b]	17487	1			T2	5		T20	1		T30	6
valid_sources[0x2c]	15516	1			T2	4		T23	1		T4	5
valid_sources[0x2d]	16361	1			T1	11		T2	2		T4	14
valid_sources[0x2e]	17057	1			T25	2		T2	16		T19	4
valid_sources[0x2f]	16922	1			T18	4		T2	18		T21	1
valid_sources[0x30]	17574	1			T2	6		T4	1		T30	13
valid_sources[0x31]	16244	1			T2	11		T4	4		T30	1
valid_sources[0x32]	16717	1			T1	3		T2	13		T30	1
valid_sources[0x33]	17087	1			T1	7		T2	10		T19	7
valid_sources[0x34]	16761	1			T2	19		T20	1		T21	1
valid_sources[0x35]	16429	1			T1	14		T4	3		T30	5
valid_sources[0x36]	17068	1			T25	2		T2	13		T21	1
valid_sources[0x37]	17003	1			T24	1		T1	1		T2	4
valid_sources[0x38]	16216	1			T2	10		T20	1		T4	4
valid_sources[0x39]	17589	1			T2	3		T4	3		T30	8
valid_sources[0x3a]	15496	1			T2	7		T4	3		T30	3
valid_sources[0x3b]	16176	1			T2	15		T21	1		T11	4
valid_sources[0x3c]	16397	1			T7	2		T1	2		T2	5
valid_sources[0x3d]	16243	1			T2	4		T20	1		T23	1
valid_sources[0x3e]	17163	1			T1	9		T2	17		T19	25
valid_sources[0x3f]	16667	1			T2	3		T4	5		T30	1
valid_sources[0x40]	17706	1			T25	1		T2	8		T20	1
valid_sources[0x41]	17403	1			T2	19		T4	1		T30	1
valid_sources[0x42]	16297	1			T7	1		T1	4		T2	8
valid_sources[0x43]	15823	1			T2	7		T4	7		T40	1
valid_sources[0x44]	16859	1			T2	2		T21	2		T4	3
valid_sources[0x45]	17401	1			T2	7		T21	1		T4	2
valid_sources[0x46]	17213	1			T2	13		T19	3		T20	3
valid_sources[0x47]	16946	1			T24	1		T2	6		T20	2
valid_sources[0x48]	17239	1			T24	1		T1	2		T2	5
valid_sources[0x49]	16354	1			T1	19		T2	13		T4	1
valid_sources[0x4a]	17169	1			T8	13		T1	13		T2	15
valid_sources[0x4b]	17171	1			T2	2		T23	1		T30	3
valid_sources[0x4c]	16902	1			T1	1		T2	16		T20	1
valid_sources[0x4d]	17716	1			T2	10		T19	2		T22	1
valid_sources[0x4e]	15498	1			T2	2		T20	1		T30	1
valid_sources[0x4f]	16965	1			T2	6		T21	1		T4	2
valid_sources[0x50]	15331	1			T1	6		T2	31		T30	1
valid_sources[0x51]	17821	1			T1	5		T18	4		T2	10
valid_sources[0x52]	16656	1			T2	5		T19	1		T23	1
valid_sources[0x53]	17561	1			T1	6		T2	9		T30	6
valid_sources[0x54]	16067	1			T2	9		T23	1		T4	1
valid_sources[0x55]	16769	1			T2	13		T19	2		T22	1
valid_sources[0x56]	16904	1			T24	1		T2	36		T21	1
valid_sources[0x57]	17753	1			T25	1		T1	8		T2	12
valid_sources[0x58]	19425	1			T2	1		T4	9		T40	2
valid_sources[0x59]	17007	1			T24	2		T2	14		T21	1
valid_sources[0x5a]	16121	1			T7	2		T2	28		T19	9
valid_sources[0x5b]	16914	1			T24	1		T2	9		T21	1
valid_sources[0x5c]	16574	1			T2	10		T23	2		T4	7
valid_sources[0x5d]	16956	1			T2	7		T19	3		T21	1
valid_sources[0x5e]	17048	1			T2	8		T19	3		T23	1
valid_sources[0x5f]	15396	1			T2	9		T21	1		T23	1
valid_sources[0x60]	16845	1			T2	13		T4	1		T123	1
valid_sources[0x61]	15868	1			T7	2		T20	1		T23	1
valid_sources[0x62]	15836	1			T1	5		T2	7		T20	1
valid_sources[0x63]	16301	1			T1	8		T2	8		T19	8
valid_sources[0x64]	17306	1			T1	4		T2	3		T19	4
valid_sources[0x65]	16356	1			T24	2		T2	5		T4	6
valid_sources[0x66]	15997	1			T2	6		T20	1		T4	1
valid_sources[0x67]	17790	1			T24	1		T2	21		T4	2
valid_sources[0x68]	16453	1			T1	1		T2	2		T19	3
valid_sources[0x69]	18165	1			T24	1		T2	7		T20	1
valid_sources[0x6a]	16166	1			T2	10		T23	1		T30	3
valid_sources[0x6b]	15762	1			T1	7		T2	16		T20	1
valid_sources[0x6c]	16438	1			T2	6		T30	2		T128	7
valid_sources[0x6d]	16679	1			T1	3		T2	6		T4	3
valid_sources[0x6e]	17663	1			T24	1		T2	4		T3	17
valid_sources[0x6f]	16771	1			T2	6		T4	7		T30	9
valid_sources[0x70]	17485	1			T2	2		T4	1		T30	3
valid_sources[0x71]	17720	1			T24	2		T21	1		T4	1
valid_sources[0x72]	16321	1			T24	1		T2	7		T21	1
valid_sources[0x73]	16813	1			T2	14		T4	3		T30	1
valid_sources[0x74]	17955	1			T1	3		T2	5		T19	2
valid_sources[0x75]	17446	1			T2	14		T19	7		T21	1
valid_sources[0x76]	17453	1			T2	14		T21	1		T40	8
valid_sources[0x77]	17025	1			T24	1		T1	3		T2	16
valid_sources[0x78]	16174	1			T2	6		T21	1		T4	2
valid_sources[0x79]	16975	1			T2	1		T23	1		T4	1
valid_sources[0x7a]	15896	1			T2	8		T20	1		T4	8
valid_sources[0x7b]	15940	1			T7	1		T2	9		T30	2
valid_sources[0x7c]	16730	1			T18	1		T2	10		T21	1
valid_sources[0x7d]	16011	1			T2	3		T23	1		T4	1
valid_sources[0x7e]	16169	1			T24	1		T18	1		T2	11
valid_sources[0x7f]	16361	1			T18	1		T2	1		T40	1
valid_sources[0x80]	15853	1			T2	17		T40	1		T30	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

931955

1

T8

9

T24

9

T25

5

values[0x0]

all_enables

biggest_size

1408258

1

T7

6

T8

3

T24

4

values[0x1]

all_enables

biggest_size

1361633

1

T7

1

T8

2

T24

4