Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	797569525	77788	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797569525	77788	0	0
T1	1201715	498	0	0
T2	538930	280	0	0
T3	0	144	0	0
T4	549585	0	0	0
T5	23940	0	0	0
T11	0	308	0	0
T12	0	275	0	0
T13	0	690	0	0
T14	0	82	0	0
T15	0	419	0	0
T16	0	2651	0	0
T17	0	63	0	0
T18	8020	0	0	0
T19	119670	0	0	0
T20	8045	0	0	0
T21	10220	0	0	0
T22	7875	0	0	0
T23	10045	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159513905	11267	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159513905	11267	0	0
T1	240343	66	0	0
T2	107786	54	0	0
T3	0	23	0	0
T4	109917	0	0	0
T5	4788	0	0	0
T11	0	54	0	0
T12	0	44	0	0
T13	0	101	0	0
T14	0	14	0	0
T15	0	61	0	0
T16	0	343	0	0
T17	0	9	0	0
T18	1604	0	0	0
T19	23934	0	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159513905	15617	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159513905	15617	0	0
T1	240343	102	0	0
T2	107786	54	0	0
T3	0	30	0	0
T4	109917	0	0	0
T5	4788	0	0	0
T11	0	63	0	0
T12	0	56	0	0
T13	0	139	0	0
T14	0	18	0	0
T15	0	84	0	0
T16	0	526	0	0
T17	0	12	0	0
T18	1604	0	0	0
T19	23934	0	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159513905	24022	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159513905	24022	0	0
T1	240343	166	0	0
T2	107786	64	0	0
T3	0	39	0	0
T4	109917	0	0	0
T5	4788	0	0	0
T11	0	75	0	0
T12	0	75	0	0
T13	0	229	0	0
T14	0	20	0	0
T15	0	128	0	0
T16	0	875	0	0
T17	0	20	0	0
T18	1604	0	0	0
T19	23934	0	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159513905	11144	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159513905	11144	0	0
T1	240343	65	0	0
T2	107786	54	0	0
T3	0	23	0	0
T4	109917	0	0	0
T5	4788	0	0	0
T11	0	54	0	0
T12	0	44	0	0
T13	0	85	0	0
T14	0	13	0	0
T15	0	61	0	0
T16	0	384	0	0
T17	0	9	0	0
T18	1604	0	0	0
T19	23934	0	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159513905	15738	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159513905	15738	0	0
T1	240343	99	0	0
T2	107786	54	0	0
T3	0	29	0	0
T4	109917	0	0	0
T5	4788	0	0	0
T11	0	62	0	0
T12	0	56	0	0
T13	0	136	0	0
T14	0	17	0	0
T15	0	85	0	0
T16	0	523	0	0
T17	0	13	0	0
T18	1604	0	0	0
T19	23934	0	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0