Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T2,T4,T30

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	159513905	156556968	0	0
AllClkBypReqTrue_A	159513905	118796	0	0
IoClkBypReqFalse_A	159513905	156477059	0	2415
IoClkBypReqTrue_A	159513905	194185	0	0
LcClkBypAckFalse_A	159513905	156562774	0	0
LcClkBypAckTrue_A	159513905	112990	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159513905	156556968	0	0
T1	240343	240179	0	0
T2	107786	107622	0	0
T5	4788	4744	0	0
T6	1064	1037	0	0
T7	1439	1318	0	0
T8	1680	1552	0	0
T18	1604	1535	0	0
T19	23934	23910	0	0
T24	1896	1780	0	0
T25	1390	1346	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159513905	118796	0	0
T1	240343	0	0	0
T2	107786	0	0	0
T5	4788	0	0	0
T8	1680	89	0	0
T11	0	598	0	0
T12	0	2910	0	0
T18	1604	0	0	0
T19	23934	0	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T24	1896	0	0	0
T25	1390	0	0	0
T40	0	172	0	0
T123	0	64	0	0
T124	0	112	0	0
T125	0	253	0	0
T126	0	35	0	0
T127	0	41	0	0
T128	0	160	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159513905	156477059	0	2415
T1	240343	240177	0	3
T2	107786	107598	0	3
T5	4788	4742	0	3
T6	1064	1035	0	3
T7	1439	1316	0	3
T8	1680	1339	0	3
T18	1604	1533	0	3
T19	23934	23908	0	3
T24	1896	1778	0	3
T25	1390	1195	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159513905	194185	0	0
T1	240343	0	0	0
T2	107786	0	0	0
T5	4788	0	0	0
T8	1680	300	0	0
T11	0	844	0	0
T12	0	4041	0	0
T18	1604	0	0	0
T19	23934	0	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	0	45	0	0
T24	1896	0	0	0
T25	1390	149	0	0
T40	0	253	0	0
T124	0	186	0	0
T125	0	400	0	0
T127	0	122	0	0
T128	0	42	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159513905	156562774	0	0
T1	240343	240179	0	0
T2	107786	107622	0	0
T5	4788	4744	0	0
T6	1064	1037	0	0
T7	1439	1318	0	0
T8	1680	1572	0	0
T18	1604	1535	0	0
T19	23934	23910	0	0
T24	1896	1780	0	0
T25	1390	1320	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159513905	112990	0	0
T1	240343	0	0	0
T2	107786	0	0	0
T5	4788	0	0	0
T8	1680	69	0	0
T11	0	539	0	0
T12	0	2544	0	0
T18	1604	0	0	0
T19	23934	0	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	0	11	0	0
T24	1896	0	0	0
T25	1390	26	0	0
T40	0	136	0	0
T124	0	29	0	0
T125	0	257	0	0
T127	0	34	0	0
T128	0	38	0	0