Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1707530184	15010	0	0
TransStop_A	1707530184	7738	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1707530184	15010	0	0
T1	991080	0	0	0
T2	608720	29	0	0
T5	88688	0	0	0
T11	0	64	0	0
T12	0	109	0	0
T13	0	99	0	0
T18	13100	9	0	0
T19	374920	0	0	0
T20	32208	4	0	0
T21	8524	4	0	0
T22	6364	0	0	0
T23	0	13	0	0
T24	9248	15	0	0
T25	21400	0	0	0
T129	0	33	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1707530184	7738	0	0
T1	991080	0	0	0
T2	608720	15	0	0
T5	88688	0	0	0
T11	0	34	0	0
T12	0	65	0	0
T13	0	52	0	0
T18	13100	8	0	0
T19	374920	0	0	0
T20	32208	4	0	0
T21	8524	4	0	0
T22	6364	0	0	0
T23	0	7	0	0
T24	9248	11	0	0
T25	21400	0	0	0
T129	0	13	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	426882546	3761	0	0
TransStop_A	426882546	1932	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882546	3761	0	0
T1	247770	0	0	0
T2	152180	7	0	0
T5	22172	0	0	0
T11	0	17	0	0
T12	0	29	0	0
T13	0	22	0	0
T18	3275	3	0	0
T19	93730	0	0	0
T20	8052	1	0	0
T21	2131	1	0	0
T22	1591	0	0	0
T23	0	4	0	0
T24	2312	4	0	0
T25	5350	0	0	0
T129	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882546	1932	0	0
T1	247770	0	0	0
T2	152180	3	0	0
T5	22172	0	0	0
T11	0	9	0	0
T12	0	17	0	0
T13	0	9	0	0
T18	3275	2	0	0
T19	93730	0	0	0
T20	8052	1	0	0
T21	2131	1	0	0
T22	1591	0	0	0
T23	0	1	0	0
T24	2312	2	0	0
T25	5350	0	0	0
T129	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	426882546	3740	0	0
TransStop_A	426882546	1912	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882546	3740	0	0
T1	247770	0	0	0
T2	152180	6	0	0
T5	22172	0	0	0
T11	0	16	0	0
T12	0	26	0	0
T13	0	25	0	0
T18	3275	2	0	0
T19	93730	0	0	0
T20	8052	1	0	0
T21	2131	1	0	0
T22	1591	0	0	0
T23	0	5	0	0
T24	2312	5	0	0
T25	5350	0	0	0
T129	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882546	1912	0	0
T1	247770	0	0	0
T2	152180	3	0	0
T5	22172	0	0	0
T11	0	8	0	0
T12	0	14	0	0
T13	0	14	0	0
T18	3275	2	0	0
T19	93730	0	0	0
T20	8052	1	0	0
T21	2131	1	0	0
T22	1591	0	0	0
T23	0	3	0	0
T24	2312	3	0	0
T25	5350	0	0	0
T129	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	426882546	3748	0	0
TransStop_A	426882546	1943	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882546	3748	0	0
T1	247770	0	0	0
T2	152180	7	0	0
T5	22172	0	0	0
T11	0	18	0	0
T12	0	23	0	0
T13	0	24	0	0
T18	3275	2	0	0
T19	93730	0	0	0
T20	8052	1	0	0
T21	2131	1	0	0
T22	1591	0	0	0
T23	0	2	0	0
T24	2312	2	0	0
T25	5350	0	0	0
T129	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882546	1943	0	0
T1	247770	0	0	0
T2	152180	5	0	0
T5	22172	0	0	0
T11	0	10	0	0
T12	0	13	0	0
T13	0	13	0	0
T18	3275	2	0	0
T19	93730	0	0	0
T20	8052	1	0	0
T21	2131	1	0	0
T22	1591	0	0	0
T23	0	2	0	0
T24	2312	2	0	0
T25	5350	0	0	0
T129	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	426882546	3761	0	0
TransStop_A	426882546	1951	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882546	3761	0	0
T1	247770	0	0	0
T2	152180	9	0	0
T5	22172	0	0	0
T11	0	13	0	0
T12	0	31	0	0
T13	0	28	0	0
T18	3275	2	0	0
T19	93730	0	0	0
T20	8052	1	0	0
T21	2131	1	0	0
T22	1591	0	0	0
T23	0	2	0	0
T24	2312	4	0	0
T25	5350	0	0	0
T129	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882546	1951	0	0
T1	247770	0	0	0
T2	152180	4	0	0
T5	22172	0	0	0
T11	0	7	0	0
T12	0	21	0	0
T13	0	16	0	0
T18	3275	2	0	0
T19	93730	0	0	0
T20	8052	1	0	0
T21	2131	1	0	0
T22	1591	0	0	0
T23	0	1	0	0
T24	2312	4	0	0
T25	5350	0	0	0
T129	0	1	0	0