Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	160447183	5445911	0	0
clk_enables_rd_A	160447183	42942	0	0
clk_hints_rd_A	160447183	37441	0	0
extclk_ctrl_rd_A	160447183	48042	0	0
extclk_ctrl_regwen_rd_A	160447183	36019	0	0
jitter_enable_rd_A	160447183	49793	0	0
jitter_regwen_rd_A	160447183	40288	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	5445911	0	0
T12	182169	54488	0	0
T13	195983	68500	0	0
T14	18921	0	0	0
T16	0	112907	0	0
T27	0	51185	0	0
T29	0	115820	0	0
T39	1626	0	0	0
T76	0	149212	0	0
T77	0	84342	0	0
T78	0	155678	0	0
T79	0	126031	0	0
T80	0	200337	0	0
T81	6642	0	0	0
T82	1454	0	0	0
T83	973	0	0	0
T84	2238	0	0	0
T85	1827	0	0	0
T86	814	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	42942	0	0
T4	109917	0	0	0
T12	0	1146	0	0
T21	2044	3	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T27	0	1951	0	0
T29	0	2610	0	0
T30	115300	0	0	0
T32	1008	0	0	0
T40	1736	0	0	0
T81	0	5	0	0
T123	1108	0	0	0
T124	1922	0	0	0
T125	1884	0	0	0
T147	0	1	0	0
T148	0	7	0	0
T149	0	10	0	0
T150	0	5	0	0
T151	0	3	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	37441	0	0
T2	107786	2	0	0
T4	109917	0	0	0
T12	0	1098	0	0
T19	23934	0	0	0
T20	1609	5	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T27	0	1817	0	0
T29	0	1932	0	0
T40	1736	0	0	0
T81	0	5	0	0
T123	1108	0	0	0
T124	1922	0	0	0
T147	0	2	0	0
T148	0	3	0	0
T149	0	5	0	0
T150	0	3	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	48042	0	0
T3	23949	0	0	0
T12	0	1465	0	0
T30	115300	92	0	0
T31	32148	0	0	0
T32	1008	0	0	0
T33	1346	0	0	0
T64	0	73	0	0
T124	1922	22	0	0
T125	1884	37	0	0
T126	1303	10	0	0
T128	0	71	0	0
T129	3429	0	0	0
T152	0	35	0	0
T153	0	51	0	0
T154	0	6	0	0
T155	1189	0	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	36019	0	0
T3	23949	0	0	0
T11	150065	0	0	0
T12	0	1096	0	0
T27	0	1545	0	0
T29	0	2060	0	0
T30	115300	29	0	0
T31	32148	0	0	0
T33	1346	0	0	0
T34	1598	0	0	0
T64	0	39	0	0
T88	0	7	0	0
T91	0	34	0	0
T126	1303	0	0	0
T127	1067	0	0	0
T129	3429	0	0	0
T155	1189	0	0	0
T156	0	63	0	0
T157	0	37	0	0
T158	0	21	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	49793	0	0
T2	107786	113	0	0
T4	109917	0	0	0
T12	0	1449	0	0
T19	23934	0	0	0
T20	1609	68	0	0
T21	2044	47	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T27	0	2107	0	0
T29	0	3218	0	0
T40	1736	0	0	0
T81	0	90	0	0
T123	1108	0	0	0
T124	1922	0	0	0
T147	0	62	0	0
T148	0	53	0	0
T149	0	349	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	40288	0	0
T12	182169	1067	0	0
T13	195983	0	0	0
T14	18921	0	0	0
T27	0	1822	0	0
T29	0	2548	0	0
T35	0	688	0	0
T39	1626	0	0	0
T81	6642	0	0	0
T82	1454	0	0	0
T83	973	0	0	0
T84	2238	0	0	0
T85	1827	0	0	0
T86	814	0	0	0
T159	0	2218	0	0
T160	0	4581	0	0
T161	0	2389	0	0
T162	0	5582	0	0
T163	0	2840	0	0
T164	0	2031	0	0