Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T30,T64
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1604471830	1465064	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1604471830	273785	0	0
SrcBusyKnown_A	1604471830	1574864020	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604471830	1465064	0	0
T1	2403430	3390	0	0
T2	1077860	4745	0	0
T3	0	561	0	0
T4	1099170	3780	0	0
T5	47880	123	0	0
T11	0	4636	0	0
T18	16040	0	0	0
T19	239340	532	0	0
T20	16090	0	0	0
T21	20440	0	0	0
T22	15750	0	0	0
T23	20090	0	0	0
T26	0	464	0	0
T30	0	4679	0	0
T31	0	724	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1565822	1564812	0	0
T2	4133652	4128850	0	0
T5	160106	158678	0	0
T6	25832	25184	0	0
T7	18038	16678	0	0
T8	43916	43056	0	0
T18	20612	19802	0	0
T19	531804	531270	0	0
T24	14448	13724	0	0
T25	33880	32910	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604471830	273785	0	0
T1	2403430	420	0	0
T2	1077860	1860	0	0
T3	0	160	0	0
T4	1099170	454	0	0
T5	47880	40	0	0
T11	0	1580	0	0
T18	16040	0	0	0
T19	239340	160	0	0
T20	16090	0	0	0
T21	20440	0	0	0
T22	15750	0	0	0
T23	20090	0	0	0
T26	0	140	0	0
T30	0	549	0	0
T31	0	200	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604471830	1574864020	0	0
T1	2403430	2401800	0	0
T2	1077860	1076340	0	0
T5	47880	47450	0	0
T6	10640	10380	0	0
T7	14390	13190	0	0
T8	16800	16420	0	0
T18	16040	15360	0	0
T19	239340	239110	0	0
T24	18960	17810	0	0
T25	13900	13470	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160447183	90515	0	0
DstReqKnown_A	401393048	396685314	0	0
SrcAckBusyChk_A	160447183	24739	0	0
SrcBusyKnown_A	160447183	157486402	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	90515	0	0
T1	240343	212	0	0
T2	107786	465	0	0
T3	0	41	0	0
T4	109917	190	0	0
T5	4788	10	0	0
T11	0	404	0	0
T18	1604	0	0	0
T19	23934	39	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	34	0	0
T30	0	228	0	0
T31	0	55	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401393048	396685314	0	0
T1	237851	237689	0	0
T2	139752	139529	0	0
T5	27045	26800	0	0
T6	3970	3863	0	0
T7	2764	2533	0	0
T8	6455	6306	0	0
T18	3143	3008	0	0
T19	72698	72605	0	0
T24	2219	2085	0	0
T25	5136	4973	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	24739	0	0
T1	240343	42	0	0
T2	107786	186	0	0
T3	0	16	0	0
T4	109917	32	0	0
T5	4788	4	0	0
T11	0	158	0	0
T18	1604	0	0	0
T19	23934	16	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	14	0	0
T30	0	38	0	0
T31	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	157486402	0	0
T1	240343	240180	0	0
T2	107786	107634	0	0
T5	4788	4745	0	0
T6	1064	1038	0	0
T7	1439	1319	0	0
T8	1680	1642	0	0
T18	1604	1536	0	0
T19	23934	23911	0	0
T24	1896	1781	0	0
T25	1390	1347	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160447183	131525	0	0
DstReqKnown_A	199776898	198597818	0	0
SrcAckBusyChk_A	160447183	24739	0	0
SrcBusyKnown_A	160447183	157486402	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	131525	0	0
T1	240343	345	0	0
T2	107786	465	0	0
T3	0	58	0	0
T4	109917	267	0	0
T5	4788	12	0	0
T11	0	445	0	0
T18	1604	0	0	0
T19	23934	55	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	48	0	0
T30	0	321	0	0
T31	0	73	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199776898	198597818	0	0
T1	118906	118844	0	0
T2	698198	697647	0	0
T5	13462	13400	0	0
T6	1966	1931	0	0
T7	1329	1267	0	0
T8	3701	3666	0	0
T18	1545	1504	0	0
T19	36323	36302	0	0
T24	1056	1042	0	0
T25	2591	2543	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	24739	0	0
T1	240343	42	0	0
T2	107786	186	0	0
T3	0	16	0	0
T4	109917	32	0	0
T5	4788	4	0	0
T11	0	158	0	0
T18	1604	0	0	0
T19	23934	16	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	14	0	0
T30	0	38	0	0
T31	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	157486402	0	0
T1	240343	240180	0	0
T2	107786	107634	0	0
T5	4788	4745	0	0
T6	1064	1038	0	0
T7	1439	1319	0	0
T8	1680	1642	0	0
T18	1604	1536	0	0
T19	23934	23911	0	0
T24	1896	1781	0	0
T25	1390	1347	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160447183	212781	0	0
DstReqKnown_A	99887880	99298426	0	0
SrcAckBusyChk_A	160447183	24739	0	0
SrcBusyKnown_A	160447183	157486402	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	212781	0	0
T1	240343	595	0	0
T2	107786	514	0	0
T3	0	81	0	0
T4	109917	453	0	0
T5	4788	18	0	0
T11	0	609	0	0
T18	1604	0	0	0
T19	23934	78	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	68	0	0
T30	0	537	0	0
T31	0	106	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99887880	99298426	0	0
T1	59453	59422	0	0
T2	349099	348823	0	0
T5	6731	6700	0	0
T6	983	966	0	0
T7	664	633	0	0
T8	1850	1833	0	0
T18	773	752	0	0
T19	18162	18152	0	0
T24	528	521	0	0
T25	1295	1271	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	24739	0	0
T1	240343	42	0	0
T2	107786	186	0	0
T3	0	16	0	0
T4	109917	32	0	0
T5	4788	4	0	0
T11	0	158	0	0
T18	1604	0	0	0
T19	23934	16	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	14	0	0
T30	0	38	0	0
T31	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	157486402	0	0
T1	240343	240180	0	0
T2	107786	107634	0	0
T5	4788	4745	0	0
T6	1064	1038	0	0
T7	1439	1319	0	0
T8	1680	1642	0	0
T18	1604	1536	0	0
T19	23934	23911	0	0
T24	1896	1781	0	0
T25	1390	1347	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160447183	89304	0	0
DstReqKnown_A	429686150	424746271	0	0
SrcAckBusyChk_A	160447183	24739	0	0
SrcBusyKnown_A	160447183	157486402	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	89304	0	0
T1	240343	210	0	0
T2	107786	465	0	0
T3	0	39	0	0
T4	109917	154	0	0
T5	4788	10	0	0
T11	0	404	0	0
T18	1604	0	0	0
T19	23934	39	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	34	0	0
T30	0	185	0	0
T31	0	52	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429686150	424746271	0	0
T1	247770	247601	0	0
T2	152180	151947	0	0
T5	22172	21918	0	0
T6	3970	3859	0	0
T7	2880	2639	0	0
T8	6724	6569	0	0
T18	3274	3133	0	0
T19	93729	93632	0	0
T24	2311	2171	0	0
T25	5350	5181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	24739	0	0
T1	240343	42	0	0
T2	107786	186	0	0
T3	0	16	0	0
T4	109917	32	0	0
T5	4788	4	0	0
T11	0	158	0	0
T18	1604	0	0	0
T19	23934	16	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	14	0	0
T30	0	38	0	0
T31	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	157486402	0	0
T1	240343	240180	0	0
T2	107786	107634	0	0
T5	4788	4745	0	0
T6	1064	1038	0	0
T7	1439	1319	0	0
T8	1680	1642	0	0
T18	1604	1536	0	0
T19	23934	23911	0	0
T24	1896	1781	0	0
T25	1390	1347	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160447183	130462	0	0
DstReqKnown_A	206042045	203659312	0	0
SrcAckBusyChk_A	160447183	24262	0	0
SrcBusyKnown_A	160447183	157486402	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	130462	0	0
T1	240343	334	0	0
T2	107786	465	0	0
T3	0	56	0	0
T4	109917	143	0	0
T5	4788	12	0	0
T11	0	439	0	0
T18	1604	0	0	0
T19	23934	55	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	48	0	0
T30	0	206	0	0
T31	0	75	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206042045	203659312	0	0
T1	118931	118850	0	0
T2	727597	726479	0	0
T5	10643	10521	0	0
T6	2027	1973	0	0
T7	1382	1267	0	0
T8	3228	3154	0	0
T18	1571	1504	0	0
T19	44990	44944	0	0
T24	1110	1043	0	0
T25	2568	2487	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	24262	0	0
T1	240343	42	0	0
T2	107786	186	0	0
T3	0	16	0	0
T4	109917	16	0	0
T5	4788	4	0	0
T11	0	158	0	0
T18	1604	0	0	0
T19	23934	16	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	14	0	0
T30	0	21	0	0
T31	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	157486402	0	0
T1	240343	240180	0	0
T2	107786	107634	0	0
T5	4788	4745	0	0
T6	1064	1038	0	0
T7	1439	1319	0	0
T8	1680	1642	0	0
T18	1604	1536	0	0
T19	23934	23911	0	0
T24	1896	1781	0	0
T25	1390	1347	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T30,T64
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160447183	111800	0	0
DstReqKnown_A	401393048	396685314	0	0
SrcAckBusyChk_A	160447183	30122	0	0
SrcBusyKnown_A	160447183	157486402	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	111800	0	0
T1	240343	212	0	0
T2	107786	464	0	0
T3	0	43	0	0
T4	109917	368	0	0
T5	4788	10	0	0
T11	0	406	0	0
T18	1604	0	0	0
T19	23934	39	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	34	0	0
T30	0	458	0	0
T31	0	53	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401393048	396685314	0	0
T1	237851	237689	0	0
T2	139752	139529	0	0
T5	27045	26800	0	0
T6	3970	3863	0	0
T7	2764	2533	0	0
T8	6455	6306	0	0
T18	3143	3008	0	0
T19	72698	72605	0	0
T24	2219	2085	0	0
T25	5136	4973	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	30122	0	0
T1	240343	42	0	0
T2	107786	186	0	0
T3	0	16	0	0
T4	109917	64	0	0
T5	4788	4	0	0
T11	0	158	0	0
T18	1604	0	0	0
T19	23934	16	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	14	0	0
T30	0	76	0	0
T31	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	157486402	0	0
T1	240343	240180	0	0
T2	107786	107634	0	0
T5	4788	4745	0	0
T6	1064	1038	0	0
T7	1439	1319	0	0
T8	1680	1642	0	0
T18	1604	1536	0	0
T19	23934	23911	0	0
T24	1896	1781	0	0
T25	1390	1347	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T30,T64
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160447183	162584	0	0
DstReqKnown_A	199776898	198597818	0	0
SrcAckBusyChk_A	160447183	30134	0	0
SrcBusyKnown_A	160447183	157486402	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	162584	0	0
T1	240343	342	0	0
T2	107786	464	0	0
T3	0	59	0	0
T4	109917	526	0	0
T5	4788	12	0	0
T11	0	452	0	0
T18	1604	0	0	0
T19	23934	55	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	48	0	0
T30	0	647	0	0
T31	0	74	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199776898	198597818	0	0
T1	118906	118844	0	0
T2	698198	697647	0	0
T5	13462	13400	0	0
T6	1966	1931	0	0
T7	1329	1267	0	0
T8	3701	3666	0	0
T18	1545	1504	0	0
T19	36323	36302	0	0
T24	1056	1042	0	0
T25	2591	2543	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	30134	0	0
T1	240343	42	0	0
T2	107786	186	0	0
T3	0	16	0	0
T4	109917	64	0	0
T5	4788	4	0	0
T11	0	158	0	0
T18	1604	0	0	0
T19	23934	16	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	14	0	0
T30	0	76	0	0
T31	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	157486402	0	0
T1	240343	240180	0	0
T2	107786	107634	0	0
T5	4788	4745	0	0
T6	1064	1038	0	0
T7	1439	1319	0	0
T8	1680	1642	0	0
T18	1604	1536	0	0
T19	23934	23911	0	0
T24	1896	1781	0	0
T25	1390	1347	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T30,T64
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160447183	263241	0	0
DstReqKnown_A	99887880	99298426	0	0
SrcAckBusyChk_A	160447183	30118	0	0
SrcBusyKnown_A	160447183	157486402	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	263241	0	0
T1	240343	593	0	0
T2	107786	515	0	0
T3	0	83	0	0
T4	109917	905	0	0
T5	4788	16	0	0
T11	0	622	0	0
T18	1604	0	0	0
T19	23934	78	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	68	0	0
T30	0	1119	0	0
T31	0	108	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99887880	99298426	0	0
T1	59453	59422	0	0
T2	349099	348823	0	0
T5	6731	6700	0	0
T6	983	966	0	0
T7	664	633	0	0
T8	1850	1833	0	0
T18	773	752	0	0
T19	18162	18152	0	0
T24	528	521	0	0
T25	1295	1271	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	30118	0	0
T1	240343	42	0	0
T2	107786	186	0	0
T3	0	16	0	0
T4	109917	64	0	0
T5	4788	4	0	0
T11	0	158	0	0
T18	1604	0	0	0
T19	23934	16	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	14	0	0
T30	0	76	0	0
T31	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	157486402	0	0
T1	240343	240180	0	0
T2	107786	107634	0	0
T5	4788	4745	0	0
T6	1064	1038	0	0
T7	1439	1319	0	0
T8	1680	1642	0	0
T18	1604	1536	0	0
T19	23934	23911	0	0
T24	1896	1781	0	0
T25	1390	1347	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T30,T64
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160447183	110504	0	0
DstReqKnown_A	429686150	424746271	0	0
SrcAckBusyChk_A	160447183	30318	0	0
SrcBusyKnown_A	160447183	157486402	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	110504	0	0
T1	240343	206	0	0
T2	107786	464	0	0
T3	0	41	0	0
T4	109917	297	0	0
T5	4788	10	0	0
T11	0	406	0	0
T18	1604	0	0	0
T19	23934	39	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	34	0	0
T30	0	379	0	0
T31	0	52	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429686150	424746271	0	0
T1	247770	247601	0	0
T2	152180	151947	0	0
T5	22172	21918	0	0
T6	3970	3859	0	0
T7	2880	2639	0	0
T8	6724	6569	0	0
T18	3274	3133	0	0
T19	93729	93632	0	0
T24	2311	2171	0	0
T25	5350	5181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	30318	0	0
T1	240343	42	0	0
T2	107786	186	0	0
T3	0	16	0	0
T4	109917	64	0	0
T5	4788	4	0	0
T11	0	158	0	0
T18	1604	0	0	0
T19	23934	16	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	14	0	0
T30	0	76	0	0
T31	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	157486402	0	0
T1	240343	240180	0	0
T2	107786	107634	0	0
T5	4788	4745	0	0
T6	1064	1038	0	0
T7	1439	1319	0	0
T8	1680	1642	0	0
T18	1604	1536	0	0
T19	23934	23911	0	0
T24	1896	1781	0	0
T25	1390	1347	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T30,T64
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160447183	162348	0	0
DstReqKnown_A	206042045	203659312	0	0
SrcAckBusyChk_A	160447183	29875	0	0
SrcBusyKnown_A	160447183	157486402	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	162348	0	0
T1	240343	341	0	0
T2	107786	464	0	0
T3	0	60	0	0
T4	109917	477	0	0
T5	4788	13	0	0
T11	0	449	0	0
T18	1604	0	0	0
T19	23934	55	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	48	0	0
T30	0	599	0	0
T31	0	76	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206042045	203659312	0	0
T1	118931	118850	0	0
T2	727597	726479	0	0
T5	10643	10521	0	0
T6	2027	1973	0	0
T7	1382	1267	0	0
T8	3228	3154	0	0
T18	1571	1504	0	0
T19	44990	44944	0	0
T24	1110	1043	0	0
T25	2568	2487	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	29875	0	0
T1	240343	42	0	0
T2	107786	186	0	0
T3	0	16	0	0
T4	109917	54	0	0
T5	4788	4	0	0
T11	0	158	0	0
T18	1604	0	0	0
T19	23934	16	0	0
T20	1609	0	0	0
T21	2044	0	0	0
T22	1575	0	0	0
T23	2009	0	0	0
T26	0	14	0	0
T30	0	72	0	0
T31	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160447183	157486402	0	0
T1	240343	240180	0	0
T2	107786	107634	0	0
T5	4788	4745	0	0
T6	1064	1038	0	0
T7	1439	1319	0	0
T8	1680	1642	0	0
T18	1604	1536	0	0
T19	23934	23911	0	0
T24	1896	1781	0	0
T25	1390	1347	0	0