Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T24
1	0	Covered	T8,T25,T40
1	1	Covered	T8,T25,T22

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	398701739	4072	0	0
g_div2.Div2Whole_A	398701739	4921	0	0
g_div4.Div4Stepped_A	198478490	3960	0	0
g_div4.Div4Whole_A	198478490	4616	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398701739	4072	0	0
T1	237852	0	0	0
T2	139752	0	0	0
T5	27045	0	0	0
T8	6456	7	0	0
T11	0	33	0	0
T12	0	84	0	0
T18	3143	0	0	0
T19	72698	0	0	0
T20	7729	0	0	0
T21	2045	0	0	0
T24	2219	0	0	0
T25	5137	2	0	0
T40	0	9	0	0
T123	0	4	0	0
T124	0	1	0	0
T125	0	8	0	0
T127	0	4	0	0
T128	0	5	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398701739	4921	0	0
T1	237852	0	0	0
T2	139752	0	0	0
T5	27045	0	0	0
T8	6456	8	0	0
T11	0	33	0	0
T18	3143	0	0	0
T19	72698	0	0	0
T20	7729	0	0	0
T21	2045	0	0	0
T22	0	1	0	0
T24	2219	0	0	0
T25	5137	3	0	0
T40	0	8	0	0
T123	0	4	0	0
T124	0	1	0	0
T125	0	8	0	0
T127	0	5	0	0
T128	0	7	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198478490	3960	0	0
T1	118907	0	0	0
T2	698198	0	0	0
T5	13463	0	0	0
T8	3701	7	0	0
T11	0	33	0	0
T12	0	84	0	0
T18	1546	0	0	0
T19	36324	0	0	0
T20	3818	0	0	0
T21	997	0	0	0
T24	1057	0	0	0
T25	2591	2	0	0
T40	0	9	0	0
T123	0	3	0	0
T124	0	1	0	0
T125	0	8	0	0
T127	0	4	0	0
T128	0	5	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198478490	4616	0	0
T1	118907	0	0	0
T2	698198	0	0	0
T5	13463	0	0	0
T8	3701	7	0	0
T11	0	33	0	0
T18	1546	0	0	0
T19	36324	0	0	0
T20	3818	0	0	0
T21	997	0	0	0
T22	0	1	0	0
T24	1057	0	0	0
T25	2591	3	0	0
T40	0	8	0	0
T123	0	4	0	0
T124	0	1	0	0
T125	0	8	0	0
T127	0	4	0	0
T128	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T24
1	0	Covered	T8,T25,T40
1	1	Covered	T8,T25,T22

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	398701739	4072	0	0
g_div2.Div2Whole_A	398701739	4921	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398701739	4072	0	0
T1	237852	0	0	0
T2	139752	0	0	0
T5	27045	0	0	0
T8	6456	7	0	0
T11	0	33	0	0
T12	0	84	0	0
T18	3143	0	0	0
T19	72698	0	0	0
T20	7729	0	0	0
T21	2045	0	0	0
T24	2219	0	0	0
T25	5137	2	0	0
T40	0	9	0	0
T123	0	4	0	0
T124	0	1	0	0
T125	0	8	0	0
T127	0	4	0	0
T128	0	5	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398701739	4921	0	0
T1	237852	0	0	0
T2	139752	0	0	0
T5	27045	0	0	0
T8	6456	8	0	0
T11	0	33	0	0
T18	3143	0	0	0
T19	72698	0	0	0
T20	7729	0	0	0
T21	2045	0	0	0
T22	0	1	0	0
T24	2219	0	0	0
T25	5137	3	0	0
T40	0	8	0	0
T123	0	4	0	0
T124	0	1	0	0
T125	0	8	0	0
T127	0	5	0	0
T128	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T24
1	0	Covered	T8,T25,T40
1	1	Covered	T8,T25,T22

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	198478490	3960	0	0
g_div4.Div4Whole_A	198478490	4616	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198478490	3960	0	0
T1	118907	0	0	0
T2	698198	0	0	0
T5	13463	0	0	0
T8	3701	7	0	0
T11	0	33	0	0
T12	0	84	0	0
T18	1546	0	0	0
T19	36324	0	0	0
T20	3818	0	0	0
T21	997	0	0	0
T24	1057	0	0	0
T25	2591	2	0	0
T40	0	9	0	0
T123	0	3	0	0
T124	0	1	0	0
T125	0	8	0	0
T127	0	4	0	0
T128	0	5	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198478490	4616	0	0
T1	118907	0	0	0
T2	698198	0	0	0
T5	13463	0	0	0
T8	3701	7	0	0
T11	0	33	0	0
T18	1546	0	0	0
T19	36324	0	0	0
T20	3818	0	0	0
T21	997	0	0	0
T22	0	1	0	0
T24	1057	0	0	0
T25	2591	3	0	0
T40	0	8	0	0
T123	0	4	0	0
T124	0	1	0	0
T125	0	8	0	0
T127	0	4	0	0
T128	0	7	0	0