Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47208	0	0
CgEnOn_A	2147483647	38148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47208	0	0
T1	2556877	3	0	0
T2	4712973	101	0	0
T5	251613	3	0	0
T6	41651	58	0	0
T7	29504	31	0	0
T8	71284	3	0	0
T18	33683	6	0	0
T19	898054	3	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	23638	7	0	0
T25	55302	3	0	0
T38	0	18	0	0
T39	0	20	0	0
T77	0	5	0	0
T165	0	20	0	0
T166	0	10	0	0
T167	0	20	0	0
T168	0	5	0	0
T169	0	5	0	0
T170	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38148	0	0
T1	2556877	0	0	0
T2	4712973	65	0	0
T5	251613	0	0	0
T6	41651	55	0	0
T7	29504	28	0	0
T8	71284	0	0	0
T11	0	144	0	0
T12	0	260	0	0
T13	0	51	0	0
T18	33683	0	0	0
T19	898054	0	0	0
T20	0	4	0	0
T21	0	3	0	0
T24	23638	4	0	0
T25	55302	0	0	0
T38	0	27	0	0
T39	0	20	0	0
T77	0	4	0	0
T155	0	15	0	0
T165	0	20	0	0
T166	0	10	0	0
T167	0	20	0	0
T168	0	5	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	1	0	0
T172	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	198478070	155	0	0
CgEnOn_A	198478070	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198478070	155	0	0
T1	118906	0	0	0
T2	698198	0	0	0
T5	13462	0	0	0
T6	1966	6	0	0
T7	1329	0	0	0
T8	3701	0	0	0
T18	1545	0	0	0
T19	36323	0	0	0
T24	1056	0	0	0
T25	2591	0	0	0
T38	0	3	0	0
T39	0	4	0	0
T77	0	1	0	0
T165	0	4	0	0
T166	0	2	0	0
T167	0	4	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198478070	155	0	0
T1	118906	0	0	0
T2	698198	0	0	0
T5	13462	0	0	0
T6	1966	6	0	0
T7	1329	0	0	0
T8	3701	0	0	0
T18	1545	0	0	0
T19	36323	0	0	0
T24	1056	0	0	0
T25	2591	0	0	0
T38	0	3	0	0
T39	0	4	0	0
T77	0	1	0	0
T165	0	4	0	0
T166	0	2	0	0
T167	0	4	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99238459	155	0	0
CgEnOn_A	99238459	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99238459	155	0	0
T1	59453	0	0	0
T2	349099	0	0	0
T5	6731	0	0	0
T6	983	6	0	0
T7	664	0	0	0
T8	1850	0	0	0
T18	773	0	0	0
T19	18162	0	0	0
T24	528	0	0	0
T25	1295	0	0	0
T38	0	3	0	0
T39	0	4	0	0
T77	0	1	0	0
T165	0	4	0	0
T166	0	2	0	0
T167	0	4	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99238459	155	0	0
T1	59453	0	0	0
T2	349099	0	0	0
T5	6731	0	0	0
T6	983	6	0	0
T7	664	0	0	0
T8	1850	0	0	0
T18	773	0	0	0
T19	18162	0	0	0
T24	528	0	0	0
T25	1295	0	0	0
T38	0	3	0	0
T39	0	4	0	0
T77	0	1	0	0
T165	0	4	0	0
T166	0	2	0	0
T167	0	4	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	398701291	155	0	0
CgEnOn_A	398701291	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398701291	155	0	0
T1	237851	0	0	0
T2	139752	0	0	0
T5	27045	0	0	0
T6	3970	6	0	0
T7	2764	0	0	0
T8	6455	0	0	0
T18	3143	0	0	0
T19	72698	0	0	0
T24	2219	0	0	0
T25	5136	0	0	0
T38	0	3	0	0
T39	0	4	0	0
T77	0	1	0	0
T165	0	4	0	0
T166	0	2	0	0
T167	0	4	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398701291	151	0	0
T1	237851	0	0	0
T2	139752	0	0	0
T5	27045	0	0	0
T6	3970	6	0	0
T7	2764	0	0	0
T8	6455	0	0	0
T18	3143	0	0	0
T19	72698	0	0	0
T24	2219	0	0	0
T25	5136	0	0	0
T38	0	3	0	0
T39	0	4	0	0
T165	0	4	0	0
T166	0	2	0	0
T167	0	4	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426882127	163	0	0
CgEnOn_A	426882127	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882127	163	0	0
T1	247770	0	0	0
T2	152180	0	0	0
T5	22172	0	0	0
T6	3970	7	0	0
T7	2880	0	0	0
T8	6724	0	0	0
T18	3274	0	0	0
T19	93729	0	0	0
T24	2311	0	0	0
T25	5350	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T165	0	3	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	4	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882127	159	0	0
T1	247770	0	0	0
T2	152180	0	0	0
T5	22172	0	0	0
T6	3970	7	0	0
T7	2880	0	0	0
T8	6724	0	0	0
T18	3274	0	0	0
T19	93729	0	0	0
T24	2311	0	0	0
T25	5350	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T165	0	3	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	4	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99238459	155	0	0
CgEnOn_A	99238459	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99238459	155	0	0
T1	59453	0	0	0
T2	349099	0	0	0
T5	6731	0	0	0
T6	983	6	0	0
T7	664	0	0	0
T8	1850	0	0	0
T18	773	0	0	0
T19	18162	0	0	0
T24	528	0	0	0
T25	1295	0	0	0
T38	0	3	0	0
T39	0	4	0	0
T77	0	1	0	0
T165	0	4	0	0
T166	0	2	0	0
T167	0	4	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99238459	155	0	0
T1	59453	0	0	0
T2	349099	0	0	0
T5	6731	0	0	0
T6	983	6	0	0
T7	664	0	0	0
T8	1850	0	0	0
T18	773	0	0	0
T19	18162	0	0	0
T24	528	0	0	0
T25	1295	0	0	0
T38	0	3	0	0
T39	0	4	0	0
T77	0	1	0	0
T165	0	4	0	0
T166	0	2	0	0
T167	0	4	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426882127	163	0	0
CgEnOn_A	426882127	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882127	163	0	0
T1	247770	0	0	0
T2	152180	0	0	0
T5	22172	0	0	0
T6	3970	7	0	0
T7	2880	0	0	0
T8	6724	0	0	0
T18	3274	0	0	0
T19	93729	0	0	0
T24	2311	0	0	0
T25	5350	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T165	0	3	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	4	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882127	159	0	0
T1	247770	0	0	0
T2	152180	0	0	0
T5	22172	0	0	0
T6	3970	7	0	0
T7	2880	0	0	0
T8	6724	0	0	0
T18	3274	0	0	0
T19	93729	0	0	0
T24	2311	0	0	0
T25	5350	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T165	0	3	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	4	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99238459	155	0	0
CgEnOn_A	99238459	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99238459	155	0	0
T1	59453	0	0	0
T2	349099	0	0	0
T5	6731	0	0	0
T6	983	6	0	0
T7	664	0	0	0
T8	1850	0	0	0
T18	773	0	0	0
T19	18162	0	0	0
T24	528	0	0	0
T25	1295	0	0	0
T38	0	3	0	0
T39	0	4	0	0
T77	0	1	0	0
T165	0	4	0	0
T166	0	2	0	0
T167	0	4	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99238459	155	0	0
T1	59453	0	0	0
T2	349099	0	0	0
T5	6731	0	0	0
T6	983	6	0	0
T7	664	0	0	0
T8	1850	0	0	0
T18	773	0	0	0
T19	18162	0	0	0
T24	528	0	0	0
T25	1295	0	0	0
T38	0	3	0	0
T39	0	4	0	0
T77	0	1	0	0
T165	0	4	0	0
T166	0	2	0	0
T167	0	4	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T38,T39
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	198478070	7643	0	0
CgEnOn_A	198478070	5387	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198478070	7643	0	0
T1	118906	1	0	0
T2	698198	32	0	0
T5	13462	1	0	0
T6	1966	7	0	0
T7	1329	10	0	0
T8	3701	1	0	0
T18	1545	1	0	0
T19	36323	1	0	0
T24	1056	1	0	0
T25	2591	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198478070	5387	0	0
T1	118906	0	0	0
T2	698198	20	0	0
T5	13462	0	0	0
T6	1966	6	0	0
T7	1329	9	0	0
T8	3701	0	0	0
T11	0	38	0	0
T12	0	89	0	0
T18	1545	0	0	0
T19	36323	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	1056	0	0	0
T25	2591	0	0	0
T38	0	3	0	0
T155	0	4	0	0
T172	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T38,T39
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99238459	7550	0	0
CgEnOn_A	99238459	5294	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99238459	7550	0	0
T1	59453	1	0	0
T2	349099	31	0	0
T5	6731	1	0	0
T6	983	7	0	0
T7	664	12	0	0
T8	1850	1	0	0
T18	773	1	0	0
T19	18162	1	0	0
T24	528	1	0	0
T25	1295	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99238459	5294	0	0
T1	59453	0	0	0
T2	349099	19	0	0
T5	6731	0	0	0
T6	983	6	0	0
T7	664	11	0	0
T8	1850	0	0	0
T11	0	44	0	0
T12	0	84	0	0
T13	0	51	0	0
T18	773	0	0	0
T19	18162	0	0	0
T20	0	1	0	0
T24	528	0	0	0
T25	1295	0	0	0
T38	0	3	0	0
T155	0	5	0	0
T172	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T38,T39
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	398701291	7640	0	0
CgEnOn_A	398701291	5380	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398701291	7640	0	0
T1	237851	1	0	0
T2	139752	31	0	0
T5	27045	1	0	0
T6	3970	7	0	0
T7	2764	9	0	0
T8	6455	1	0	0
T18	3143	1	0	0
T19	72698	1	0	0
T24	2219	1	0	0
T25	5136	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398701291	5380	0	0
T1	237851	0	0	0
T2	139752	19	0	0
T5	27045	0	0	0
T6	3970	6	0	0
T7	2764	8	0	0
T8	6455	0	0	0
T11	0	45	0	0
T12	0	87	0	0
T18	3143	0	0	0
T19	72698	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	2219	0	0	0
T25	5136	0	0	0
T38	0	3	0	0
T155	0	6	0	0
T172	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T38,T39
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	204696144	7612	0	0
CgEnOn_A	204696144	5352	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204696144	7612	0	0
T1	118931	1	0	0
T2	727597	33	0	0
T5	10643	1	0	0
T6	2027	5	0	0
T7	1382	11	0	0
T8	3228	1	0	0
T18	1571	1	0	0
T19	44990	1	0	0
T24	1110	1	0	0
T25	2568	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204696144	5352	0	0
T1	118931	0	0	0
T2	727597	21	0	0
T5	10643	0	0	0
T6	2027	4	0	0
T7	1382	10	0	0
T8	3228	0	0	0
T11	0	45	0	0
T12	0	88	0	0
T18	1571	0	0	0
T19	44990	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	1110	0	0	0
T25	2568	0	0	0
T38	0	2	0	0
T155	0	5	0	0
T172	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Covered	T24,T18,T2
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426882127	3924	0	0
CgEnOn_A	426882127	3920	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882127	3924	0	0
T1	247770	0	0	0
T2	152180	7	0	0
T5	22172	0	0	0
T6	3970	7	0	0
T7	2880	0	0	0
T8	6724	0	0	0
T11	0	17	0	0
T18	3274	3	0	0
T19	93729	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	4	0	0
T24	2311	4	0	0
T25	5350	0	0	0
T38	0	3	0	0
T129	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882127	3920	0	0
T1	247770	0	0	0
T2	152180	7	0	0
T5	22172	0	0	0
T6	3970	7	0	0
T7	2880	0	0	0
T8	6724	0	0	0
T11	0	17	0	0
T18	3274	3	0	0
T19	93729	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	4	0	0
T24	2311	4	0	0
T25	5350	0	0	0
T38	0	3	0	0
T129	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Covered	T24,T18,T2
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426882127	3903	0	0
CgEnOn_A	426882127	3899	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882127	3903	0	0
T1	247770	0	0	0
T2	152180	6	0	0
T5	22172	0	0	0
T6	3970	7	0	0
T7	2880	0	0	0
T8	6724	0	0	0
T11	0	16	0	0
T18	3274	2	0	0
T19	93729	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	5	0	0
T24	2311	5	0	0
T25	5350	0	0	0
T38	0	3	0	0
T129	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882127	3899	0	0
T1	247770	0	0	0
T2	152180	6	0	0
T5	22172	0	0	0
T6	3970	7	0	0
T7	2880	0	0	0
T8	6724	0	0	0
T11	0	16	0	0
T18	3274	2	0	0
T19	93729	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	5	0	0
T24	2311	5	0	0
T25	5350	0	0	0
T38	0	3	0	0
T129	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Covered	T24,T18,T2
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426882127	3911	0	0
CgEnOn_A	426882127	3907	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882127	3911	0	0
T1	247770	0	0	0
T2	152180	7	0	0
T5	22172	0	0	0
T6	3970	7	0	0
T7	2880	0	0	0
T8	6724	0	0	0
T11	0	18	0	0
T18	3274	2	0	0
T19	93729	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	2	0	0
T24	2311	2	0	0
T25	5350	0	0	0
T38	0	3	0	0
T129	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882127	3907	0	0
T1	247770	0	0	0
T2	152180	7	0	0
T5	22172	0	0	0
T6	3970	7	0	0
T7	2880	0	0	0
T8	6724	0	0	0
T11	0	18	0	0
T18	3274	2	0	0
T19	93729	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	2	0	0
T24	2311	2	0	0
T25	5350	0	0	0
T38	0	3	0	0
T129	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Covered	T24,T18,T2
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426882127	3924	0	0
CgEnOn_A	426882127	3920	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882127	3924	0	0
T1	247770	0	0	0
T2	152180	9	0	0
T5	22172	0	0	0
T6	3970	7	0	0
T7	2880	0	0	0
T8	6724	0	0	0
T11	0	13	0	0
T18	3274	2	0	0
T19	93729	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	2	0	0
T24	2311	4	0	0
T25	5350	0	0	0
T38	0	3	0	0
T129	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426882127	3920	0	0
T1	247770	0	0	0
T2	152180	9	0	0
T5	22172	0	0	0
T6	3970	7	0	0
T7	2880	0	0	0
T8	6724	0	0	0
T11	0	13	0	0
T18	3274	2	0	0
T19	93729	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	2	0	0
T24	2311	4	0	0
T25	5350	0	0	0
T38	0	3	0	0
T129	0	5	0	0