Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T2
0	1	Covered	T7,T2,T155
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T20
1	0	Covered	T6,T38,T39
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	901115607	13880	0	0
GateOpen_A	901115607	13880	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	901115607	13880	0	0
T1	535145	0	0	0
T2	1914648	47	0	0
T5	57883	0	0	0
T6	8949	22	0	0
T7	6141	26	0	0
T8	15235	0	0	0
T11	0	101	0	0
T12	0	252	0	0
T18	7033	0	0	0
T19	172175	0	0	0
T20	0	4	0	0
T21	0	4	0	0
T24	4915	0	0	0
T25	11592	0	0	0
T38	0	11	0	0
T155	0	15	0	0
T172	0	12	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	901115607	13880	0	0
T1	535145	0	0	0
T2	1914648	47	0	0
T5	57883	0	0	0
T6	8949	22	0	0
T7	6141	26	0	0
T8	15235	0	0	0
T11	0	101	0	0
T12	0	252	0	0
T18	7033	0	0	0
T19	172175	0	0	0
T20	0	4	0	0
T21	0	4	0	0
T24	4915	0	0	0
T25	11592	0	0	0
T38	0	11	0	0
T155	0	15	0	0
T172	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T2
0	1	Covered	T7,T2,T155
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T20
1	0	Covered	T6,T38,T39
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	99238861	3447	0	0
GateOpen_A	99238861	3447	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99238861	3447	0	0
T1	59454	0	0	0
T2	349100	11	0	0
T5	6732	0	0	0
T6	984	6	0	0
T7	665	7	0	0
T8	1850	0	0	0
T11	0	27	0	0
T12	0	62	0	0
T18	773	0	0	0
T19	18162	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	529	0	0	0
T25	1295	0	0	0
T38	0	3	0	0
T155	0	4	0	0
T172	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99238861	3447	0	0
T1	59454	0	0	0
T2	349100	11	0	0
T5	6732	0	0	0
T6	984	6	0	0
T7	665	7	0	0
T8	1850	0	0	0
T11	0	27	0	0
T12	0	62	0	0
T18	773	0	0	0
T19	18162	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	529	0	0	0
T25	1295	0	0	0
T38	0	3	0	0
T155	0	4	0	0
T172	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T2
0	1	Covered	T7,T2,T155
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T20
1	0	Covered	T6,T38,T39
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	198478490	3446	0	0
GateOpen_A	198478490	3446	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198478490	3446	0	0
T1	118907	0	0	0
T2	698198	12	0	0
T5	13463	0	0	0
T6	1967	6	0	0
T7	1329	7	0	0
T8	3701	0	0	0
T11	0	23	0	0
T12	0	64	0	0
T18	1546	0	0	0
T19	36324	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	1057	0	0	0
T25	2591	0	0	0
T38	0	3	0	0
T155	0	3	0	0
T172	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198478490	3446	0	0
T1	118907	0	0	0
T2	698198	12	0	0
T5	13463	0	0	0
T6	1967	6	0	0
T7	1329	7	0	0
T8	3701	0	0	0
T11	0	23	0	0
T12	0	64	0	0
T18	1546	0	0	0
T19	36324	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	1057	0	0	0
T25	2591	0	0	0
T38	0	3	0	0
T155	0	3	0	0
T172	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T2
0	1	Covered	T7,T2,T155
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T20
1	0	Covered	T6,T38,T39
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	398701739	3505	0	0
GateOpen_A	398701739	3505	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398701739	3505	0	0
T1	237852	0	0	0
T2	139752	12	0	0
T5	27045	0	0	0
T6	3971	6	0	0
T7	2765	6	0	0
T8	6456	0	0	0
T11	0	26	0	0
T12	0	63	0	0
T18	3143	0	0	0
T19	72698	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	2219	0	0	0
T25	5137	0	0	0
T38	0	3	0	0
T155	0	4	0	0
T172	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398701739	3505	0	0
T1	237852	0	0	0
T2	139752	12	0	0
T5	27045	0	0	0
T6	3971	6	0	0
T7	2765	6	0	0
T8	6456	0	0	0
T11	0	26	0	0
T12	0	63	0	0
T18	3143	0	0	0
T19	72698	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	2219	0	0	0
T25	5137	0	0	0
T38	0	3	0	0
T155	0	4	0	0
T172	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T2
0	1	Covered	T7,T2,T155
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T20
1	0	Covered	T6,T38,T39
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	204696517	3482	0	0
GateOpen_A	204696517	3482	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204696517	3482	0	0
T1	118932	0	0	0
T2	727598	12	0	0
T5	10643	0	0	0
T6	2027	4	0	0
T7	1382	6	0	0
T8	3228	0	0	0
T11	0	25	0	0
T12	0	63	0	0
T18	1571	0	0	0
T19	44991	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	1110	0	0	0
T25	2569	0	0	0
T38	0	2	0	0
T155	0	4	0	0
T172	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204696517	3482	0	0
T1	118932	0	0	0
T2	727598	12	0	0
T5	10643	0	0	0
T6	2027	4	0	0
T7	1382	6	0	0
T8	3228	0	0	0
T11	0	25	0	0
T12	0	63	0	0
T18	1571	0	0	0
T19	44991	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	1110	0	0	0
T25	2569	0	0	0
T38	0	2	0	0
T155	0	4	0	0
T172	0	3	0	0