Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	616062	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3574632

1

T5

10

T4

114

T6

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1027896	1			T4	120		T22	100		T23	72
values[0x0]	1453297	1			T5	19		T4	49		T6	10
values[0x1]	1709501	1			T5	21		T4	66		T6	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	338359	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3852335

1

T5

10

T4

142

T6

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17263	1			T4	9		T22	2		T3	238
valid_sources[0x01]	15479	1			T2	2		T3	206		T28	1
valid_sources[0x02]	18071	1			T2	1		T3	223		T29	4
valid_sources[0x03]	16095	1			T2	12		T3	229		T28	1
valid_sources[0x04]	15481	1			T4	3		T2	1		T110	1
valid_sources[0x05]	16176	1			T2	1		T17	1		T110	3
valid_sources[0x06]	17061	1			T5	1		T23	3		T2	2
valid_sources[0x07]	16492	1			T5	2		T2	1		T3	212
valid_sources[0x08]	16564	1			T2	1		T17	1		T27	1
valid_sources[0x09]	16050	1			T4	3		T2	1		T3	181
valid_sources[0x0a]	17370	1			T5	1		T2	6		T3	183
valid_sources[0x0b]	16590	1			T2	8		T110	2		T3	205
valid_sources[0x0c]	15671	1			T2	2		T3	223		T68	1
valid_sources[0x0d]	17138	1			T5	2		T4	14		T1	1
valid_sources[0x0e]	17616	1			T2	8		T17	1		T3	199
valid_sources[0x0f]	15889	1			T4	3		T1	3		T2	4
valid_sources[0x10]	15727	1			T4	10		T2	4		T110	1
valid_sources[0x11]	14595	1			T23	1		T2	3		T3	206
valid_sources[0x12]	16739	1			T2	11		T110	1		T109	1
valid_sources[0x13]	15896	1			T2	4		T17	1		T3	214
valid_sources[0x14]	18408	1			T4	5		T2	4		T17	1
valid_sources[0x15]	16200	1			T22	3		T2	6		T20	13
valid_sources[0x16]	17750	1			T5	1		T6	1		T2	1
valid_sources[0x17]	17473	1			T4	3		T2	8		T21	1
valid_sources[0x18]	17871	1			T2	4		T3	195		T68	1
valid_sources[0x19]	17749	1			T6	1		T2	5		T73	5
valid_sources[0x1a]	15670	1			T5	2		T23	3		T2	4
valid_sources[0x1b]	15305	1			T2	2		T3	214		T28	2
valid_sources[0x1c]	16027	1			T2	1		T3	237		T68	1
valid_sources[0x1d]	16733	1			T5	1		T23	4		T2	2
valid_sources[0x1e]	14919	1			T15	23		T3	222		T29	5
valid_sources[0x1f]	16112	1			T2	3		T3	246		T29	8
valid_sources[0x20]	15297	1			T4	6		T2	8		T3	204
valid_sources[0x21]	17534	1			T1	2		T2	5		T3	240
valid_sources[0x22]	16778	1			T17	2		T110	1		T3	266
valid_sources[0x23]	15763	1			T2	3		T17	1		T3	191
valid_sources[0x24]	16590	1			T1	16		T2	3		T17	1
valid_sources[0x25]	15239	1			T6	1		T2	3		T110	2
valid_sources[0x26]	15873	1			T1	2		T3	247		T28	2
valid_sources[0x27]	17197	1			T2	2		T3	271		T67	1
valid_sources[0x28]	16226	1			T110	3		T3	209		T113	8
valid_sources[0x29]	15705	1			T5	1		T17	1		T73	3
valid_sources[0x2a]	18083	1			T17	1		T3	227		T28	2
valid_sources[0x2b]	16910	1			T1	1		T2	5		T27	2
valid_sources[0x2c]	17959	1			T2	6		T27	1		T110	3
valid_sources[0x2d]	18066	1			T4	2		T2	2		T17	1
valid_sources[0x2e]	17091	1			T23	2		T1	3		T2	7
valid_sources[0x2f]	16267	1			T2	5		T17	1		T19	81
valid_sources[0x30]	16535	1			T2	5		T3	212		T68	2
valid_sources[0x31]	17833	1			T4	9		T6	1		T3	290
valid_sources[0x32]	14297	1			T22	6		T2	3		T110	1
valid_sources[0x33]	16580	1			T2	4		T110	1		T3	194
valid_sources[0x34]	15551	1			T22	2		T1	11		T2	1
valid_sources[0x35]	16565	1			T6	1		T2	4		T110	1
valid_sources[0x36]	15788	1			T4	7		T2	4		T17	1
valid_sources[0x37]	15698	1			T110	1		T3	211		T29	2
valid_sources[0x38]	16778	1			T2	2		T17	1		T3	221
valid_sources[0x39]	17292	1			T1	3		T2	6		T73	2
valid_sources[0x3a]	16884	1			T6	1		T2	6		T17	1
valid_sources[0x3b]	15183	1			T5	1		T23	7		T2	1
valid_sources[0x3c]	16354	1			T109	1		T3	191		T28	1
valid_sources[0x3d]	16228	1			T5	1		T4	1		T22	1
valid_sources[0x3e]	16940	1			T2	11		T3	209		T7	7
valid_sources[0x3f]	16852	1			T2	2		T109	1		T3	221
valid_sources[0x40]	16783	1			T2	4		T3	195		T28	1
valid_sources[0x41]	15719	1			T1	10		T2	8		T17	1
valid_sources[0x42]	15737	1			T22	3		T2	2		T3	228
valid_sources[0x43]	15580	1			T5	1		T4	9		T110	1
valid_sources[0x44]	15572	1			T4	2		T1	1		T2	6
valid_sources[0x45]	15976	1			T5	2		T4	1		T22	6
valid_sources[0x46]	16064	1			T5	1		T4	1		T2	5
valid_sources[0x47]	16524	1			T3	238		T67	1		T28	4
valid_sources[0x48]	15665	1			T2	3		T17	1		T110	1
valid_sources[0x49]	17175	1			T6	1		T2	3		T3	198
valid_sources[0x4a]	16956	1			T2	1		T27	1		T110	1
valid_sources[0x4b]	16516	1			T6	1		T1	2		T2	1
valid_sources[0x4c]	16942	1			T23	4		T109	3		T3	239
valid_sources[0x4d]	17691	1			T5	1		T4	1		T3	221
valid_sources[0x4e]	16646	1			T22	6		T2	7		T3	217
valid_sources[0x4f]	16674	1			T4	9		T6	1		T2	7
valid_sources[0x50]	18258	1			T3	224		T28	1		T29	4
valid_sources[0x51]	15254	1			T6	1		T110	1		T3	219
valid_sources[0x52]	17608	1			T4	1		T2	4		T110	2
valid_sources[0x53]	15604	1			T3	207		T29	1		T7	7
valid_sources[0x54]	15138	1			T15	23		T21	7		T110	1
valid_sources[0x55]	16130	1			T2	1		T27	2		T3	204
valid_sources[0x56]	16294	1			T5	2		T2	2		T109	1
valid_sources[0x57]	16765	1			T22	9		T2	2		T21	1
valid_sources[0x58]	17412	1			T1	2		T2	2		T27	2
valid_sources[0x59]	15503	1			T2	4		T110	1		T3	221
valid_sources[0x5a]	15685	1			T2	2		T17	1		T27	1
valid_sources[0x5b]	15037	1			T1	1		T27	1		T3	207
valid_sources[0x5c]	16146	1			T5	1		T2	1		T17	1
valid_sources[0x5d]	15284	1			T6	2		T2	2		T3	234
valid_sources[0x5e]	17293	1			T17	2		T73	1		T3	218
valid_sources[0x5f]	18631	1			T2	14		T21	1		T3	222
valid_sources[0x60]	15297	1			T4	1		T2	6		T110	2
valid_sources[0x61]	17034	1			T2	2		T3	222		T28	4
valid_sources[0x62]	16817	1			T5	1		T2	1		T27	1
valid_sources[0x63]	16164	1			T4	1		T2	5		T3	228
valid_sources[0x64]	16440	1			T4	11		T1	4		T2	6
valid_sources[0x65]	16044	1			T5	1		T2	12		T3	204
valid_sources[0x66]	17750	1			T3	203		T68	1		T28	1
valid_sources[0x67]	15228	1			T4	18		T3	219		T29	1
valid_sources[0x68]	16423	1			T2	3		T17	1		T110	1
valid_sources[0x69]	15918	1			T23	3		T2	9		T21	1
valid_sources[0x6a]	16923	1			T17	2		T110	1		T3	196
valid_sources[0x6b]	16832	1			T1	2		T2	1		T73	1
valid_sources[0x6c]	15644	1			T2	3		T109	1		T3	222
valid_sources[0x6d]	15856	1			T4	5		T2	2		T109	2
valid_sources[0x6e]	16764	1			T2	19		T110	1		T3	177
valid_sources[0x6f]	15432	1			T4	2		T2	3		T110	1
valid_sources[0x70]	16324	1			T6	1		T2	2		T3	209
valid_sources[0x71]	15291	1			T23	31		T17	1		T110	3
valid_sources[0x72]	16100	1			T2	6		T27	1		T3	229
valid_sources[0x73]	16357	1			T4	3		T2	1		T109	1
valid_sources[0x74]	15579	1			T2	2		T110	1		T3	252
valid_sources[0x75]	15716	1			T2	1		T110	2		T3	189
valid_sources[0x76]	14596	1			T2	4		T3	214		T68	1
valid_sources[0x77]	16154	1			T2	7		T3	186		T29	1
valid_sources[0x78]	17000	1			T2	6		T17	1		T110	2
valid_sources[0x79]	15884	1			T110	3		T3	227		T29	6
valid_sources[0x7a]	15725	1			T2	11		T3	223		T68	1
valid_sources[0x7b]	16574	1			T2	1		T17	1		T110	1
valid_sources[0x7c]	16708	1			T2	4		T3	195		T67	1
valid_sources[0x7d]	17260	1			T2	10		T3	164		T68	1
valid_sources[0x7e]	17311	1			T2	5		T3	223		T68	2
valid_sources[0x7f]	15363	1			T2	3		T27	1		T3	212
valid_sources[0x80]	17356	1			T2	2		T109	1		T3	230

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

901137

1

T4

67

T23

39

T1

10

values[0x0]

all_enables

biggest_size

1360051

1

T5

7

T4

28

T6

3

values[0x1]

all_enables

biggest_size

1313444

1

T5

3

T4

19

T6

1