Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	744282795	71889	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744282795	71889	0	0
T1	106110	77	0	0
T2	478880	42	0	0
T3	0	783	0	0
T7	0	457	0	0
T8	0	50	0	0
T9	0	1071	0	0
T10	0	475	0	0
T11	0	495	0	0
T12	0	183	0	0
T13	0	138	0	0
T14	8385	0	0	0
T15	7170	0	0	0
T16	6420	0	0	0
T17	10545	0	0	0
T18	6000	0	0	0
T19	10575	0	0	0
T20	2730	0	0	0
T21	8620	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	148856559	10591	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148856559	10591	0	0
T1	21222	11	0	0
T2	95776	7	0	0
T3	0	127	0	0
T7	0	64	0	0
T8	0	8	0	0
T9	0	170	0	0
T10	0	63	0	0
T11	0	81	0	0
T12	0	27	0	0
T13	0	26	0	0
T14	1677	0	0	0
T15	1434	0	0	0
T16	1284	0	0	0
T17	2109	0	0	0
T18	1200	0	0	0
T19	2115	0	0	0
T20	546	0	0	0
T21	1724	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	148856559	14525	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148856559	14525	0	0
T1	21222	15	0	0
T2	95776	8	0	0
T3	0	159	0	0
T7	0	89	0	0
T8	0	10	0	0
T9	0	218	0	0
T10	0	96	0	0
T11	0	100	0	0
T12	0	37	0	0
T13	0	26	0	0
T14	1677	0	0	0
T15	1434	0	0	0
T16	1284	0	0	0
T17	2109	0	0	0
T18	1200	0	0	0
T19	2115	0	0	0
T20	546	0	0	0
T21	1724	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	148856559	22038	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148856559	22038	0	0
T1	21222	23	0	0
T2	95776	11	0	0
T3	0	216	0	0
T7	0	137	0	0
T8	0	14	0	0
T9	0	299	0	0
T10	0	157	0	0
T11	0	134	0	0
T12	0	56	0	0
T13	0	34	0	0
T14	1677	0	0	0
T15	1434	0	0	0
T16	1284	0	0	0
T17	2109	0	0	0
T18	1200	0	0	0
T19	2115	0	0	0
T20	546	0	0	0
T21	1724	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	148856559	10281	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148856559	10281	0	0
T1	21222	11	0	0
T2	95776	7	0	0
T3	0	122	0	0
T7	0	64	0	0
T8	0	8	0	0
T9	0	166	0	0
T10	0	61	0	0
T11	0	80	0	0
T12	0	26	0	0
T13	0	26	0	0
T14	1677	0	0	0
T15	1434	0	0	0
T16	1284	0	0	0
T17	2109	0	0	0
T18	1200	0	0	0
T19	2115	0	0	0
T20	546	0	0	0
T21	1724	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	148856559	14454	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148856559	14454	0	0
T1	21222	17	0	0
T2	95776	9	0	0
T3	0	159	0	0
T7	0	103	0	0
T8	0	10	0	0
T9	0	218	0	0
T10	0	98	0	0
T11	0	100	0	0
T12	0	37	0	0
T13	0	26	0	0
T14	1677	0	0	0
T15	1434	0	0	0
T16	1284	0	0	0
T17	2109	0	0	0
T18	1200	0	0	0
T19	2115	0	0	0
T20	546	0	0	0
T21	1724	0	0	0