Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T4,T6
0	1	Unreachable
1	0	Covered	T4,T22,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	148856559	146381120	0	0
AllClkBypReqTrue_A	148856559	122155	0	0
IoClkBypReqFalse_A	148856559	146301137	0	2415
IoClkBypReqTrue_A	148856559	197618	0	0
LcClkBypAckFalse_A	148856559	146389265	0	0
LcClkBypAckTrue_A	148856559	114010	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148856559	146381120	0	0
T1	21222	21092	0	0
T2	95776	95725	0	0
T4	6069	1229	0	0
T5	2027	1966	0	0
T6	1262	1199	0	0
T14	1677	1454	0	0
T15	1434	1263	0	0
T16	1284	1184	0	0
T22	11380	9966	0	0
T23	3326	3304	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148856559	122155	0	0
T3	0	923	0	0
T15	1434	152	0	0
T16	1284	0	0	0
T17	2109	0	0	0
T18	1200	104	0	0
T19	2115	0	0	0
T20	546	0	0	0
T21	1724	0	0	0
T27	1289	55	0	0
T67	0	197	0	0
T70	0	370	0	0
T71	0	238	0	0
T72	0	281	0	0
T73	1828	168	0	0
T109	0	244	0	0
T110	3141	0	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148856559	146301137	0	2415
T1	21222	21090	0	3
T2	95776	95721	0	3
T4	6069	1217	0	3
T5	2027	1964	0	3
T6	1262	1197	0	3
T14	1677	1452	0	3
T15	1434	1307	0	3
T16	1284	1182	0	3
T22	11380	9764	0	3
T23	3326	3302	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148856559	197618	0	0
T3	0	1130	0	0
T15	1434	106	0	0
T16	1284	0	0	0
T17	2109	0	0	0
T18	1200	156	0	0
T19	2115	0	0	0
T20	546	0	0	0
T21	1724	220	0	0
T27	1289	236	0	0
T67	0	310	0	0
T70	0	512	0	0
T71	0	448	0	0
T73	1828	146	0	0
T109	0	344	0	0
T110	3141	0	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148856559	146389265	0	0
T1	21222	21092	0	0
T2	95776	95725	0	0
T4	6069	1229	0	0
T5	2027	1966	0	0
T6	1262	1199	0	0
T14	1677	1454	0	0
T15	1434	1318	0	0
T16	1284	1184	0	0
T22	11380	9966	0	0
T23	3326	3304	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148856559	114010	0	0
T3	0	567	0	0
T15	1434	97	0	0
T16	1284	0	0	0
T17	2109	0	0	0
T18	1200	137	0	0
T19	2115	0	0	0
T20	546	0	0	0
T21	1724	70	0	0
T27	1289	97	0	0
T67	0	175	0	0
T70	0	213	0	0
T71	0	299	0	0
T73	1828	119	0	0
T109	0	164	0	0
T110	3141	0	0	0