Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1707373380	15235	0	0
TransStop_A	1707373380	7582	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1707373380	15235	0	0
T1	176848	0	0	0
T2	1800308	10	0	0
T3	0	120	0	0
T14	6500	0	0	0
T15	57388	0	0	0
T16	10940	0	0	0
T17	8440	4	0	0
T18	19220	0	0	0
T19	14108	4	0	0
T20	27332	0	0	0
T23	95060	39	0	0
T68	0	4	0	0
T110	0	27	0	0
T111	0	27	0	0
T112	0	4	0	0
T113	0	4	0	0
T114	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1707373380	7582	0	0
T1	176848	0	0	0
T2	1800308	7	0	0
T3	0	71	0	0
T7	0	9	0	0
T14	6500	0	0	0
T15	57388	0	0	0
T16	10940	0	0	0
T17	8440	4	0	0
T18	19220	0	0	0
T19	14108	4	0	0
T20	27332	0	0	0
T23	95060	24	0	0
T68	0	4	0	0
T110	0	8	0	0
T111	0	12	0	0
T112	0	4	0	0
T113	0	4	0	0
T114	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	426843345	3820	0	0
TransStop_A	426843345	1892	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426843345	3820	0	0
T1	44212	0	0	0
T2	450077	4	0	0
T3	0	32	0	0
T14	1625	0	0	0
T15	14347	0	0	0
T16	2735	0	0	0
T17	2110	1	0	0
T18	4805	0	0	0
T19	3527	1	0	0
T20	6833	0	0	0
T23	23765	9	0	0
T68	0	1	0	0
T110	0	9	0	0
T111	0	5	0	0
T112	0	1	0	0
T113	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426843345	1892	0	0
T1	44212	0	0	0
T2	450077	3	0	0
T3	0	18	0	0
T14	1625	0	0	0
T15	14347	0	0	0
T16	2735	0	0	0
T17	2110	1	0	0
T18	4805	0	0	0
T19	3527	1	0	0
T20	6833	0	0	0
T23	23765	3	0	0
T68	0	1	0	0
T110	0	2	0	0
T111	0	2	0	0
T112	0	1	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	426843345	3808	0	0
TransStop_A	426843345	1884	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426843345	3808	0	0
T1	44212	0	0	0
T2	450077	3	0	0
T3	0	33	0	0
T14	1625	0	0	0
T15	14347	0	0	0
T16	2735	0	0	0
T17	2110	1	0	0
T18	4805	0	0	0
T19	3527	1	0	0
T20	6833	0	0	0
T23	23765	11	0	0
T68	0	1	0	0
T110	0	5	0	0
T111	0	8	0	0
T112	0	2	0	0
T113	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426843345	1884	0	0
T1	44212	0	0	0
T2	450077	2	0	0
T3	0	19	0	0
T14	1625	0	0	0
T15	14347	0	0	0
T16	2735	0	0	0
T17	2110	1	0	0
T18	4805	0	0	0
T19	3527	1	0	0
T20	6833	0	0	0
T23	23765	8	0	0
T68	0	1	0	0
T110	0	3	0	0
T111	0	4	0	0
T112	0	2	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	426843345	3805	0	0
TransStop_A	426843345	1910	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426843345	3805	0	0
T1	44212	0	0	0
T2	450077	2	0	0
T3	0	27	0	0
T14	1625	0	0	0
T15	14347	0	0	0
T16	2735	0	0	0
T17	2110	1	0	0
T18	4805	0	0	0
T19	3527	1	0	0
T20	6833	0	0	0
T23	23765	11	0	0
T68	0	1	0	0
T110	0	7	0	0
T111	0	8	0	0
T112	0	1	0	0
T113	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426843345	1910	0	0
T1	44212	0	0	0
T2	450077	2	0	0
T3	0	18	0	0
T14	1625	0	0	0
T15	14347	0	0	0
T16	2735	0	0	0
T17	2110	1	0	0
T18	4805	0	0	0
T19	3527	1	0	0
T20	6833	0	0	0
T23	23765	6	0	0
T68	0	1	0	0
T110	0	2	0	0
T111	0	3	0	0
T112	0	1	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	426843345	3802	0	0
TransStop_A	426843345	1896	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426843345	3802	0	0
T1	44212	0	0	0
T2	450077	1	0	0
T3	0	28	0	0
T14	1625	0	0	0
T15	14347	0	0	0
T16	2735	0	0	0
T17	2110	1	0	0
T18	4805	0	0	0
T19	3527	1	0	0
T20	6833	0	0	0
T23	23765	8	0	0
T68	0	1	0	0
T110	0	6	0	0
T111	0	6	0	0
T113	0	1	0	0
T114	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426843345	1896	0	0
T1	44212	0	0	0
T2	450077	0	0	0
T3	0	16	0	0
T7	0	9	0	0
T14	1625	0	0	0
T15	14347	0	0	0
T16	2735	0	0	0
T17	2110	1	0	0
T18	4805	0	0	0
T19	3527	1	0	0
T20	6833	0	0	0
T23	23765	7	0	0
T68	0	1	0	0
T110	0	1	0	0
T111	0	3	0	0
T113	0	1	0	0
T114	0	3	0	0