Unified Coverage Report :: Module :: prim_clock_timeout

Module : prim_clock_timeout

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	100.00			75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk	100.00	100.00	100.00			100.00
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk	100.00	100.00	100.00			100.00
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk	100.00	100.00	100.00			100.00
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk	100.00	100.00	100.00			100.00
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_out	100.00	100.00				100.00
u_ref_timeout	87.50	100.00	100.00			100.00	50.00

---

Module Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_out	100.00	100.00				100.00
u_ref_timeout	87.50	100.00	100.00			100.00	50.00

---

Module Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_out	100.00	100.00				100.00
u_ref_timeout	87.50	100.00	100.00			100.00	50.00

---

Module Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_out	100.00	100.00				100.00
u_ref_timeout	87.50	100.00	100.00			100.00	50.00

---

Module Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_out	100.00	100.00				100.00
u_ref_timeout	87.50	100.00	100.00			100.00	50.00

Line Coverage for Module : prim_clock_timeout

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30		unreachable
32	1	1
33	1	1
34	1	1
35	1	1
36	1	1
37		unreachable
38	1	1
39	1	1
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_clock_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T4,T6
1	0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_clock_timeout

	Line No.	Total	Covered	Percent
Branches		4	3	75.00
IF	32	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if ((ack || (!en_i)))
-3-:	36	if (timeout)
-4-:	38	if (en_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T5,T4,T6
0	1	-	-	Covered	T5,T4,T6
0	0	1	-	Unreachable	T2,T3,T28
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30		unreachable
32	1	1
33	1	1
34	1	1
35	1	1
36	1	1
37		unreachable
38	1	1
39	1	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T4,T6
1	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if ((ack || (!en_i)))
-3-:	36	if (timeout)
-4-:	38	if (en_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T5,T4,T6
0	1	-	-	Covered	T5,T4,T6
0	0	1	-	Unreachable	T2,T3,T28
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30		unreachable
32	1	1
33	1	1
34	1	1
35	1	1
36	1	1
37		unreachable
38	1	1
39	1	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T4,T6
1	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if ((ack || (!en_i)))
-3-:	36	if (timeout)
-4-:	38	if (en_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T5,T4,T6
0	1	-	-	Covered	T5,T4,T6
0	0	1	-	Unreachable	T2,T3,T28
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30		unreachable
32	1	1
33	1	1
34	1	1
35	1	1
36	1	1
37		unreachable
38	1	1
39	1	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T4,T6
1	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if ((ack || (!en_i)))
-3-:	36	if (timeout)
-4-:	38	if (en_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T5,T4,T6
0	1	-	-	Covered	T5,T4,T6
0	0	1	-	Unreachable	T2,T3,T28
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30		unreachable
32	1	1
33	1	1
34	1	1
35	1	1
36	1	1
37		unreachable
38	1	1
39	1	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T4,T6
1	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if ((ack || (!en_i)))
-3-:	36	if (timeout)
-4-:	38	if (en_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T5,T4,T6
0	1	-	-	Covered	T5,T4,T6
0	0	1	-	Unreachable	T2,T3,T28
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30		unreachable
32	1	1
33	1	1
34	1	1
35	1	1
36	1	1
37		unreachable
38	1	1
39	1	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T4,T6
1	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if ((ack || (!en_i)))
-3-:	36	if (timeout)
-4-:	38	if (en_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T5,T4,T6
0	1	-	-	Covered	T5,T4,T6
0	0	1	-	Unreachable	T2,T3,T28
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Excluded		VC_COV_UNR