Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	149738243	5198354	0	0
clk_enables_rd_A	149738243	29263	0	0
clk_hints_rd_A	149738243	26732	0	0
extclk_ctrl_rd_A	149738243	34586	0	0
extclk_ctrl_regwen_rd_A	149738243	25010	0	0
jitter_enable_rd_A	149738243	40527	0	0
jitter_regwen_rd_A	149738243	28535	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149738243	5198354	0	0
T3	223972	78877	0	0
T9	0	171098	0	0
T28	108090	0	0	0
T31	1959	0	0	0
T33	0	129166	0	0
T35	1501	0	0	0
T37	0	197836	0	0
T61	0	65086	0	0
T62	0	35310	0	0
T63	0	102647	0	0
T64	0	99715	0	0
T65	0	202024	0	0
T66	0	56043	0	0
T67	1991	0	0	0
T68	2072	0	0	0
T69	980	0	0	0
T70	2573	0	0	0
T71	2112	0	0	0
T72	1407	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149738243	29263	0	0
T3	223972	0	0	0
T7	0	11	0	0
T17	2109	4	0	0
T18	1200	0	0	0
T19	2115	5	0	0
T20	546	0	0	0
T21	1724	0	0	0
T27	1289	0	0	0
T61	0	1529	0	0
T62	0	619	0	0
T66	0	1152	0	0
T68	0	1	0	0
T73	1828	0	0	0
T109	2237	0	0	0
T110	3141	0	0	0
T132	0	8	0	0
T133	0	12	0	0
T134	0	4977	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149738243	26732	0	0
T3	223972	0	0	0
T7	0	6	0	0
T11	0	6	0	0
T19	2115	1	0	0
T20	546	0	0	0
T21	1724	0	0	0
T27	1289	0	0	0
T61	0	1247	0	0
T62	0	687	0	0
T66	0	956	0	0
T67	1991	0	0	0
T68	2072	4	0	0
T73	1828	0	0	0
T109	2237	0	0	0
T110	3141	0	0	0
T132	0	2	0	0
T133	0	12	0	0
T134	0	4421	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149738243	34586	0	0
T3	223972	0	0	0
T7	0	51	0	0
T11	0	31	0	0
T35	1501	0	0	0
T67	1991	0	0	0
T68	2072	0	0	0
T69	980	2	0	0
T70	2573	70	0	0
T71	2112	16	0	0
T72	0	19	0	0
T73	1828	24	0	0
T74	0	15	0	0
T85	0	59	0	0
T109	2237	0	0	0
T110	3141	0	0	0
T135	0	21	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149738243	25010	0	0
T61	212949	1291	0	0
T62	0	684	0	0
T66	0	934	0	0
T91	2499	0	0	0
T134	0	4021	0	0
T136	0	44	0	0
T137	0	8	0	0
T138	0	25	0	0
T139	0	37	0	0
T140	0	25	0	0
T141	0	262	0	0
T142	1143	0	0	0
T143	978	0	0	0
T144	1217	0	0	0
T145	2978	0	0	0
T146	1700	0	0	0
T147	16068	0	0	0
T148	2917	0	0	0
T149	609325	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149738243	40527	0	0
T3	223972	0	0	0
T7	0	343	0	0
T11	0	377	0	0
T17	2109	99	0	0
T18	1200	0	0	0
T19	2115	108	0	0
T20	546	0	0	0
T21	1724	0	0	0
T27	1289	0	0	0
T61	0	2044	0	0
T68	0	31	0	0
T73	1828	0	0	0
T109	2237	0	0	0
T110	3141	0	0	0
T132	0	117	0	0
T133	0	462	0	0
T146	0	61	0	0
T150	0	102	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149738243	28535	0	0
T61	212949	1300	0	0
T62	0	750	0	0
T66	0	1220	0	0
T91	2499	0	0	0
T134	0	4932	0	0
T141	0	260	0	0
T142	1143	0	0	0
T143	978	0	0	0
T144	1217	0	0	0
T145	2978	0	0	0
T146	1700	0	0	0
T147	16068	0	0	0
T148	2917	0	0	0
T149	609325	0	0	0
T151	0	1119	0	0
T152	0	3499	0	0
T153	0	1507	0	0
T154	0	2766	0	0
T155	0	2255	0	0