Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T2
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48659	0	0
CgEnOn_A	2147483647	39627	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48659	0	0
T1	272247	3	0	0
T2	2687421	10	0	0
T4	57236	18	0	0
T5	17440	3	0	0
T6	5440	3	0	0
T9	0	5	0	0
T14	16566	45	0	0
T15	151460	3	0	0
T16	27974	41	0	0
T17	17145	1	0	0
T18	39929	0	0	0
T19	28647	1	0	0
T20	55651	0	0	0
T21	7810	0	0	0
T22	301066	303	0	0
T23	146331	12	0	0
T27	22926	0	0	0
T35	0	17	0	0
T36	0	15	0	0
T37	0	5	0	0
T73	7834	0	0	0
T156	0	15	0	0
T157	0	15	0	0
T158	0	15	0	0
T159	0	10	0	0
T160	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39627	0	0
T1	176844	0	0	0
T2	1800304	4	0	0
T3	0	175	0	0
T7	0	12	0	0
T9	0	4	0	0
T14	16566	42	0	0
T15	151460	0	0	0
T16	27974	38	0	0
T17	21662	3	0	0
T18	50744	0	0	0
T19	36185	4	0	0
T20	70349	14	0	0
T21	11868	0	0	0
T23	95060	9	0	0
T27	34877	0	0	0
T35	0	26	0	0
T36	0	24	0	0
T37	0	5	0	0
T68	0	2	0	0
T73	11914	0	0	0
T113	0	2	0	0
T142	0	1	0	0
T156	0	21	0	0
T157	0	18	0	0
T158	0	15	0	0
T159	0	10	0	0
T160	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T2
1	0	Unreachable
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	198552031	147	0	0
CgEnOn_A	198552031	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198552031	147	0	0
T9	0	1	0	0
T14	736	5	0	0
T15	7738	0	0	0
T16	1252	0	0	0
T17	987	0	0	0
T18	2599	0	0	0
T19	1639	0	0	0
T20	3240	0	0	0
T21	906	0	0	0
T27	2810	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T73	949	0	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198552031	147	0	0
T9	0	1	0	0
T14	736	5	0	0
T15	7738	0	0	0
T16	1252	0	0	0
T17	987	0	0	0
T18	2599	0	0	0
T19	1639	0	0	0
T20	3240	0	0	0
T21	906	0	0	0
T27	2810	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T73	949	0	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T2
1	0	Unreachable
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99275417	147	0	0
CgEnOn_A	99275417	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99275417	147	0	0
T9	0	1	0	0
T14	368	5	0	0
T15	3868	0	0	0
T16	626	0	0	0
T17	493	0	0	0
T18	1298	0	0	0
T19	820	0	0	0
T20	1620	0	0	0
T21	452	0	0	0
T27	1404	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T73	474	0	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99275417	147	0	0
T9	0	1	0	0
T14	368	5	0	0
T15	3868	0	0	0
T16	626	0	0	0
T17	493	0	0	0
T18	1298	0	0	0
T19	820	0	0	0
T20	1620	0	0	0
T21	452	0	0	0
T27	1404	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T73	474	0	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T2
1	0	Unreachable
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	398669474	147	0	0
CgEnOn_A	398669474	140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398669474	147	0	0
T9	0	1	0	0
T14	1565	5	0	0
T15	13772	0	0	0
T16	2625	0	0	0
T17	2025	0	0	0
T18	4612	0	0	0
T19	3386	0	0	0
T20	6559	0	0	0
T21	1800	0	0	0
T27	5158	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T73	1771	0	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398669474	140	0	0
T14	1565	5	0	0
T15	13772	0	0	0
T16	2625	0	0	0
T17	2025	0	0	0
T18	4612	0	0	0
T19	3386	0	0	0
T20	6559	0	0	0
T21	1800	0	0	0
T27	5158	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T73	1771	0	0	0
T142	0	1	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T2
1	0	Unreachable
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426842906	136	0	0
CgEnOn_A	426842906	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426842906	136	0	0
T14	1624	2	0	0
T15	14347	0	0	0
T16	2734	0	0	0
T17	2109	0	0	0
T18	4804	0	0	0
T19	3527	0	0	0
T20	6832	0	0	0
T21	1874	0	0	0
T27	5373	0	0	0
T35	0	2	0	0
T36	0	3	0	0
T73	1846	0	0	0
T142	0	1	0	0
T156	0	3	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426842906	135	0	0
T14	1624	2	0	0
T15	14347	0	0	0
T16	2734	0	0	0
T17	2109	0	0	0
T18	4804	0	0	0
T19	3527	0	0	0
T20	6832	0	0	0
T21	1874	0	0	0
T27	5373	0	0	0
T35	0	2	0	0
T36	0	3	0	0
T73	1846	0	0	0
T142	0	1	0	0
T156	0	3	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T2
1	0	Unreachable
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99275417	147	0	0
CgEnOn_A	99275417	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99275417	147	0	0
T9	0	1	0	0
T14	368	5	0	0
T15	3868	0	0	0
T16	626	0	0	0
T17	493	0	0	0
T18	1298	0	0	0
T19	820	0	0	0
T20	1620	0	0	0
T21	452	0	0	0
T27	1404	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T73	474	0	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99275417	147	0	0
T9	0	1	0	0
T14	368	5	0	0
T15	3868	0	0	0
T16	626	0	0	0
T17	493	0	0	0
T18	1298	0	0	0
T19	820	0	0	0
T20	1620	0	0	0
T21	452	0	0	0
T27	1404	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T73	474	0	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T2
1	0	Unreachable
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426842906	136	0	0
CgEnOn_A	426842906	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426842906	136	0	0
T14	1624	2	0	0
T15	14347	0	0	0
T16	2734	0	0	0
T17	2109	0	0	0
T18	4804	0	0	0
T19	3527	0	0	0
T20	6832	0	0	0
T21	1874	0	0	0
T27	5373	0	0	0
T35	0	2	0	0
T36	0	3	0	0
T73	1846	0	0	0
T142	0	1	0	0
T156	0	3	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426842906	135	0	0
T14	1624	2	0	0
T15	14347	0	0	0
T16	2734	0	0	0
T17	2109	0	0	0
T18	4804	0	0	0
T19	3527	0	0	0
T20	6832	0	0	0
T21	1874	0	0	0
T27	5373	0	0	0
T35	0	2	0	0
T36	0	3	0	0
T73	1846	0	0	0
T142	0	1	0	0
T156	0	3	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T2
1	0	Unreachable
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99275417	147	0	0
CgEnOn_A	99275417	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99275417	147	0	0
T9	0	1	0	0
T14	368	5	0	0
T15	3868	0	0	0
T16	626	0	0	0
T17	493	0	0	0
T18	1298	0	0	0
T19	820	0	0	0
T20	1620	0	0	0
T21	452	0	0	0
T27	1404	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T73	474	0	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99275417	147	0	0
T9	0	1	0	0
T14	368	5	0	0
T15	3868	0	0	0
T16	626	0	0	0
T17	493	0	0	0
T18	1298	0	0	0
T19	820	0	0	0
T20	1620	0	0	0
T21	452	0	0	0
T27	1404	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T73	474	0	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T35,T36
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	198552031	7975	0	0
CgEnOn_A	198552031	5724	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198552031	7975	0	0
T1	21160	1	0	0
T2	195824	2	0	0
T4	9022	6	0	0
T5	3840	1	0	0
T6	1201	1	0	0
T14	736	6	0	0
T15	7738	1	0	0
T16	1252	15	0	0
T22	64144	101	0	0
T23	11367	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198552031	5724	0	0
T3	0	48	0	0
T14	736	5	0	0
T15	7738	0	0	0
T16	1252	14	0	0
T17	987	1	0	0
T18	2599	0	0	0
T19	1639	1	0	0
T20	3240	4	0	0
T21	906	0	0	0
T27	2810	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T73	949	0	0	0
T113	0	1	0	0
T156	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T35,T36
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99275417	7933	0	0
CgEnOn_A	99275417	5682	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99275417	7933	0	0
T1	10580	1	0	0
T2	97912	2	0	0
T4	4512	6	0	0
T5	1920	1	0	0
T6	600	1	0	0
T14	368	6	0	0
T15	3868	1	0	0
T16	626	13	0	0
T22	32068	101	0	0
T23	5684	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99275417	5682	0	0
T3	0	48	0	0
T7	0	12	0	0
T14	368	5	0	0
T15	3868	0	0	0
T16	626	12	0	0
T17	493	0	0	0
T18	1298	0	0	0
T19	820	1	0	0
T20	1620	5	0	0
T21	452	0	0	0
T27	1404	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T73	474	0	0	0
T156	0	3	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T35,T36
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	398669474	8012	0	0
CgEnOn_A	398669474	5754	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398669474	8012	0	0
T1	42441	1	0	0
T2	391741	2	0	0
T4	29134	6	0	0
T5	7787	1	0	0
T6	2426	1	0	0
T14	1565	6	0	0
T15	13772	1	0	0
T16	2625	13	0	0
T22	136568	101	0	0
T23	22813	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398669474	5754	0	0
T3	0	47	0	0
T14	1565	5	0	0
T15	13772	0	0	0
T16	2625	12	0	0
T17	2025	1	0	0
T18	4612	0	0	0
T19	3386	1	0	0
T20	6559	5	0	0
T21	1800	0	0	0
T27	5158	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T68	0	1	0	0
T73	1771	0	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T35,T36
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	204773044	7953	0	0
CgEnOn_A	204773044	5694	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204773044	7953	0	0
T1	21222	1	0	0
T2	201640	2	0	0
T4	14568	6	0	0
T5	3893	1	0	0
T6	1213	1	0	0
T14	748	4	0	0
T15	6886	1	0	0
T16	1312	14	0	0
T22	68286	101	0	0
T23	11407	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204773044	5694	0	0
T3	0	46	0	0
T14	748	3	0	0
T15	6886	0	0	0
T16	1312	13	0	0
T17	1012	1	0	0
T18	2306	0	0	0
T19	1693	1	0	0
T20	3279	5	0	0
T21	900	0	0	0
T27	2579	0	0	0
T35	0	1	0	0
T36	0	4	0	0
T68	0	1	0	0
T73	886	0	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T2
1	0	Covered	T23,T2,T17
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426842906	3956	0	0
CgEnOn_A	426842906	3955	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426842906	3956	0	0
T1	44211	0	0	0
T2	450076	4	0	0
T3	0	32	0	0
T14	1624	2	0	0
T15	14347	0	0	0
T16	2734	0	0	0
T17	2109	1	0	0
T18	4804	0	0	0
T19	3527	1	0	0
T20	6832	0	0	0
T23	23765	9	0	0
T35	0	2	0	0
T68	0	1	0	0
T110	0	9	0	0
T111	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426842906	3955	0	0
T1	44211	0	0	0
T2	450076	4	0	0
T3	0	32	0	0
T14	1624	2	0	0
T15	14347	0	0	0
T16	2734	0	0	0
T17	2109	1	0	0
T18	4804	0	0	0
T19	3527	1	0	0
T20	6832	0	0	0
T23	23765	9	0	0
T35	0	2	0	0
T68	0	1	0	0
T110	0	9	0	0
T111	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T2
1	0	Covered	T23,T2,T17
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426842906	3944	0	0
CgEnOn_A	426842906	3943	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426842906	3944	0	0
T1	44211	0	0	0
T2	450076	3	0	0
T3	0	33	0	0
T14	1624	2	0	0
T15	14347	0	0	0
T16	2734	0	0	0
T17	2109	1	0	0
T18	4804	0	0	0
T19	3527	1	0	0
T20	6832	0	0	0
T23	23765	11	0	0
T35	0	2	0	0
T68	0	1	0	0
T110	0	5	0	0
T111	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426842906	3943	0	0
T1	44211	0	0	0
T2	450076	3	0	0
T3	0	33	0	0
T14	1624	2	0	0
T15	14347	0	0	0
T16	2734	0	0	0
T17	2109	1	0	0
T18	4804	0	0	0
T19	3527	1	0	0
T20	6832	0	0	0
T23	23765	11	0	0
T35	0	2	0	0
T68	0	1	0	0
T110	0	5	0	0
T111	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T2
1	0	Covered	T23,T2,T17
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426842906	3941	0	0
CgEnOn_A	426842906	3940	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426842906	3941	0	0
T1	44211	0	0	0
T2	450076	2	0	0
T3	0	27	0	0
T14	1624	2	0	0
T15	14347	0	0	0
T16	2734	0	0	0
T17	2109	1	0	0
T18	4804	0	0	0
T19	3527	1	0	0
T20	6832	0	0	0
T23	23765	11	0	0
T35	0	2	0	0
T68	0	1	0	0
T110	0	7	0	0
T111	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426842906	3940	0	0
T1	44211	0	0	0
T2	450076	2	0	0
T3	0	27	0	0
T14	1624	2	0	0
T15	14347	0	0	0
T16	2734	0	0	0
T17	2109	1	0	0
T18	4804	0	0	0
T19	3527	1	0	0
T20	6832	0	0	0
T23	23765	11	0	0
T35	0	2	0	0
T68	0	1	0	0
T110	0	7	0	0
T111	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T2
1	0	Covered	T23,T2,T17
1	1	Covered	T5,T4,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	426842906	3938	0	0
CgEnOn_A	426842906	3937	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426842906	3938	0	0
T1	44211	0	0	0
T2	450076	1	0	0
T3	0	28	0	0
T14	1624	2	0	0
T15	14347	0	0	0
T16	2734	0	0	0
T17	2109	1	0	0
T18	4804	0	0	0
T19	3527	1	0	0
T20	6832	0	0	0
T23	23765	8	0	0
T35	0	2	0	0
T68	0	1	0	0
T110	0	6	0	0
T111	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426842906	3937	0	0
T1	44211	0	0	0
T2	450076	1	0	0
T3	0	28	0	0
T14	1624	2	0	0
T15	14347	0	0	0
T16	2734	0	0	0
T17	2109	1	0	0
T18	4804	0	0	0
T19	3527	1	0	0
T20	6832	0	0	0
T23	23765	8	0	0
T35	0	2	0	0
T68	0	1	0	0
T110	0	6	0	0
T111	0	6	0	0