Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T17
0	1	Covered	T16,T20,T3
1	0	Covered	T5,T4,T22

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T19
1	0	Covered	T14,T35,T36
1	1	Covered	T5,T4,T22

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	901271577	14849	0	0
GateOpen_A	901271577	14849	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	901271577	14849	0	0
T3	0	148	0	0
T14	3418	18	0	0
T15	32266	0	0	0
T16	5819	23	0	0
T17	4519	4	0	0
T18	10818	0	0	0
T19	7539	4	0	0
T20	14699	8	0	0
T21	4058	0	0	0
T27	11955	0	0	0
T35	0	10	0	0
T36	0	13	0	0
T68	0	4	0	0
T73	4082	0	0	0
T113	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	901271577	14849	0	0
T3	0	148	0	0
T14	3418	18	0	0
T15	32266	0	0	0
T16	5819	23	0	0
T17	4519	4	0	0
T18	10818	0	0	0
T19	7539	4	0	0
T20	14699	8	0	0
T21	4058	0	0	0
T27	11955	0	0	0
T35	0	10	0	0
T36	0	13	0	0
T68	0	4	0	0
T73	4082	0	0	0
T113	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T17
0	1	Covered	T16,T20,T3
1	0	Covered	T5,T4,T22

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T19
1	0	Covered	T14,T35,T36
1	1	Covered	T5,T4,T22

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	99275810	3670	0	0
GateOpen_A	99275810	3670	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99275810	3670	0	0
T3	0	36	0	0
T14	368	5	0	0
T15	3868	0	0	0
T16	627	5	0	0
T17	494	1	0	0
T18	1299	0	0	0
T19	820	1	0	0
T20	1620	2	0	0
T21	452	0	0	0
T27	1405	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T68	0	1	0	0
T73	475	0	0	0
T113	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99275810	3670	0	0
T3	0	36	0	0
T14	368	5	0	0
T15	3868	0	0	0
T16	627	5	0	0
T17	494	1	0	0
T18	1299	0	0	0
T19	820	1	0	0
T20	1620	2	0	0
T21	452	0	0	0
T27	1405	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T68	0	1	0	0
T73	475	0	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T17
0	1	Covered	T16,T20,T3
1	0	Covered	T5,T4,T22

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T19
1	0	Covered	T14,T35,T36
1	1	Covered	T5,T4,T22

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	198552408	3705	0	0
GateOpen_A	198552408	3705	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198552408	3705	0	0
T3	0	39	0	0
T14	736	5	0	0
T15	7738	0	0	0
T16	1253	7	0	0
T17	987	1	0	0
T18	2599	0	0	0
T19	1640	1	0	0
T20	3240	2	0	0
T21	906	0	0	0
T27	2811	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T68	0	1	0	0
T73	949	0	0	0
T113	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198552408	3705	0	0
T3	0	39	0	0
T14	736	5	0	0
T15	7738	0	0	0
T16	1253	7	0	0
T17	987	1	0	0
T18	2599	0	0	0
T19	1640	1	0	0
T20	3240	2	0	0
T21	906	0	0	0
T27	2811	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T68	0	1	0	0
T73	949	0	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T17
0	1	Covered	T16,T20,T3
1	0	Covered	T5,T4,T22

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T19
1	0	Covered	T14,T35,T36
1	1	Covered	T5,T4,T22

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	398669901	3771	0	0
GateOpen_A	398669901	3771	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398669901	3771	0	0
T3	0	35	0	0
T14	1566	5	0	0
T15	13773	0	0	0
T16	2626	5	0	0
T17	2025	1	0	0
T18	4613	0	0	0
T19	3386	1	0	0
T20	6559	2	0	0
T21	1800	0	0	0
T27	5159	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T68	0	1	0	0
T73	1772	0	0	0
T113	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398669901	3771	0	0
T3	0	35	0	0
T14	1566	5	0	0
T15	13773	0	0	0
T16	2626	5	0	0
T17	2025	1	0	0
T18	4613	0	0	0
T19	3386	1	0	0
T20	6559	2	0	0
T21	1800	0	0	0
T27	5159	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T68	0	1	0	0
T73	1772	0	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T17
0	1	Covered	T16,T20,T3
1	0	Covered	T5,T4,T22

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T19
1	0	Covered	T14,T35,T36
1	1	Covered	T5,T4,T22

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	204773458	3703	0	0
GateOpen_A	204773458	3703	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204773458	3703	0	0
T3	0	38	0	0
T14	748	3	0	0
T15	6887	0	0	0
T16	1313	6	0	0
T17	1013	1	0	0
T18	2307	0	0	0
T19	1693	1	0	0
T20	3280	2	0	0
T21	900	0	0	0
T27	2580	0	0	0
T35	0	1	0	0
T36	0	4	0	0
T68	0	1	0	0
T73	886	0	0	0
T113	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204773458	3703	0	0
T3	0	38	0	0
T14	748	3	0	0
T15	6887	0	0	0
T16	1313	6	0	0
T17	1013	1	0	0
T18	2307	0	0	0
T19	1693	1	0	0
T20	3280	2	0	0
T21	900	0	0	0
T27	2580	0	0	0
T35	0	1	0	0
T36	0	4	0	0
T68	0	1	0	0
T73	886	0	0	0
T113	0	1	0	0