Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	617510	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3607538

1

T7

12

T5

46

T8

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1035296	1			T7	16		T5	5		T8	42
values[0x0]	1468929	1			T7	16		T5	52		T8	24
values[0x1]	1720823	1			T7	17		T5	54		T8	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	340174	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3884874

1

T7

15

T5

59

T8

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17649	1			T2	520		T3	17		T102	1
valid_sources[0x01]	15392	1			T8	1		T2	537		T3	8
valid_sources[0x02]	16829	1			T6	2		T4	7		T2	427
valid_sources[0x03]	15943	1			T8	2		T2	499		T3	15
valid_sources[0x04]	17076	1			T6	2		T2	594		T3	4
valid_sources[0x05]	16803	1			T4	5		T2	550		T3	9
valid_sources[0x06]	16650	1			T6	2		T4	1		T2	573
valid_sources[0x07]	16052	1			T8	1		T4	4		T2	527
valid_sources[0x08]	16180	1			T8	1		T25	1		T6	1
valid_sources[0x09]	16141	1			T4	7		T2	503		T3	2
valid_sources[0x0a]	16999	1			T2	578		T3	13		T102	1
valid_sources[0x0b]	17082	1			T6	3		T2	525		T3	4
valid_sources[0x0c]	15548	1			T7	2		T25	1		T4	7
valid_sources[0x0d]	15505	1			T25	1		T26	1		T4	9
valid_sources[0x0e]	15233	1			T25	1		T2	579		T3	10
valid_sources[0x0f]	16216	1			T7	1		T8	2		T2	507
valid_sources[0x10]	17315	1			T2	532		T3	6		T11	38
valid_sources[0x11]	16107	1			T25	1		T4	1		T2	516
valid_sources[0x12]	15276	1			T8	1		T2	558		T3	15
valid_sources[0x13]	17484	1			T2	576		T3	3		T102	1
valid_sources[0x14]	15024	1			T8	1		T25	1		T2	503
valid_sources[0x15]	16532	1			T4	11		T2	517		T3	12
valid_sources[0x16]	17122	1			T2	518		T3	5		T79	1
valid_sources[0x17]	18916	1			T6	2		T1	1160		T2	580
valid_sources[0x18]	17500	1			T25	1		T6	1		T4	8
valid_sources[0x19]	17189	1			T2	538		T3	11		T69	6
valid_sources[0x1a]	16255	1			T8	1		T2	485		T3	8
valid_sources[0x1b]	15979	1			T7	1		T8	1		T4	5
valid_sources[0x1c]	17038	1			T6	1		T4	1		T2	545
valid_sources[0x1d]	17056	1			T7	1		T8	1		T6	2
valid_sources[0x1e]	16435	1			T6	1		T4	1		T2	500
valid_sources[0x1f]	16898	1			T6	1		T2	544		T3	3
valid_sources[0x20]	15968	1			T4	16		T2	426		T102	1
valid_sources[0x21]	15047	1			T8	1		T6	2		T2	449
valid_sources[0x22]	16491	1			T6	4		T4	1		T2	531
valid_sources[0x23]	16295	1			T26	1		T2	605		T11	74
valid_sources[0x24]	15467	1			T25	1		T2	563		T3	2
valid_sources[0x25]	16515	1			T4	1		T2	542		T3	2
valid_sources[0x26]	16555	1			T2	452		T3	7		T11	56
valid_sources[0x27]	16555	1			T25	1		T4	13		T2	481
valid_sources[0x28]	16770	1			T6	2		T2	551		T3	11
valid_sources[0x29]	17367	1			T4	3		T2	577		T3	8
valid_sources[0x2a]	15457	1			T7	1		T6	1		T4	9
valid_sources[0x2b]	15425	1			T25	1		T4	1		T2	494
valid_sources[0x2c]	16011	1			T2	576		T3	9		T20	1
valid_sources[0x2d]	16489	1			T8	1		T2	530		T3	5
valid_sources[0x2e]	16363	1			T25	1		T4	2		T2	566
valid_sources[0x2f]	15622	1			T7	1		T4	1		T2	584
valid_sources[0x30]	16086	1			T4	2		T2	485		T3	3
valid_sources[0x31]	17286	1			T2	508		T3	5		T79	1
valid_sources[0x32]	15690	1			T26	2		T4	9		T2	495
valid_sources[0x33]	16910	1			T26	1		T4	5		T2	535
valid_sources[0x34]	16111	1			T2	614		T3	6		T20	1
valid_sources[0x35]	16671	1			T26	1		T4	5		T2	553
valid_sources[0x36]	16178	1			T25	1		T2	562		T3	10
valid_sources[0x37]	16963	1			T2	573		T3	10		T11	41
valid_sources[0x38]	16936	1			T8	2		T26	1		T4	5
valid_sources[0x39]	15560	1			T8	1		T2	493		T3	11
valid_sources[0x3a]	16429	1			T2	571		T3	12		T102	1
valid_sources[0x3b]	18368	1			T7	1		T8	1		T25	1
valid_sources[0x3c]	17079	1			T8	2		T4	5		T2	586
valid_sources[0x3d]	17081	1			T2	629		T3	8		T20	2
valid_sources[0x3e]	16375	1			T8	1		T25	1		T6	1
valid_sources[0x3f]	15241	1			T4	3		T2	534		T3	12
valid_sources[0x40]	16538	1			T6	1		T4	4		T2	427
valid_sources[0x41]	16252	1			T7	1		T6	1		T4	2
valid_sources[0x42]	16869	1			T2	507		T3	2		T11	105
valid_sources[0x43]	16279	1			T8	1		T2	550		T3	1
valid_sources[0x44]	15465	1			T2	534		T3	6		T11	52
valid_sources[0x45]	16616	1			T7	2		T25	2		T4	1
valid_sources[0x46]	17034	1			T2	570		T3	13		T102	1
valid_sources[0x47]	16142	1			T2	573		T3	11		T11	88
valid_sources[0x48]	16611	1			T26	2		T2	516		T3	6
valid_sources[0x49]	15931	1			T2	612		T3	11		T102	1
valid_sources[0x4a]	14836	1			T8	1		T2	539		T3	3
valid_sources[0x4b]	15981	1			T4	14		T2	582		T3	8
valid_sources[0x4c]	15660	1			T25	1		T2	555		T3	12
valid_sources[0x4d]	16407	1			T4	3		T2	485		T3	3
valid_sources[0x4e]	18641	1			T8	1		T6	1		T4	4
valid_sources[0x4f]	16079	1			T8	1		T25	1		T2	548
valid_sources[0x50]	15056	1			T8	2		T6	4		T2	622
valid_sources[0x51]	17067	1			T25	1		T4	8		T2	544
valid_sources[0x52]	15868	1			T2	605		T3	1		T80	1
valid_sources[0x53]	15759	1			T7	2		T2	504		T11	99
valid_sources[0x54]	17116	1			T6	1		T2	429		T3	15
valid_sources[0x55]	16452	1			T25	1		T6	1		T2	544
valid_sources[0x56]	15715	1			T6	1		T4	6		T2	614
valid_sources[0x57]	15461	1			T8	1		T2	527		T3	2
valid_sources[0x58]	17146	1			T8	1		T2	554		T3	15
valid_sources[0x59]	16444	1			T8	1		T4	5		T2	514
valid_sources[0x5a]	16047	1			T6	2		T2	575		T3	7
valid_sources[0x5b]	15562	1			T2	574		T3	7		T11	94
valid_sources[0x5c]	15796	1			T2	537		T3	2		T102	2
valid_sources[0x5d]	16826	1			T25	1		T26	1		T6	3
valid_sources[0x5e]	15603	1			T2	550		T3	4		T102	1
valid_sources[0x5f]	16613	1			T8	2		T4	5		T2	513
valid_sources[0x60]	18520	1			T2	491		T3	23		T102	2
valid_sources[0x61]	16162	1			T25	1		T2	586		T3	2
valid_sources[0x62]	16636	1			T7	1		T8	1		T6	2
valid_sources[0x63]	15220	1			T2	466		T3	4		T22	9
valid_sources[0x64]	19637	1			T7	3		T4	4		T2	495
valid_sources[0x65]	17525	1			T25	1		T2	602		T3	10
valid_sources[0x66]	16799	1			T6	1		T2	563		T3	15
valid_sources[0x67]	16607	1			T26	2		T2	514		T3	8
valid_sources[0x68]	15954	1			T2	466		T3	1		T79	1
valid_sources[0x69]	16173	1			T25	1		T6	1		T2	491
valid_sources[0x6a]	15390	1			T6	1		T4	6		T2	503
valid_sources[0x6b]	16531	1			T7	2		T4	2		T2	601
valid_sources[0x6c]	15865	1			T8	1		T26	1		T4	2
valid_sources[0x6d]	19015	1			T7	1		T25	1		T4	5
valid_sources[0x6e]	17065	1			T4	3		T2	493		T3	4
valid_sources[0x6f]	15999	1			T2	581		T3	4		T20	1
valid_sources[0x70]	15151	1			T2	545		T3	11		T11	70
valid_sources[0x71]	15878	1			T7	2		T6	2		T2	560
valid_sources[0x72]	16036	1			T2	611		T3	14		T11	107
valid_sources[0x73]	17070	1			T26	1		T6	1		T4	5
valid_sources[0x74]	15398	1			T6	1		T4	1		T2	478
valid_sources[0x75]	16602	1			T7	1		T26	1		T2	583
valid_sources[0x76]	16531	1			T2	595		T3	4		T11	87
valid_sources[0x77]	16632	1			T8	1		T6	2		T4	11
valid_sources[0x78]	18229	1			T7	3		T26	1		T2	635
valid_sources[0x79]	16494	1			T2	550		T3	1		T20	1
valid_sources[0x7a]	19958	1			T26	1		T4	2		T2	523
valid_sources[0x7b]	16245	1			T2	578		T79	1		T11	76
valid_sources[0x7c]	17536	1			T8	1		T26	1		T6	1
valid_sources[0x7d]	17542	1			T7	2		T8	1		T6	2
valid_sources[0x7e]	15790	1			T25	1		T4	16		T2	503
valid_sources[0x7f]	18388	1			T7	1		T25	1		T6	2
valid_sources[0x80]	16304	1			T25	1		T4	4		T2	501

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

909285

1

T7

7

T5

1

T8

15

values[0x0]

all_enables

biggest_size

1374413

1

T7

2

T5

29

T8

7

values[0x1]

all_enables

biggest_size

1323840

1

T7

3

T5

16

T8

1