Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg

Group : clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
PeriDiv2	100.00	1	100	1	64	64
PeriDiv4	100.00	1	100	1	64	64
PeriIo	100.00	1	100	1	64	64
PeriUsb	100.00	1	100	1	64	64

---

Group Instance : PeriDiv2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriDiv2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriDiv2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriDiv2

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

---

Group Instance : PeriDiv4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriDiv4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriDiv4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriDiv4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

---

Group Instance : PeriIo

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriIo

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriIo

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriIo

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

---

Group Instance : PeriUsb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriUsb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriUsb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriUsb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294477

1

T7

2

T5

2

T8

3

auto[1]

206026402

1

T7

5745

T5

26588

T8

737

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7659

1

T7

2

T5

2

T8

2

auto[1]

206313220

1

T7

5745

T5

26588

T8

738

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112944311

1

T7

4981

T5

26590

T8

740

auto[1]

93376568

1

T7

766

T25

2454

T26

73

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

4852

1

T7

2

T5

2

T8

2

auto[0]

auto[0]

auto[1]

1552

1

T1

6

T2

12

T3

12

auto[0]

auto[1]

auto[0]

229885

1

T8

1

T1

48

T2

532

auto[0]

auto[1]

auto[1]

58188

1

T1

56

T2

503

T3

131

auto[1]

auto[1]

auto[0]

112708319

1

T7

4979

T5

26588

T8

737

auto[1]

auto[1]

auto[1]

93316828

1

T7

766

T25

2454

T26

73

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152379

1

T7

2

T5

2

T8

3

auto[1]

103006364

1

T7

2870

T5

13293

T8

366

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7037

1

T7

2

T5

2

T8

2

auto[1]

103151706

1

T7

2870

T5

13293

T8

367

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56470392

1

T7

2490

T5

13295

T8

369

auto[1]

46688351

1

T7

382

T25

1226

T26

36

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

4852

1

T7

2

T5

2

T8

2

auto[0]

auto[0]

auto[1]

1552

1

T1

6

T2

12

T3

12

auto[0]

auto[1]

auto[0]

116216

1

T8

1

T1

25

T2

263

auto[0]

auto[1]

auto[1]

29759

1

T1

27

T2

252

T3

71

auto[1]

auto[1]

auto[0]

56348691

1

T7

2488

T5

13293

T8

366

auto[1]

auto[1]

auto[1]

46657040

1

T7

382

T25

1226

T26

36

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

524951

1

T7

2

T5

2

T8

5

auto[1]

411582891

1

T7

10222

T5

53178

T8

1474

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8910

1

T7

2

T5

2

T8

2

auto[1]

412098932

1

T7

10222

T5

53178

T8

1477

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

225354710

1

T7

8693

T5

53180

T8

1479

auto[1]

186753132

1

T7

1531

T25

4907

T26

146

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

4852

1

T7

2

T5

2

T8

2

auto[0]

auto[0]

auto[1]

1552

1

T1

6

T2

12

T3

12

auto[0]

auto[1]

auto[0]

402686

1

T8

3

T1

93

T2

970

auto[0]

auto[1]

auto[1]

115861

1

T1

117

T2

1089

T3

288

auto[1]

auto[1]

auto[0]

224944666

1

T7

8691

T5

53178

T8

1474

auto[1]

auto[1]

auto[1]

186635719

1

T7

1531

T25

4907

T26

146

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262623

1

T7

2

T5

2

T8

4

auto[1]

211132798

1

T7

5111

T5

26590

T8

735

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7369

1

T7

2

T5

2

T8

2

auto[1]

211388052

1

T7

5111

T5

26590

T8

737

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115693607

1

T7

4346

T5

26592

T8

739

auto[1]

95701814

1

T7

767

T25

2453

T26

72

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

4840

1

T7

2

T5

2

T8

2

auto[0]

auto[0]

auto[1]

1564

1

T1

6

T2

12

T3

12

auto[0]

auto[1]

auto[0]

199266

1

T8

2

T1

42

T2

481

auto[0]

auto[1]

auto[1]

56953

1

T1

63

T2

547

T3

154

auto[1]

auto[1]

auto[0]

115488536

1

T7

4344

T5

26590

T8

735

auto[1]

auto[1]

auto[1]

95643297

1

T7

767

T25

2453

T26

72

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded