Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	758909170	73699	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758909170	73699	0	0
T1	2502990	191	0	0
T2	1855115	2398	0	0
T3	376930	293	0	0
T11	0	734	0	0
T12	0	422	0	0
T13	0	91	0	0
T14	0	321	0	0
T15	0	258	0	0
T16	0	864	0	0
T17	0	186	0	0
T18	4595	0	0	0
T19	6665	0	0	0
T20	10600	0	0	0
T21	6060	0	0	0
T22	5285	0	0	0
T23	11435	0	0	0
T24	6570	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151781834	10909	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	10909	0	0
T1	500598	25	0	0
T2	371023	349	0	0
T3	75386	57	0	0
T11	0	105	0	0
T12	0	62	0	0
T13	0	14	0	0
T14	0	51	0	0
T15	0	47	0	0
T16	0	126	0	0
T17	0	35	0	0
T18	919	0	0	0
T19	1333	0	0	0
T20	2120	0	0	0
T21	1212	0	0	0
T22	1057	0	0	0
T23	2287	0	0	0
T24	1314	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151781834	14795	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	14795	0	0
T1	500598	39	0	0
T2	371023	483	0	0
T3	75386	57	0	0
T11	0	143	0	0
T12	0	81	0	0
T13	0	18	0	0
T14	0	65	0	0
T15	0	50	0	0
T16	0	173	0	0
T17	0	35	0	0
T18	919	0	0	0
T19	1333	0	0	0
T20	2120	0	0	0
T21	1212	0	0	0
T22	1057	0	0	0
T23	2287	0	0	0
T24	1314	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151781834	22235	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	22235	0	0
T1	500598	63	0	0
T2	371023	746	0	0
T3	75386	65	0	0
T11	0	218	0	0
T12	0	137	0	0
T13	0	25	0	0
T14	0	89	0	0
T15	0	64	0	0
T16	0	268	0	0
T17	0	46	0	0
T18	919	0	0	0
T19	1333	0	0	0
T20	2120	0	0	0
T21	1212	0	0	0
T22	1057	0	0	0
T23	2287	0	0	0
T24	1314	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151781834	10852	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	10852	0	0
T1	500598	25	0	0
T2	371023	338	0	0
T3	75386	57	0	0
T11	0	103	0	0
T12	0	58	0	0
T13	0	14	0	0
T14	0	51	0	0
T15	0	47	0	0
T16	0	124	0	0
T17	0	35	0	0
T18	919	0	0	0
T19	1333	0	0	0
T20	2120	0	0	0
T21	1212	0	0	0
T22	1057	0	0	0
T23	2287	0	0	0
T24	1314	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151781834	14908	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	14908	0	0
T1	500598	39	0	0
T2	371023	482	0	0
T3	75386	57	0	0
T11	0	165	0	0
T12	0	84	0	0
T13	0	20	0	0
T14	0	65	0	0
T15	0	50	0	0
T16	0	173	0	0
T17	0	35	0	0
T18	919	0	0	0
T19	1333	0	0	0
T20	2120	0	0	0
T21	1212	0	0	0
T22	1057	0	0	0
T23	2287	0	0	0
T24	1314	0	0	0