Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T4,T1,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	151781834	149335611	0	0
AllClkBypReqTrue_A	151781834	122316	0	0
IoClkBypReqFalse_A	151781834	149256819	0	2415
IoClkBypReqTrue_A	151781834	196772	0	0
LcClkBypAckFalse_A	151781834	149343402	0	0
LcClkBypAckTrue_A	151781834	114525	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	149335611	0	0
T1	500598	500055	0	0
T2	371023	369994	0	0
T4	81115	8047	0	0
T5	60895	60784	0	0
T6	14240	14219	0	0
T7	2155	1730	0	0
T8	1705	1510	0	0
T18	919	869	0	0
T25	1507	1469	0	0
T26	2300	1820	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	122316	0	0
T1	500598	0	0	0
T2	371023	1325	0	0
T3	0	298	0	0
T4	81115	0	0	0
T5	60895	0	0	0
T6	14240	0	0	0
T7	2155	399	0	0
T8	1705	0	0	0
T11	0	344	0	0
T18	919	0	0	0
T19	0	6	0	0
T20	0	233	0	0
T23	0	170	0	0
T25	1507	26	0	0
T26	2300	239	0	0
T69	0	382	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	149256819	0	2415
T1	500598	500045	0	3
T2	371023	369915	0	3
T4	81115	8019	0	3
T5	60895	60782	0	3
T6	14240	14217	0	3
T7	2155	1748	0	3
T8	1705	1508	0	3
T18	919	867	0	3
T25	1507	1184	0	3
T26	2300	1739	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	196772	0	0
T1	500598	0	0	0
T2	371023	2099	0	0
T3	0	331	0	0
T4	81115	0	0	0
T5	60895	0	0	0
T6	14240	0	0	0
T7	2155	379	0	0
T8	1705	0	0	0
T11	0	559	0	0
T18	919	0	0	0
T19	0	213	0	0
T20	0	351	0	0
T23	0	302	0	0
T25	1507	309	0	0
T26	2300	318	0	0
T69	0	400	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	149343402	0	0
T1	500598	500055	0	0
T2	371023	370002	0	0
T4	81115	8047	0	0
T5	60895	60784	0	0
T6	14240	14219	0	0
T7	2155	1973	0	0
T8	1705	1510	0	0
T18	919	869	0	0
T25	1507	1432	0	0
T26	2300	1821	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	114525	0	0
T1	500598	0	0	0
T2	371023	1243	0	0
T3	0	229	0	0
T4	81115	0	0	0
T5	60895	0	0	0
T6	14240	0	0	0
T7	2155	156	0	0
T8	1705	0	0	0
T11	0	301	0	0
T18	919	0	0	0
T19	0	94	0	0
T20	0	160	0	0
T23	0	163	0	0
T25	1507	63	0	0
T26	2300	238	0	0
T69	0	268	0	0