Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1772040724	15282	0	0
TransStop_A	1772040724	7665	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1772040724	15282	0	0
T1	1944264	37	0	0
T2	2917788	288	0	0
T3	425976	44	0	0
T4	337996	0	0	0
T6	316472	0	0	0
T8	6960	4	0	0
T11	0	208	0	0
T12	0	45	0	0
T18	13392	0	0	0
T19	10668	0	0	0
T25	66972	0	0	0
T26	9204	0	0	0
T29	0	23	0	0
T79	0	19	0	0
T80	0	26	0	0
T102	0	22	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1772040724	7665	0	0
T1	1944264	24	0	0
T2	2917788	146	0	0
T3	425976	29	0	0
T4	337996	0	0	0
T6	316472	0	0	0
T8	6960	4	0	0
T11	0	91	0	0
T12	0	30	0	0
T13	0	5	0	0
T18	13392	0	0	0
T19	10668	0	0	0
T25	66972	0	0	0
T26	9204	0	0	0
T29	0	5	0	0
T79	0	6	0	0
T80	0	14	0	0
T102	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	443010181	3822	0	0
TransStop_A	443010181	1902	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443010181	3822	0	0
T1	486066	7	0	0
T2	729447	69	0	0
T3	106494	13	0	0
T4	84499	0	0	0
T6	79118	0	0	0
T8	1740	1	0	0
T11	0	51	0	0
T12	0	8	0	0
T18	3348	0	0	0
T19	2667	0	0	0
T25	16743	0	0	0
T26	2301	0	0	0
T29	0	5	0	0
T79	0	6	0	0
T80	0	8	0	0
T102	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443010181	1902	0	0
T1	486066	5	0	0
T2	729447	32	0	0
T3	106494	7	0	0
T4	84499	0	0	0
T6	79118	0	0	0
T8	1740	1	0	0
T11	0	25	0	0
T12	0	5	0	0
T18	3348	0	0	0
T19	2667	0	0	0
T25	16743	0	0	0
T26	2301	0	0	0
T29	0	1	0	0
T79	0	3	0	0
T80	0	5	0	0
T102	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	443010181	3855	0	0
TransStop_A	443010181	1951	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443010181	3855	0	0
T1	486066	5	0	0
T2	729447	74	0	0
T3	106494	10	0	0
T4	84499	0	0	0
T6	79118	0	0	0
T8	1740	1	0	0
T11	0	55	0	0
T12	0	12	0	0
T18	3348	0	0	0
T19	2667	0	0	0
T25	16743	0	0	0
T26	2301	0	0	0
T29	0	4	0	0
T79	0	4	0	0
T80	0	6	0	0
T102	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443010181	1951	0	0
T1	486066	2	0	0
T2	729447	37	0	0
T3	106494	7	0	0
T4	84499	0	0	0
T6	79118	0	0	0
T8	1740	1	0	0
T11	0	23	0	0
T12	0	8	0	0
T13	0	5	0	0
T18	3348	0	0	0
T19	2667	0	0	0
T25	16743	0	0	0
T26	2301	0	0	0
T29	0	1	0	0
T80	0	3	0	0
T102	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	443010181	3796	0	0
TransStop_A	443010181	1902	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443010181	3796	0	0
T1	486066	12	0	0
T2	729447	67	0	0
T3	106494	10	0	0
T4	84499	0	0	0
T6	79118	0	0	0
T8	1740	1	0	0
T11	0	50	0	0
T12	0	13	0	0
T18	3348	0	0	0
T19	2667	0	0	0
T25	16743	0	0	0
T26	2301	0	0	0
T29	0	7	0	0
T79	0	4	0	0
T80	0	6	0	0
T102	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443010181	1902	0	0
T1	486066	9	0	0
T2	729447	35	0	0
T3	106494	8	0	0
T4	84499	0	0	0
T6	79118	0	0	0
T8	1740	1	0	0
T11	0	18	0	0
T12	0	9	0	0
T18	3348	0	0	0
T19	2667	0	0	0
T25	16743	0	0	0
T26	2301	0	0	0
T29	0	1	0	0
T79	0	2	0	0
T80	0	4	0	0
T102	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	443010181	3809	0	0
TransStop_A	443010181	1910	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443010181	3809	0	0
T1	486066	13	0	0
T2	729447	78	0	0
T3	106494	11	0	0
T4	84499	0	0	0
T6	79118	0	0	0
T8	1740	1	0	0
T11	0	52	0	0
T12	0	12	0	0
T18	3348	0	0	0
T19	2667	0	0	0
T25	16743	0	0	0
T26	2301	0	0	0
T29	0	7	0	0
T79	0	5	0	0
T80	0	6	0	0
T102	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443010181	1910	0	0
T1	486066	8	0	0
T2	729447	42	0	0
T3	106494	7	0	0
T4	84499	0	0	0
T6	79118	0	0	0
T8	1740	1	0	0
T11	0	25	0	0
T12	0	8	0	0
T18	3348	0	0	0
T19	2667	0	0	0
T25	16743	0	0	0
T26	2301	0	0	0
T29	0	2	0	0
T79	0	1	0	0
T80	0	2	0	0
T102	0	1	0	0