Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T5,T8
01CoveredT7,T5,T8
10CoveredT7,T25,T26 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T5,T8
10CoveredT7,T25,T26
11CoveredT7,T25,T26 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT7,T25,T26
10CoveredT7,T5,T8
11CoveredT7,T5,T8
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 515673219 515670804 0 0
selKnown1 1243006431 1243004016 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 515673219 515670804 0 0
T1 532527 532524 0 0
T2 848992 848992 0 0
T4 56966 56963 0 0
T5 66545 66542 0 0
T6 87690 87687 0 0
T7 13781 13778 0 0
T8 1987 1984 0 0
T18 3895 3892 0 0
T25 20591 20588 0 0
T26 2807 2804 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1243006431 1243004016 0 0
T1 1278873 1278870 0 0
T2 2038533 2038533 0 0
T4 243345 243342 0 0
T5 159864 159861 0 0
T6 210570 210567 0 0
T7 31035 31032 0 0
T8 5007 5004 0 0
T18 9708 9705 0 0
T25 48216 48213 0 0
T26 6627 6624 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T5,T8
01CoveredT7,T5,T8
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T5,T8
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT7,T5,T8
11CoveredT7,T5,T8
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 206375244 206374439 0 0
selKnown1 414335477 414334672 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 206375244 206374439 0 0
T1 213011 213010 0 0
T2 339674 339674 0 0
T4 22787 22786 0 0
T5 26618 26617 0 0
T6 35076 35075 0 0
T7 5766 5765 0 0
T8 795 794 0 0
T18 1558 1557 0 0
T25 8397 8396 0 0
T26 1176 1175 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 414335477 414334672 0 0
T1 426291 426290 0 0
T2 679511 679511 0 0
T4 81115 81114 0 0
T5 53288 53287 0 0
T6 70190 70189 0 0
T7 10345 10344 0 0
T8 1669 1668 0 0
T18 3236 3235 0 0
T25 16072 16071 0 0
T26 2209 2208 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T5,T8
01CoveredT7,T5,T8
10CoveredT7,T25,T26 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T5,T8
10CoveredT7,T25,T26
11CoveredT7,T25,T26 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT7,T25,T26
10CoveredT7,T5,T8
11CoveredT7,T5,T8
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 206110876 206110071 0 0
selKnown1 414335477 414334672 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 206110876 206110071 0 0
T1 213011 213010 0 0
T2 339482 339482 0 0
T4 22787 22786 0 0
T5 26618 26617 0 0
T6 35076 35075 0 0
T7 5133 5132 0 0
T8 795 794 0 0
T18 1558 1557 0 0
T25 7996 7995 0 0
T26 1044 1043 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 414335477 414334672 0 0
T1 426291 426290 0 0
T2 679511 679511 0 0
T4 81115 81114 0 0
T5 53288 53287 0 0
T6 70190 70189 0 0
T7 10345 10344 0 0
T8 1669 1668 0 0
T18 3236 3235 0 0
T25 16072 16071 0 0
T26 2209 2208 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T5,T8
01CoveredT7,T5,T8
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T5,T8
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT7,T5,T8
11CoveredT7,T5,T8
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 103187099 103186294 0 0
selKnown1 414335477 414334672 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 103187099 103186294 0 0
T1 106505 106504 0 0
T2 169836 169836 0 0
T4 11392 11391 0 0
T5 13309 13308 0 0
T6 17538 17537 0 0
T7 2882 2881 0 0
T8 397 396 0 0
T18 779 778 0 0
T25 4198 4197 0 0
T26 587 586 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 414335477 414334672 0 0
T1 426291 426290 0 0
T2 679511 679511 0 0
T4 81115 81114 0 0
T5 53288 53287 0 0
T6 70190 70189 0 0
T7 10345 10344 0 0
T8 1669 1668 0 0
T18 3236 3235 0 0
T25 16072 16071 0 0
T26 2209 2208 0 0

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