Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clkmgr_byp.u_io_byp_req	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_all_byp_req	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_hi_speed_sel	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_main_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_usb_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_main_secure	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_usb_peri	100.00	100.00					100.00
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender	100.00	100.00					100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_aes_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_hmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_kmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_otbn_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_byp_req

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_hi_speed_sel

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_main_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_usb_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_main_secure

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_usb_peri

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6583678	6576626	0	0
T2	8908321	8888494	0	0
T4	1084823	114797	0	0
T5	746083	744647	0	0
T6	851018	849830	0	0
T7	125223	123948	0	0
T8	23733	21171	0	0
T18	38849	36806	0	0
T25	186775	185542	0	0
T26	32026	28952	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	151781834	149460095	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	149460095	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	151781834	149460095	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	149460095	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	151781834	149460095	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151781834	149460095	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	103187099	102656510	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187099	102656510	0	0
T1	106505	106440	0	0
T2	169836	169612	0	0
T4	11392	2015	0	0
T5	13309	13295	0	0
T6	17538	17521	0	0
T7	2882	2872	0	0
T8	397	369	0	0
T18	779	762	0	0
T25	4198	4188	0	0
T26	587	559	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	443009740	438519538	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	438519538	0	0
T1	486065	485511	0	0
T2	729447	727656	0	0
T4	84498	8386	0	0
T5	49510	49398	0	0
T6	79117	79005	0	0
T7	10777	10651	0	0
T8	1739	1541	0	0
T18	3347	3149	0	0
T25	16742	16616	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	212543150	210391016	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212543150	210391016	0	0
T1	230435	230169	0	0
T2	350428	349569	0	0
T4	40559	4025	0	0
T5	26645	26592	0	0
T6	26456	26403	0	0
T7	5173	5113	0	0
T8	834	739	0	0
T18	1653	1558	0	0
T25	8036	7976	0	0
T26	1104	989	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	414335477	410099081	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414335477	410099081	0	0
T1	426291	425761	0	0
T2	679511	678068	0	0
T4	81115	8061	0	0
T5	53288	53180	0	0
T6	70190	70083	0	0
T7	10345	10224	0	0
T8	1669	1479	0	0
T18	3236	3046	0	0
T25	16072	15951	0	0
T26	2209	1978	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	206375244	205313988	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206375244	205313988	0	0
T1	213011	212880	0	0
T2	339674	339226	0	0
T4	22787	4033	0	0
T5	26618	26590	0	0
T6	35076	35042	0	0
T7	5766	5745	0	0
T8	795	740	0	0
T18	1558	1523	0	0
T25	8397	8376	0	0
T26	1176	1121	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	103187099	102656510	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187099	102656510	0	0
T1	106505	106440	0	0
T2	169836	169612	0	0
T4	11392	2015	0	0
T5	13309	13295	0	0
T6	17538	17521	0	0
T7	2882	2872	0	0
T8	397	369	0	0
T18	779	762	0	0
T25	4198	4188	0	0
T26	587	559	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	443009740	438519538	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	438519538	0	0
T1	486065	485511	0	0
T2	729447	727656	0	0
T4	84498	8386	0	0
T5	49510	49398	0	0
T6	79117	79005	0	0
T7	10777	10651	0	0
T8	1739	1541	0	0
T18	3347	3149	0	0
T25	16742	16616	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	103187099	102656510	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187099	102656510	0	0
T1	106505	106440	0	0
T2	169836	169612	0	0
T4	11392	2015	0	0
T5	13309	13295	0	0
T6	17538	17521	0	0
T7	2882	2872	0	0
T8	397	369	0	0
T18	779	762	0	0
T25	4198	4188	0	0
T26	587	559	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	103187099	102656510	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187099	102656510	0	0
T1	106505	106440	0	0
T2	169836	169612	0	0
T4	11392	2015	0	0
T5	13309	13295	0	0
T6	17538	17521	0	0
T7	2882	2872	0	0
T8	397	369	0	0
T18	779	762	0	0
T25	4198	4188	0	0
T26	587	559	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	206375244	205313988	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206375244	205313988	0	0
T1	213011	212880	0	0
T2	339674	339226	0	0
T4	22787	4033	0	0
T5	26618	26590	0	0
T6	35076	35042	0	0
T7	5766	5745	0	0
T8	795	740	0	0
T18	1558	1523	0	0
T25	8397	8376	0	0
T26	1176	1121	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	414335477	410099081	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414335477	410099081	0	0
T1	426291	425761	0	0
T2	679511	678068	0	0
T4	81115	8061	0	0
T5	53288	53180	0	0
T6	70190	70083	0	0
T7	10345	10224	0	0
T8	1669	1479	0	0
T18	3236	3046	0	0
T25	16072	15951	0	0
T26	2209	1978	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	212543150	210391016	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212543150	210391016	0	0
T1	230435	230169	0	0
T2	350428	349569	0	0
T4	40559	4025	0	0
T5	26645	26592	0	0
T6	26456	26403	0	0
T7	5173	5113	0	0
T8	834	739	0	0
T18	1653	1558	0	0
T25	8036	7976	0	0
T26	1104	989	0	0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	443009740	438519538	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	438519538	0	0
T1	486065	485511	0	0
T2	729447	727656	0	0
T4	84498	8386	0	0
T5	49510	49398	0	0
T6	79117	79005	0	0
T7	10777	10651	0	0
T8	1739	1541	0	0
T18	3347	3149	0	0
T25	16742	16616	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	443009740	438519538	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	438519538	0	0
T1	486065	485511	0	0
T2	729447	727656	0	0
T4	84498	8386	0	0
T5	49510	49398	0	0
T6	79117	79005	0	0
T7	10777	10651	0	0
T8	1739	1541	0	0
T18	3347	3149	0	0
T25	16742	16616	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	443009740	438519538	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	438519538	0	0
T1	486065	485511	0	0
T2	729447	727656	0	0
T4	84498	8386	0	0
T5	49510	49398	0	0
T6	79117	79005	0	0
T7	10777	10651	0	0
T8	1739	1541	0	0
T18	3347	3149	0	0
T25	16742	16616	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	443009740	438519538	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	438519538	0	0
T1	486065	485511	0	0
T2	729447	727656	0	0
T4	84498	8386	0	0
T5	49510	49398	0	0
T6	79117	79005	0	0
T7	10777	10651	0	0
T8	1739	1541	0	0
T18	3347	3149	0	0
T25	16742	16616	0	0
T26	2300	2060	0	0