Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	152667191	5283642	0	0
clk_enables_rd_A	152667191	30466	0	0
clk_hints_rd_A	152667191	27329	0	0
extclk_ctrl_rd_A	152667191	34645	0	0
extclk_ctrl_regwen_rd_A	152667191	27187	0	0
jitter_enable_rd_A	152667191	36786	0	0
jitter_regwen_rd_A	152667191	29201	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	5283642	0	0
T2	371023	177523	0	0
T3	75386	0	0	0
T11	0	24786	0	0
T14	0	30144	0	0
T16	0	68113	0	0
T17	0	31586	0	0
T18	919	0	0	0
T19	1333	0	0	0
T20	2120	0	0	0
T21	1212	0	0	0
T22	1057	0	0	0
T23	2287	0	0	0
T24	1314	0	0	0
T28	0	91350	0	0
T29	2030	0	0	0
T32	0	153509	0	0
T66	0	74395	0	0
T67	0	118684	0	0
T68	0	132505	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	30466	0	0
T13	50950	7	0	0
T14	963126	573	0	0
T17	0	1324	0	0
T30	2186	0	0	0
T31	1671	0	0	0
T67	0	4328	0	0
T82	1828	0	0	0
T85	0	3439	0	0
T109	57589	0	0	0
T122	0	8	0	0
T123	0	5	0	0
T124	0	2410	0	0
T125	0	4	0	0
T126	0	3	0	0
T127	2237	0	0	0
T128	24684	0	0	0
T129	1702	0	0	0
T130	831	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	27329	0	0
T13	50950	13	0	0
T14	963126	556	0	0
T17	0	1143	0	0
T30	2186	0	0	0
T31	1671	0	0	0
T67	0	4255	0	0
T82	1828	0	0	0
T85	0	2787	0	0
T109	57589	0	0	0
T122	0	5	0	0
T123	0	9	0	0
T124	0	1880	0	0
T125	0	9	0	0
T126	0	8	0	0
T127	2237	0	0	0
T128	24684	0	0	0
T129	1702	0	0	0
T130	831	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	34645	0	0
T1	500598	0	0	0
T2	371023	0	0	0
T4	81115	95	0	0
T5	60895	0	0	0
T6	14240	0	0	0
T7	2155	67	0	0
T8	1705	0	0	0
T13	0	51	0	0
T14	0	733	0	0
T17	0	1569	0	0
T18	919	0	0	0
T19	0	5	0	0
T20	0	41	0	0
T25	1507	0	0	0
T26	2300	23	0	0
T69	0	29	0	0
T131	0	41	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	27187	0	0
T1	500598	0	0	0
T2	371023	0	0	0
T3	75386	0	0	0
T4	81115	39	0	0
T14	0	541	0	0
T17	0	1156	0	0
T18	919	0	0	0
T19	1333	0	0	0
T20	2120	0	0	0
T21	1212	0	0	0
T22	1057	0	0	0
T23	2287	0	0	0
T41	0	17	0	0
T67	0	4305	0	0
T85	0	2907	0	0
T132	0	75	0	0
T133	0	53	0	0
T134	0	21	0	0
T135	0	30	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	36786	0	0
T13	50950	459	0	0
T14	963126	441	0	0
T17	0	1990	0	0
T30	2186	0	0	0
T31	1671	0	0	0
T67	0	5069	0	0
T82	1828	0	0	0
T85	0	3931	0	0
T109	57589	0	0	0
T122	0	87	0	0
T123	0	114	0	0
T124	0	2091	0	0
T125	0	115	0	0
T126	0	106	0	0
T127	2237	0	0	0
T128	24684	0	0	0
T129	1702	0	0	0
T130	831	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	29201	0	0
T14	963126	643	0	0
T17	0	1198	0	0
T30	2186	0	0	0
T31	1671	0	0	0
T67	0	4728	0	0
T85	0	3405	0	0
T109	57589	0	0	0
T124	0	2153	0	0
T127	2237	0	0	0
T128	24684	0	0	0
T129	1702	0	0	0
T130	831	0	0	0
T136	0	1908	0	0
T137	0	3867	0	0
T138	0	2493	0	0
T139	0	1618	0	0
T140	0	1757	0	0
T141	1308	0	0	0
T142	2138	0	0	0