Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T5,T8
1	1	Covered	T7,T5,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48041	0	0
CgEnOn_A	2147483647	39370	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48041	0	0
T1	2920502	72	0	0
T2	4457237	500	0	0
T3	2658098	13	0	0
T4	493845	42	0	0
T5	119860	3	0	0
T6	465728	3	0	0
T7	24166	3	0	0
T8	10651	5	0	0
T14	0	5	0	0
T18	34439	30	0	0
T19	21877	0	0	0
T20	9077	0	0	0
T21	20111	0	0	0
T22	36544	0	0	0
T23	9659	0	0	0
T24	22667	0	0	0
T25	103671	3	0	0
T26	14276	3	0	0
T29	17424	5	0	0
T35	0	17	0	0
T36	0	15	0	0
T67	0	5	0	0
T102	33072	0	0	0
T143	0	20	0	0
T144	0	10	0	0
T145	0	10	0	0
T146	0	5	0	0
T151	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39370	0	0
T1	2920502	34	0	0
T2	4457237	268	0	0
T3	4730358	25	0	0
T4	459666	0	0	0
T6	413114	0	0	0
T8	9459	0	0	0
T11	0	43	0	0
T12	0	78	0	0
T13	0	8	0	0
T14	0	4	0	0
T18	34439	21	0	0
T19	27706	0	0	0
T20	10758	0	0	0
T21	23564	0	0	0
T22	42834	16	0	0
T23	11394	0	0	0
T24	26540	34	0	0
T25	91076	0	0	0
T26	12513	0	0	0
T29	17424	0	0	0
T35	0	21	0	0
T36	0	15	0	0
T67	0	4	0	0
T102	33072	0	0	0
T143	0	20	0	0
T144	0	10	0	0
T145	0	10	0	0
T146	0	5	0	0
T147	0	5	0	0
T148	0	4	0	0
T149	0	6	0	0
T151	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	206375244	139	0	0
CgEnOn_A	206375244	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206375244	139	0	0
T3	449414	0	0	0
T14	0	1	0	0
T18	1558	3	0	0
T19	1326	0	0	0
T20	1121	0	0	0
T21	2302	0	0	0
T22	4193	0	0	0
T23	1158	0	0	0
T24	2582	0	0	0
T29	1963	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T67	0	1	0	0
T102	3797	0	0	0
T143	0	4	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206375244	139	0	0
T3	449414	0	0	0
T14	0	1	0	0
T18	1558	3	0	0
T19	1326	0	0	0
T20	1121	0	0	0
T21	2302	0	0	0
T22	4193	0	0	0
T23	1158	0	0	0
T24	2582	0	0	0
T29	1963	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T67	0	1	0	0
T102	3797	0	0	0
T143	0	4	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103187099	139	0	0
CgEnOn_A	103187099	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187099	139	0	0
T3	224707	0	0	0
T14	0	1	0	0
T18	779	3	0	0
T19	663	0	0	0
T20	560	0	0	0
T21	1151	0	0	0
T22	2097	0	0	0
T23	577	0	0	0
T24	1291	0	0	0
T29	981	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T67	0	1	0	0
T102	1899	0	0	0
T143	0	4	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187099	139	0	0
T3	224707	0	0	0
T14	0	1	0	0
T18	779	3	0	0
T19	663	0	0	0
T20	560	0	0	0
T21	1151	0	0	0
T22	2097	0	0	0
T23	577	0	0	0
T24	1291	0	0	0
T29	981	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T67	0	1	0	0
T102	1899	0	0	0
T143	0	4	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	414335477	139	0	0
CgEnOn_A	414335477	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414335477	139	0	0
T3	895599	0	0	0
T14	0	1	0	0
T18	3236	3	0	0
T19	2560	0	0	0
T20	2036	0	0	0
T21	4656	0	0	0
T22	8452	0	0	0
T23	2196	0	0	0
T24	5258	0	0	0
T29	4060	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T67	0	1	0	0
T102	7646	0	0	0
T143	0	4	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414335477	129	0	0
T3	895599	0	0	0
T18	3236	3	0	0
T19	2560	0	0	0
T20	2036	0	0	0
T21	4656	0	0	0
T22	8452	0	0	0
T23	2196	0	0	0
T24	5258	0	0	0
T29	4060	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T102	7646	0	0	0
T143	0	4	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	5	0	0
T148	0	4	0	0
T149	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	443009740	129	0	0
CgEnOn_A	443009740	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	129	0	0
T3	106494	0	0	0
T18	3347	3	0	0
T19	2667	0	0	0
T20	2120	0	0	0
T21	4850	0	0	0
T22	8804	0	0	0
T23	2287	0	0	0
T24	5477	0	0	0
T29	4229	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T102	7966	0	0	0
T143	0	3	0	0
T144	0	5	0	0
T145	0	5	0	0
T146	0	1	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	127	0	0
T3	106494	0	0	0
T18	3347	3	0	0
T19	2667	0	0	0
T20	2120	0	0	0
T21	4850	0	0	0
T22	8804	0	0	0
T23	2287	0	0	0
T24	5477	0	0	0
T29	4229	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T102	7966	0	0	0
T143	0	3	0	0
T144	0	5	0	0
T145	0	5	0	0
T146	0	1	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103187099	139	0	0
CgEnOn_A	103187099	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187099	139	0	0
T3	224707	0	0	0
T14	0	1	0	0
T18	779	3	0	0
T19	663	0	0	0
T20	560	0	0	0
T21	1151	0	0	0
T22	2097	0	0	0
T23	577	0	0	0
T24	1291	0	0	0
T29	981	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T67	0	1	0	0
T102	1899	0	0	0
T143	0	4	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187099	139	0	0
T3	224707	0	0	0
T14	0	1	0	0
T18	779	3	0	0
T19	663	0	0	0
T20	560	0	0	0
T21	1151	0	0	0
T22	2097	0	0	0
T23	577	0	0	0
T24	1291	0	0	0
T29	981	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T67	0	1	0	0
T102	1899	0	0	0
T143	0	4	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	443009740	129	0	0
CgEnOn_A	443009740	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	129	0	0
T3	106494	0	0	0
T18	3347	3	0	0
T19	2667	0	0	0
T20	2120	0	0	0
T21	4850	0	0	0
T22	8804	0	0	0
T23	2287	0	0	0
T24	5477	0	0	0
T29	4229	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T102	7966	0	0	0
T143	0	3	0	0
T144	0	5	0	0
T145	0	5	0	0
T146	0	1	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	127	0	0
T3	106494	0	0	0
T18	3347	3	0	0
T19	2667	0	0	0
T20	2120	0	0	0
T21	4850	0	0	0
T22	8804	0	0	0
T23	2287	0	0	0
T24	5477	0	0	0
T29	4229	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T102	7966	0	0	0
T143	0	3	0	0
T144	0	5	0	0
T145	0	5	0	0
T146	0	1	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103187099	139	0	0
CgEnOn_A	103187099	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187099	139	0	0
T3	224707	0	0	0
T14	0	1	0	0
T18	779	3	0	0
T19	663	0	0	0
T20	560	0	0	0
T21	1151	0	0	0
T22	2097	0	0	0
T23	577	0	0	0
T24	1291	0	0	0
T29	981	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T67	0	1	0	0
T102	1899	0	0	0
T143	0	4	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187099	139	0	0
T3	224707	0	0	0
T14	0	1	0	0
T18	779	3	0	0
T19	663	0	0	0
T20	560	0	0	0
T21	1151	0	0	0
T22	2097	0	0	0
T23	577	0	0	0
T24	1291	0	0	0
T29	981	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T67	0	1	0	0
T102	1899	0	0	0
T143	0	4	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T35,T36
1	0	Covered	T7,T5,T8
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	206375244	7848	0	0
CgEnOn_A	206375244	5691	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206375244	7848	0	0
T1	213011	21	0	0
T2	339674	146	0	0
T4	22787	14	0	0
T5	26618	1	0	0
T6	35076	1	0	0
T7	5766	1	0	0
T8	795	1	0	0
T18	1558	4	0	0
T25	8397	1	0	0
T26	1176	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206375244	5691	0	0
T1	213011	16	0	0
T2	339674	135	0	0
T3	449414	14	0	0
T11	0	23	0	0
T12	0	37	0	0
T13	0	4	0	0
T18	1558	3	0	0
T19	1326	0	0	0
T20	1121	0	0	0
T21	2302	0	0	0
T22	4193	8	0	0
T23	1158	0	0	0
T24	2582	18	0	0
T35	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T35,T36
1	0	Covered	T7,T5,T8
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103187099	7782	0	0
CgEnOn_A	103187099	5625	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187099	7782	0	0
T1	106505	23	0	0
T2	169836	144	0	0
T4	11392	14	0	0
T5	13309	1	0	0
T6	17538	1	0	0
T7	2882	1	0	0
T8	397	1	0	0
T18	779	4	0	0
T25	4198	1	0	0
T26	587	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187099	5625	0	0
T1	106505	18	0	0
T2	169836	133	0	0
T3	224707	11	0	0
T11	0	20	0	0
T12	0	41	0	0
T13	0	4	0	0
T18	779	3	0	0
T19	663	0	0	0
T20	560	0	0	0
T21	1151	0	0	0
T22	2097	8	0	0
T23	577	0	0	0
T24	1291	16	0	0
T35	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T35,T36
1	0	Covered	T7,T5,T8
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	414335477	7824	0	0
CgEnOn_A	414335477	5657	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414335477	7824	0	0
T1	426291	21	0	0
T2	679511	141	0	0
T4	81115	14	0	0
T5	53288	1	0	0
T6	70190	1	0	0
T7	10345	1	0	0
T8	1669	2	0	0
T18	3236	4	0	0
T25	16072	1	0	0
T26	2209	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414335477	5657	0	0
T1	426291	16	0	0
T2	679511	130	0	0
T3	895599	12	0	0
T4	81115	0	0	0
T6	70190	0	0	0
T8	1669	1	0	0
T11	0	23	0	0
T12	0	39	0	0
T18	3236	3	0	0
T19	2560	0	0	0
T22	0	7	0	0
T24	0	15	0	0
T25	16072	0	0	0
T26	2209	0	0	0
T35	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T35,T36
1	0	Covered	T7,T5,T8
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	212543150	7836	0	0
CgEnOn_A	212543150	5668	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212543150	7836	0	0
T1	230435	19	0	0
T2	350428	148	0	0
T4	40559	14	0	0
T5	26645	1	0	0
T6	26456	1	0	0
T7	5173	1	0	0
T8	834	2	0	0
T18	1653	4	0	0
T25	8036	1	0	0
T26	1104	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212543150	5668	0	0
T1	230435	14	0	0
T2	350428	137	0	0
T3	502540	13	0	0
T4	40559	0	0	0
T6	26456	0	0	0
T8	834	1	0	0
T11	0	20	0	0
T12	0	38	0	0
T18	1653	3	0	0
T19	1280	0	0	0
T22	0	8	0	0
T24	0	17	0	0
T25	8036	0	0	0
T26	1104	0	0	0
T35	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	443009740	3951	0	0
CgEnOn_A	443009740	3949	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	3951	0	0
T1	486065	7	0	0
T2	729447	69	0	0
T3	106494	13	0	0
T4	84498	0	0	0
T6	79117	0	0	0
T8	1739	1	0	0
T18	3347	3	0	0
T19	2667	0	0	0
T25	16742	0	0	0
T26	2300	0	0	0
T29	0	5	0	0
T35	0	2	0	0
T79	0	6	0	0
T80	0	8	0	0
T102	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	3949	0	0
T1	486065	7	0	0
T2	729447	69	0	0
T3	106494	13	0	0
T4	84498	0	0	0
T6	79117	0	0	0
T8	1739	1	0	0
T18	3347	3	0	0
T19	2667	0	0	0
T25	16742	0	0	0
T26	2300	0	0	0
T29	0	5	0	0
T35	0	2	0	0
T79	0	6	0	0
T80	0	8	0	0
T102	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	443009740	3984	0	0
CgEnOn_A	443009740	3982	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	3984	0	0
T1	486065	5	0	0
T2	729447	74	0	0
T3	106494	10	0	0
T4	84498	0	0	0
T6	79117	0	0	0
T8	1739	1	0	0
T18	3347	3	0	0
T19	2667	0	0	0
T25	16742	0	0	0
T26	2300	0	0	0
T29	0	4	0	0
T35	0	2	0	0
T79	0	4	0	0
T80	0	6	0	0
T102	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	3982	0	0
T1	486065	5	0	0
T2	729447	74	0	0
T3	106494	10	0	0
T4	84498	0	0	0
T6	79117	0	0	0
T8	1739	1	0	0
T18	3347	3	0	0
T19	2667	0	0	0
T25	16742	0	0	0
T26	2300	0	0	0
T29	0	4	0	0
T35	0	2	0	0
T79	0	4	0	0
T80	0	6	0	0
T102	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	443009740	3925	0	0
CgEnOn_A	443009740	3923	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	3925	0	0
T1	486065	12	0	0
T2	729447	67	0	0
T3	106494	10	0	0
T4	84498	0	0	0
T6	79117	0	0	0
T8	1739	1	0	0
T18	3347	3	0	0
T19	2667	0	0	0
T25	16742	0	0	0
T26	2300	0	0	0
T29	0	7	0	0
T35	0	2	0	0
T79	0	4	0	0
T80	0	6	0	0
T102	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	3923	0	0
T1	486065	12	0	0
T2	729447	67	0	0
T3	106494	10	0	0
T4	84498	0	0	0
T6	79117	0	0	0
T8	1739	1	0	0
T18	3347	3	0	0
T19	2667	0	0	0
T25	16742	0	0	0
T26	2300	0	0	0
T29	0	7	0	0
T35	0	2	0	0
T79	0	4	0	0
T80	0	6	0	0
T102	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	443009740	3938	0	0
CgEnOn_A	443009740	3936	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	3938	0	0
T1	486065	13	0	0
T2	729447	78	0	0
T3	106494	11	0	0
T4	84498	0	0	0
T6	79117	0	0	0
T8	1739	1	0	0
T18	3347	3	0	0
T19	2667	0	0	0
T25	16742	0	0	0
T26	2300	0	0	0
T29	0	7	0	0
T35	0	2	0	0
T79	0	5	0	0
T80	0	6	0	0
T102	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443009740	3936	0	0
T1	486065	13	0	0
T2	729447	78	0	0
T3	106494	11	0	0
T4	84498	0	0	0
T6	79117	0	0	0
T8	1739	1	0	0
T18	3347	3	0	0
T19	2667	0	0	0
T25	16742	0	0	0
T26	2300	0	0	0
T29	0	7	0	0
T35	0	2	0	0
T79	0	5	0	0
T80	0	6	0	0
T102	0	5	0	0