Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T25

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T2
1	0	Covered	T18,T35,T36
1	1	Covered	T7,T8,T25

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	936442687	14496	0	0
GateOpen_A	936442687	14496	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	936442687	14496	0	0
T1	976244	38	0	0
T2	1539450	329	0	0
T3	2072262	30	0	0
T4	155857	0	0	0
T6	149262	0	0	0
T8	3698	4	0	0
T11	0	40	0	0
T12	0	118	0	0
T18	7227	12	0	0
T19	5829	0	0	0
T22	0	14	0	0
T24	0	41	0	0
T25	36706	0	0	0
T26	5078	0	0	0
T35	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	936442687	14496	0	0
T1	976244	38	0	0
T2	1539450	329	0	0
T3	2072262	30	0	0
T4	155857	0	0	0
T6	149262	0	0	0
T8	3698	4	0	0
T11	0	40	0	0
T12	0	118	0	0
T18	7227	12	0	0
T19	5829	0	0	0
T22	0	14	0	0
T24	0	41	0	0
T25	36706	0	0	0
T26	5078	0	0	0
T35	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T25

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T2
1	0	Covered	T18,T35,T36
1	1	Covered	T7,T8,T25

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	103187515	3598	0	0
GateOpen_A	103187515	3598	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187515	3598	0	0
T1	106506	9	0	0
T2	169836	78	0	0
T3	224708	7	0	0
T4	11393	0	0	0
T6	17538	0	0	0
T8	398	1	0	0
T11	0	10	0	0
T12	0	31	0	0
T18	779	3	0	0
T19	663	0	0	0
T22	0	4	0	0
T24	0	11	0	0
T25	4198	0	0	0
T26	588	0	0	0
T35	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103187515	3598	0	0
T1	106506	9	0	0
T2	169836	78	0	0
T3	224708	7	0	0
T4	11393	0	0	0
T6	17538	0	0	0
T8	398	1	0	0
T11	0	10	0	0
T12	0	31	0	0
T18	779	3	0	0
T19	663	0	0	0
T22	0	4	0	0
T24	0	11	0	0
T25	4198	0	0	0
T26	588	0	0	0
T35	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T25

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T2
1	0	Covered	T18,T35,T36
1	1	Covered	T7,T8,T25

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	206375672	3659	0	0
GateOpen_A	206375672	3659	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206375672	3659	0	0
T1	213011	8	0	0
T2	339675	85	0	0
T3	449414	8	0	0
T4	22788	0	0	0
T6	35076	0	0	0
T8	795	1	0	0
T11	0	11	0	0
T12	0	31	0	0
T18	1558	3	0	0
T19	1326	0	0	0
T22	0	4	0	0
T24	0	11	0	0
T25	8398	0	0	0
T26	1177	0	0	0
T35	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206375672	3659	0	0
T1	213011	8	0	0
T2	339675	85	0	0
T3	449414	8	0	0
T4	22788	0	0	0
T6	35076	0	0	0
T8	795	1	0	0
T11	0	11	0	0
T12	0	31	0	0
T18	1558	3	0	0
T19	1326	0	0	0
T22	0	4	0	0
T24	0	11	0	0
T25	8398	0	0	0
T26	1177	0	0	0
T35	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T25

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T2
1	0	Covered	T18,T35,T36
1	1	Covered	T7,T8,T25

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	414335922	3608	0	0
GateOpen_A	414335922	3608	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414335922	3608	0	0
T1	426291	11	0	0
T2	679511	81	0	0
T3	895600	7	0	0
T4	81116	0	0	0
T6	70191	0	0	0
T8	1670	1	0	0
T11	0	10	0	0
T12	0	26	0	0
T18	3237	3	0	0
T19	2560	0	0	0
T22	0	3	0	0
T24	0	9	0	0
T25	16073	0	0	0
T26	2209	0	0	0
T35	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414335922	3608	0	0
T1	426291	11	0	0
T2	679511	81	0	0
T3	895600	7	0	0
T4	81116	0	0	0
T6	70191	0	0	0
T8	1670	1	0	0
T11	0	10	0	0
T12	0	26	0	0
T18	3237	3	0	0
T19	2560	0	0	0
T22	0	3	0	0
T24	0	9	0	0
T25	16073	0	0	0
T26	2209	0	0	0
T35	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T25

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T2
1	0	Covered	T18,T35,T36
1	1	Covered	T7,T8,T25

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	212543578	3631	0	0
GateOpen_A	212543578	3631	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212543578	3631	0	0
T1	230436	10	0	0
T2	350428	85	0	0
T3	502540	8	0	0
T4	40560	0	0	0
T6	26457	0	0	0
T8	835	1	0	0
T11	0	9	0	0
T12	0	30	0	0
T18	1653	3	0	0
T19	1280	0	0	0
T22	0	3	0	0
T24	0	10	0	0
T25	8037	0	0	0
T26	1104	0	0	0
T35	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212543578	3631	0	0
T1	230436	10	0	0
T2	350428	85	0	0
T3	502540	8	0	0
T4	40560	0	0	0
T6	26457	0	0	0
T8	835	1	0	0
T11	0	9	0	0
T12	0	30	0	0
T18	1653	3	0	0
T19	1280	0	0	0
T22	0	3	0	0
T24	0	10	0	0
T25	8037	0	0	0
T26	1104	0	0	0
T35	0	2	0	0