Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

Total test records in report: 1010

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1215627826			Mar 12 01:01:09 PM PDT 24	Mar 12 01:01:10 PM PDT 24	12183319 ps
T1002	/workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2572266619			Mar 12 01:00:51 PM PDT 24	Mar 12 01:00:53 PM PDT 24	81261449 ps
T1003	/workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.125326049			Mar 12 01:00:50 PM PDT 24	Mar 12 01:00:52 PM PDT 24	18666528 ps
T1004	/workspace/coverage/cover_reg_top/40.clkmgr_intr_test.1337994596			Mar 12 01:01:14 PM PDT 24	Mar 12 01:01:15 PM PDT 24	14984927 ps
T1005	/workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1962320118			Mar 12 01:00:49 PM PDT 24	Mar 12 01:00:50 PM PDT 24	26927220 ps
T1006	/workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.550981911			Mar 12 01:00:55 PM PDT 24	Mar 12 01:00:56 PM PDT 24	59199752 ps
T1007	/workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3344776442			Mar 12 01:01:00 PM PDT 24	Mar 12 01:01:01 PM PDT 24	48356092 ps
T1008	/workspace/coverage/cover_reg_top/25.clkmgr_intr_test.68801183			Mar 12 01:00:58 PM PDT 24	Mar 12 01:01:04 PM PDT 24	30576049 ps
T1009	/workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3742481579			Mar 12 01:01:05 PM PDT 24	Mar 12 01:01:05 PM PDT 24	16559087 ps
T1010	/workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3861312704			Mar 12 01:00:41 PM PDT 24	Mar 12 01:00:51 PM PDT 24	995661875 ps

Test location	/workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.1082728742
Short name	T2
Test name
Test status
Simulation time	74204786483 ps
CPU time	812.87 seconds
Started	Mar 12 12:47:34 PM PDT 24
Finished	Mar 12 01:01:07 PM PDT 24
Peak memory	209440 kb
Host	smart-8710c9e1-7c44-4598-88b4-9a473e33c1dc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1082728742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1082728742
Directory	/workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all.1062443167
Short name	T12
Test name
Test status
Simulation time	6049228877 ps
CPU time	34.12 seconds
Started	Mar 12 12:46:48 PM PDT 24
Finished	Mar 12 12:47:22 PM PDT 24
Peak memory	201196 kb
Host	smart-14e1a5af-dd63-487b-891f-38dd8463d4ff
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062443167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.1062443167
Directory	/workspace/11.clkmgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2295460825
Short name	T58
Test name
Test status
Simulation time	267566349 ps
CPU time	2.87 seconds
Started	Mar 12 01:00:58 PM PDT 24
Finished	Mar 12 01:01:02 PM PDT 24
Peak memory	217840 kb
Host	smart-bdd59024-c097-4469-af6f-149bf243216a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295460825 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.2295460825
Directory	/workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/4.clkmgr_regwen.4177884258
Short name	T4
Test name
Test status
Simulation time	845006457 ps
CPU time	5.08 seconds
Started	Mar 12 12:46:31 PM PDT 24
Finished	Mar 12 12:46:37 PM PDT 24
Peak memory	201012 kb
Host	smart-1f9731c8-4c3d-4fe7-9ae6-853b4091738d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177884258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.4177884258
Directory	/workspace/4.clkmgr_regwen/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_status.1697394816
Short name	T18
Test name
Test status
Simulation time	36818928 ps
CPU time	0.77 seconds
Started	Mar 12 12:48:09 PM PDT 24
Finished	Mar 12 12:48:12 PM PDT 24
Peak memory	200768 kb
Host	smart-48a3ec94-fabe-416c-a775-057fe11aee25
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697394816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.1697394816
Directory	/workspace/38.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/0.clkmgr_sec_cm.3131769740
Short name	T40
Test name
Test status
Simulation time	156434523 ps
CPU time	1.99 seconds
Started	Mar 12 12:46:21 PM PDT 24
Finished	Mar 12 12:46:23 PM PDT 24
Peak memory	215704 kb
Host	smart-7eae41ba-9286-463b-af14-12b28f4945a8
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131769740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg r_sec_cm.3131769740
Directory	/workspace/0.clkmgr_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.471668088
Short name	T111
Test name
Test status
Simulation time	127752285 ps
CPU time	2.33 seconds
Started	Mar 12 01:00:59 PM PDT 24
Finished	Mar 12 01:01:02 PM PDT 24
Peak memory	201508 kb
Host	smart-4696dee1-fc15-49cc-8d35-927bee7fd287
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471668088 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 10.clkmgr_shadow_reg_errors.471668088
Directory	/workspace/10.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/13.clkmgr_idle_intersig_mubi.2627477946
Short name	T171
Test name
Test status
Simulation time	34718023 ps
CPU time	1.03 seconds
Started	Mar 12 12:47:02 PM PDT 24
Finished	Mar 12 12:47:04 PM PDT 24
Peak memory	200828 kb
Host	smart-d9a3f8ef-8094-43a8-9554-0f3a61ea3ed1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627477946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.2627477946
Directory	/workspace/13.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_alert_test.2432935398
Short name	T184
Test name
Test status
Simulation time	31340116 ps
CPU time	0.74 seconds
Started	Mar 12 12:47:03 PM PDT 24
Finished	Mar 12 12:47:04 PM PDT 24
Peak memory	200876 kb
Host	smart-58b688ce-4afb-462b-9528-9637ffa28a3c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432935398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk mgr_alert_test.2432935398
Directory	/workspace/12.clkmgr_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3004424317
Short name	T91
Test name
Test status
Simulation time	133208369 ps
CPU time	2.87 seconds
Started	Mar 12 01:00:43 PM PDT 24
Finished	Mar 12 01:00:46 PM PDT 24
Peak memory	201084 kb
Host	smart-942e83cf-40ce-44d8-99c2-0e8741ec1f1c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004424317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 2.clkmgr_tl_intg_err.3004424317
Directory	/workspace/2.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all.1802446207
Short name	T13
Test name
Test status
Simulation time	2038052471 ps
CPU time	9.66 seconds
Started	Mar 12 12:46:26 PM PDT 24
Finished	Mar 12 12:46:36 PM PDT 24
Peak memory	201084 kb
Host	smart-232ab988-a72f-4213-bb28-837aa2e797c3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802446207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.1802446207
Directory	/workspace/1.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.412821843
Short name	T157
Test name
Test status
Simulation time	49035238422 ps
CPU time	512.84 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:56:05 PM PDT 24
Peak memory	209532 kb
Host	smart-2100cdf9-0bdc-4946-8553-b088f63f3eac
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=412821843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.412821843
Directory	/workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.clkmgr_regwen.2562919724
Short name	T9
Test name
Test status
Simulation time	1209740138 ps
CPU time	7 seconds
Started	Mar 12 12:48:46 PM PDT 24
Finished	Mar 12 12:48:53 PM PDT 24
Peak memory	201032 kb
Host	smart-3f566fde-d354-41a0-9532-eb6ea50b8e64
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562919724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.2562919724
Directory	/workspace/49.clkmgr_regwen/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1100834313
Short name	T154
Test name
Test status
Simulation time	118503708 ps
CPU time	1.79 seconds
Started	Mar 12 01:01:28 PM PDT 24
Finished	Mar 12 01:01:31 PM PDT 24
Peak memory	201092 kb
Host	smart-b8a6c804-2060-4e77-8c07-74208f60fa12
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100834313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 13.clkmgr_tl_intg_err.1100834313
Directory	/workspace/13.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.2448497250
Short name	T83
Test name
Test status
Simulation time	22700977 ps
CPU time	0.86 seconds
Started	Mar 12 12:46:30 PM PDT 24
Finished	Mar 12 12:46:32 PM PDT 24
Peak memory	200728 kb
Host	smart-95564410-ff19-4065-a758-d12c9de34642
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448497250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.2448497250
Directory	/workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.3662269165
Short name	T59
Test name
Test status
Simulation time	154681283 ps
CPU time	1.4 seconds
Started	Mar 12 01:00:54 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	201308 kb
Host	smart-c86b30e2-08f2-4c44-8b29-a0792a003b6a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662269165 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.clkmgr_shadow_reg_errors.3662269165
Directory	/workspace/13.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.1589380216
Short name	T67
Test name
Test status
Simulation time	43198592434 ps
CPU time	607.26 seconds
Started	Mar 12 12:46:21 PM PDT 24
Finished	Mar 12 12:56:29 PM PDT 24
Peak memory	210604 kb
Host	smart-d7bfb729-f51d-4793-8e87-3f619a935318
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1589380216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.1589380216
Directory	/workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1968333453
Short name	T98
Test name
Test status
Simulation time	351977262 ps
CPU time	2.91 seconds
Started	Mar 12 01:00:46 PM PDT 24
Finished	Mar 12 01:00:49 PM PDT 24
Peak memory	201144 kb
Host	smart-b5363f9c-b943-46b4-a3cb-a27c14fba668
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968333453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 5.clkmgr_tl_intg_err.1968333453
Directory	/workspace/5.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3818899475
Short name	T119
Test name
Test status
Simulation time	961852521 ps
CPU time	4.28 seconds
Started	Mar 12 01:00:58 PM PDT 24
Finished	Mar 12 01:01:02 PM PDT 24
Peak memory	209412 kb
Host	smart-3f490de3-0490-460e-b02a-62632fa6b7f1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818899475 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.3818899475
Directory	/workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all.2648691372
Short name	T33
Test name
Test status
Simulation time	10036352630 ps
CPU time	50.58 seconds
Started	Mar 12 12:46:20 PM PDT 24
Finished	Mar 12 12:47:11 PM PDT 24
Peak memory	201124 kb
Host	smart-28416edb-e330-4b10-827c-606fa5fd2cb7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648691372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.2648691372
Directory	/workspace/0.clkmgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2199500515
Short name	T99
Test name
Test status
Simulation time	219851463 ps
CPU time	2.85 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	201120 kb
Host	smart-8892faa8-56bd-47a1-b2a5-0f1e13a756ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199500515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 10.clkmgr_tl_intg_err.2199500515
Directory	/workspace/10.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2021223440
Short name	T95
Test name
Test status
Simulation time	121806411 ps
CPU time	2.75 seconds
Started	Mar 12 01:00:41 PM PDT 24
Finished	Mar 12 01:00:44 PM PDT 24
Peak memory	201100 kb
Host	smart-9ee69dae-9ea6-46ba-af70-362e8799eea6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021223440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 3.clkmgr_tl_intg_err.2021223440
Directory	/workspace/3.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2618003706
Short name	T932
Test name
Test status
Simulation time	54664644 ps
CPU time	1.18 seconds
Started	Mar 12 01:00:48 PM PDT 24
Finished	Mar 12 01:00:49 PM PDT 24
Peak memory	200988 kb
Host	smart-326a5a81-0be8-407d-b277-504087499cfd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618003706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_aliasing.2618003706
Directory	/workspace/0.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3861312704
Short name	T1010
Test name
Test status
Simulation time	995661875 ps
CPU time	9.41 seconds
Started	Mar 12 01:00:41 PM PDT 24
Finished	Mar 12 01:00:51 PM PDT 24
Peak memory	201024 kb
Host	smart-36d9a4da-ca29-40f9-95b2-6b4fea21f10b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861312704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_bit_bash.3861312704
Directory	/workspace/0.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.2786370076
Short name	T907
Test name
Test status
Simulation time	30185373 ps
CPU time	0.87 seconds
Started	Mar 12 01:00:39 PM PDT 24
Finished	Mar 12 01:00:40 PM PDT 24
Peak memory	200896 kb
Host	smart-a42e1faf-1bc3-42bf-9d50-10c49800c3fe
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786370076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_hw_reset.2786370076
Directory	/workspace/0.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2397743135
Short name	T885
Test name
Test status
Simulation time	121675956 ps
CPU time	1.6 seconds
Started	Mar 12 01:00:49 PM PDT 24
Finished	Mar 12 01:00:50 PM PDT 24
Peak memory	209424 kb
Host	smart-102be61c-d619-4da6-81b3-97ff0b35c671
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397743135 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.2397743135
Directory	/workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1075400837
Short name	T943
Test name
Test status
Simulation time	25457754 ps
CPU time	0.78 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	200976 kb
Host	smart-3528cbe8-c8c0-4157-9b65-1828ee60ce37
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075400837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. clkmgr_csr_rw.1075400837
Directory	/workspace/0.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1823778656
Short name	T852
Test name
Test status
Simulation time	41205422 ps
CPU time	0.72 seconds
Started	Mar 12 01:00:51 PM PDT 24
Finished	Mar 12 01:00:52 PM PDT 24
Peak memory	199208 kb
Host	smart-7dea2b48-5fa8-4b0c-9c62-2165b67c1409
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823778656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk mgr_intr_test.1823778656
Directory	/workspace/0.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.4018246882
Short name	T982
Test name
Test status
Simulation time	107531414 ps
CPU time	1.13 seconds
Started	Mar 12 01:00:47 PM PDT 24
Finished	Mar 12 01:00:49 PM PDT 24
Peak memory	200852 kb
Host	smart-2d2cf78f-9a27-48cf-aabc-824c8cd12844
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018246882 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.clkmgr_same_csr_outstanding.4018246882
Directory	/workspace/0.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3438259387
Short name	T945
Test name
Test status
Simulation time	189900375 ps
CPU time	1.62 seconds
Started	Mar 12 01:00:45 PM PDT 24
Finished	Mar 12 01:00:47 PM PDT 24
Peak memory	201316 kb
Host	smart-32cabbe2-c19f-4f08-a742-1913e780fe32
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438259387 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.clkmgr_shadow_reg_errors.3438259387
Directory	/workspace/0.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.148308953
Short name	T53
Test name
Test status
Simulation time	138189409 ps
CPU time	2.93 seconds
Started	Mar 12 01:00:38 PM PDT 24
Finished	Mar 12 01:00:41 PM PDT 24
Peak memory	209676 kb
Host	smart-c8a3b9b3-e2d2-494e-8ef0-e876c65c13c2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148308953 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.148308953
Directory	/workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.3650995835
Short name	T939
Test name
Test status
Simulation time	270336943 ps
CPU time	2.75 seconds
Started	Mar 12 01:00:49 PM PDT 24
Finished	Mar 12 01:00:51 PM PDT 24
Peak memory	201176 kb
Host	smart-2c7165d5-3ed4-4a47-87c2-1dd7c5ad57d7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650995835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk mgr_tl_errors.3650995835
Directory	/workspace/0.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1664570881
Short name	T970
Test name
Test status
Simulation time	57249349 ps
CPU time	1.56 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:51 PM PDT 24
Peak memory	201144 kb
Host	smart-ffd05e90-4029-4235-9574-43c90fa4a1ce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664570881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 0.clkmgr_tl_intg_err.1664570881
Directory	/workspace/0.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.561782680
Short name	T977
Test name
Test status
Simulation time	149517831 ps
CPU time	1.56 seconds
Started	Mar 12 01:00:46 PM PDT 24
Finished	Mar 12 01:00:48 PM PDT 24
Peak memory	200824 kb
Host	smart-42d5ed0a-67f3-47e7-8761-21d78b434162
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561782680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 1.clkmgr_csr_aliasing.561782680
Directory	/workspace/1.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.200112908
Short name	T974
Test name
Test status
Simulation time	705387451 ps
CPU time	7.04 seconds
Started	Mar 12 01:00:49 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	200984 kb
Host	smart-ec20de1a-6f27-42c1-8f4b-e0289f527b55
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200112908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 1.clkmgr_csr_bit_bash.200112908
Directory	/workspace/1.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2492007244
Short name	T881
Test name
Test status
Simulation time	27078009 ps
CPU time	0.78 seconds
Started	Mar 12 01:00:40 PM PDT 24
Finished	Mar 12 01:00:41 PM PDT 24
Peak memory	200800 kb
Host	smart-9ba7aec9-26dd-4a62-9788-ed4f0ba64a5b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492007244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_hw_reset.2492007244
Directory	/workspace/1.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.701431091
Short name	T97
Test name
Test status
Simulation time	515295236 ps
CPU time	3.15 seconds
Started	Mar 12 01:00:49 PM PDT 24
Finished	Mar 12 01:00:52 PM PDT 24
Peak memory	210124 kb
Host	smart-a1d12842-228a-4a3e-8de7-1bec83ba8db9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701431091 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.701431091
Directory	/workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.913607217
Short name	T966
Test name
Test status
Simulation time	22781919 ps
CPU time	0.93 seconds
Started	Mar 12 01:00:42 PM PDT 24
Finished	Mar 12 01:00:43 PM PDT 24
Peak memory	200924 kb
Host	smart-5170b297-638e-49c3-a0f8-c45834c715a4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913607217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.c lkmgr_csr_rw.913607217
Directory	/workspace/1.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3562842870
Short name	T988
Test name
Test status
Simulation time	24358405 ps
CPU time	0.68 seconds
Started	Mar 12 01:00:34 PM PDT 24
Finished	Mar 12 01:00:40 PM PDT 24
Peak memory	199276 kb
Host	smart-34fbdf5e-b448-4c28-97b8-20e8e44b1f39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562842870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_intr_test.3562842870
Directory	/workspace/1.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3429569153
Short name	T883
Test name
Test status
Simulation time	54889720 ps
CPU time	0.98 seconds
Started	Mar 12 01:00:33 PM PDT 24
Finished	Mar 12 01:00:34 PM PDT 24
Peak memory	200948 kb
Host	smart-58953ebd-0960-49c3-b9f0-f2e50c60431b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429569153 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.clkmgr_same_csr_outstanding.3429569153
Directory	/workspace/1.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.4118194489
Short name	T64
Test name
Test status
Simulation time	64684265 ps
CPU time	1.41 seconds
Started	Mar 12 01:00:43 PM PDT 24
Finished	Mar 12 01:00:44 PM PDT 24
Peak memory	201360 kb
Host	smart-8c4bce9f-81bb-4382-9911-29c0c972726f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118194489 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 1.clkmgr_shadow_reg_errors.4118194489
Directory	/workspace/1.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2838169253
Short name	T924
Test name
Test status
Simulation time	56993874 ps
CPU time	1.63 seconds
Started	Mar 12 01:00:42 PM PDT 24
Finished	Mar 12 01:00:44 PM PDT 24
Peak memory	201096 kb
Host	smart-295129d7-2511-4693-8317-1dae7d97b649
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838169253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_tl_errors.2838169253
Directory	/workspace/1.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1296427924
Short name	T964
Test name
Test status
Simulation time	111265972 ps
CPU time	1.75 seconds
Started	Mar 12 01:00:47 PM PDT 24
Finished	Mar 12 01:00:49 PM PDT 24
Peak memory	201192 kb
Host	smart-af676c03-c3f9-412f-9301-2f6104721047
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296427924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 1.clkmgr_tl_intg_err.1296427924
Directory	/workspace/1.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3137663978
Short name	T989
Test name
Test status
Simulation time	59676032 ps
CPU time	1.06 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	201012 kb
Host	smart-5fa19420-ea93-4b0c-934f-e833fa599cca
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137663978 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.3137663978
Directory	/workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2308740344
Short name	T880
Test name
Test status
Simulation time	18697331 ps
CPU time	0.79 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	200960 kb
Host	smart-4db6c55f-69f7-49ef-8003-02ac6addbe0e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308740344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .clkmgr_csr_rw.2308740344
Directory	/workspace/10.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2535143754
Short name	T952
Test name
Test status
Simulation time	15793431 ps
CPU time	0.65 seconds
Started	Mar 12 01:01:03 PM PDT 24
Finished	Mar 12 01:01:04 PM PDT 24
Peak memory	199352 kb
Host	smart-80c5d20b-a673-4f77-9936-5ea7a3c940fd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535143754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl kmgr_intr_test.2535143754
Directory	/workspace/10.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3853890726
Short name	T995
Test name
Test status
Simulation time	104088919 ps
CPU time	1.54 seconds
Started	Mar 12 01:00:49 PM PDT 24
Finished	Mar 12 01:00:51 PM PDT 24
Peak memory	200896 kb
Host	smart-f7fc7958-bf76-4347-9db9-c44e8eebe61d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853890726 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.clkmgr_same_csr_outstanding.3853890726
Directory	/workspace/10.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.106219995
Short name	T935
Test name
Test status
Simulation time	110642947 ps
CPU time	2.04 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	201540 kb
Host	smart-f17af036-f37d-433c-b22b-82afc4077d56
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106219995 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.106219995
Directory	/workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1935599270
Short name	T886
Test name
Test status
Simulation time	111846313 ps
CPU time	1.8 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	201176 kb
Host	smart-1f2929ce-2065-409d-874c-e278115d8ed8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935599270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl kmgr_tl_errors.1935599270
Directory	/workspace/10.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3883884494
Short name	T878
Test name
Test status
Simulation time	18747103 ps
CPU time	0.97 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:51 PM PDT 24
Peak memory	201024 kb
Host	smart-b8e9de34-ae22-4898-a1e0-390d3aaca504
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883884494 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.3883884494
Directory	/workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3509956641
Short name	T857
Test name
Test status
Simulation time	50205441 ps
CPU time	0.82 seconds
Started	Mar 12 01:00:49 PM PDT 24
Finished	Mar 12 01:00:50 PM PDT 24
Peak memory	200964 kb
Host	smart-8183cdab-9b83-4555-b8fb-760d672737c0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509956641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .clkmgr_csr_rw.3509956641
Directory	/workspace/11.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_intr_test.880487751
Short name	T929
Test name
Test status
Simulation time	30280839 ps
CPU time	0.74 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	199360 kb
Host	smart-63641e95-a4ff-4029-aeb5-0f9dc74c5c53
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880487751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clk mgr_intr_test.880487751
Directory	/workspace/11.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3567838238
Short name	T986
Test name
Test status
Simulation time	93746944 ps
CPU time	1.39 seconds
Started	Mar 12 01:00:53 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	201124 kb
Host	smart-5321e307-3392-4746-9e66-48b957f882ae
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567838238 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.clkmgr_same_csr_outstanding.3567838238
Directory	/workspace/11.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.888010732
Short name	T60
Test name
Test status
Simulation time	67129979 ps
CPU time	1.44 seconds
Started	Mar 12 01:00:47 PM PDT 24
Finished	Mar 12 01:00:49 PM PDT 24
Peak memory	201324 kb
Host	smart-27f702de-ec8a-4b55-a644-8b9bd882e820
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888010732 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 11.clkmgr_shadow_reg_errors.888010732
Directory	/workspace/11.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2102907540
Short name	T57
Test name
Test status
Simulation time	65129727 ps
CPU time	1.62 seconds
Started	Mar 12 01:00:53 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	209712 kb
Host	smart-08cccb1c-d4db-4812-bb72-c8363406ebaa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102907540 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.2102907540
Directory	/workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.3282055331
Short name	T950
Test name
Test status
Simulation time	49254136 ps
CPU time	1.44 seconds
Started	Mar 12 01:00:54 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	200940 kb
Host	smart-116aa58f-7b7c-4cbb-9aa5-c2e36f3dcba1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282055331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl kmgr_tl_errors.3282055331
Directory	/workspace/11.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.826843417
Short name	T153
Test name
Test status
Simulation time	227502457 ps
CPU time	2.12 seconds
Started	Mar 12 01:00:51 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	201156 kb
Host	smart-f7f22f79-802c-4ee9-8f12-47dd2fefd9b8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826843417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.clkmgr_tl_intg_err.826843417
Directory	/workspace/11.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3653914251
Short name	T914
Test name
Test status
Simulation time	37868964 ps
CPU time	1.88 seconds
Started	Mar 12 01:00:51 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	201232 kb
Host	smart-d57fd99c-8194-44c5-8ff7-7c276b00e891
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653914251 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.3653914251
Directory	/workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3247136600
Short name	T854
Test name
Test status
Simulation time	27040256 ps
CPU time	0.8 seconds
Started	Mar 12 01:01:14 PM PDT 24
Finished	Mar 12 01:01:15 PM PDT 24
Peak memory	200948 kb
Host	smart-e39920e3-fb20-407b-b4b7-b80b33c38bee
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247136600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .clkmgr_csr_rw.3247136600
Directory	/workspace/12.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3387097160
Short name	T906
Test name
Test status
Simulation time	79959321 ps
CPU time	0.78 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:50 PM PDT 24
Peak memory	199396 kb
Host	smart-12b08eb2-ba70-4db0-ad4f-038c2ff5b322
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387097160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_intr_test.3387097160
Directory	/workspace/12.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2495668285
Short name	T74
Test name
Test status
Simulation time	62127742 ps
CPU time	1.29 seconds
Started	Mar 12 01:00:51 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	201136 kb
Host	smart-efee806f-b08d-4cf3-a471-0288e2cee0f8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495668285 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 12.clkmgr_same_csr_outstanding.2495668285
Directory	/workspace/12.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2045622001
Short name	T54
Test name
Test status
Simulation time	124278942 ps
CPU time	1.36 seconds
Started	Mar 12 01:01:07 PM PDT 24
Finished	Mar 12 01:01:09 PM PDT 24
Peak memory	201320 kb
Host	smart-48f44188-e92a-4390-82aa-9a8274d166c6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045622001 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 12.clkmgr_shadow_reg_errors.2045622001
Directory	/workspace/12.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.2762677801
Short name	T116
Test name
Test status
Simulation time	236897417 ps
CPU time	2.15 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	201536 kb
Host	smart-adae020a-11be-4581-b10b-b2a8db7d1a86
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762677801 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.2762677801
Directory	/workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1348246479
Short name	T979
Test name
Test status
Simulation time	499177737 ps
CPU time	3.13 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	201160 kb
Host	smart-b292497d-9c10-4d4a-9848-cfb64bd7a304
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348246479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_tl_errors.1348246479
Directory	/workspace/12.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1068796105
Short name	T155
Test name
Test status
Simulation time	70026499 ps
CPU time	1.73 seconds
Started	Mar 12 01:00:54 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	201148 kb
Host	smart-e47657ae-e6fe-43d8-a14e-40f6294860cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068796105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 12.clkmgr_tl_intg_err.1068796105
Directory	/workspace/12.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.550981911
Short name	T1006
Test name
Test status
Simulation time	59199752 ps
CPU time	1.18 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	201060 kb
Host	smart-e2cad68c-e27f-490e-b870-0a87dbd62933
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550981911 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.550981911
Directory	/workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1448166959
Short name	T948
Test name
Test status
Simulation time	30607055 ps
CPU time	0.84 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	200928 kb
Host	smart-88780b0e-ae05-4091-957b-7680de529255
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448166959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .clkmgr_csr_rw.1448166959
Directory	/workspace/13.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_intr_test.3913147124
Short name	T875
Test name
Test status
Simulation time	17227342 ps
CPU time	0.64 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	199180 kb
Host	smart-a8aa73de-6d8a-41bd-b0c6-59032b320a94
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913147124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl kmgr_intr_test.3913147124
Directory	/workspace/13.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3329275761
Short name	T963
Test name
Test status
Simulation time	39351188 ps
CPU time	1.23 seconds
Started	Mar 12 01:00:59 PM PDT 24
Finished	Mar 12 01:01:00 PM PDT 24
Peak memory	201132 kb
Host	smart-520d5b16-d18b-4764-ac4d-36d6e78d8203
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329275761 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.clkmgr_same_csr_outstanding.3329275761
Directory	/workspace/13.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2431983822
Short name	T52
Test name
Test status
Simulation time	375216867 ps
CPU time	3.37 seconds
Started	Mar 12 01:01:00 PM PDT 24
Finished	Mar 12 01:01:03 PM PDT 24
Peak memory	201576 kb
Host	smart-8c15ae8b-685f-476c-b4c2-862c8c67d2ff
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431983822 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.2431983822
Directory	/workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.2668738960
Short name	T915
Test name
Test status
Simulation time	46516969 ps
CPU time	1.48 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	201128 kb
Host	smart-f634a20d-4779-4470-abe1-d6465c16311d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668738960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl kmgr_tl_errors.2668738960
Directory	/workspace/13.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.675519265
Short name	T958
Test name
Test status
Simulation time	40125145 ps
CPU time	1.83 seconds
Started	Mar 12 01:01:14 PM PDT 24
Finished	Mar 12 01:01:16 PM PDT 24
Peak memory	210384 kb
Host	smart-162222ab-e633-4e0e-b0be-36a90f7d70fe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675519265 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.675519265
Directory	/workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1631757853
Short name	T892
Test name
Test status
Simulation time	18539960 ps
CPU time	0.81 seconds
Started	Mar 12 01:01:22 PM PDT 24
Finished	Mar 12 01:01:23 PM PDT 24
Peak memory	200920 kb
Host	smart-a268f34f-ed9c-4752-b1c0-5d12e0de1b84
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631757853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .clkmgr_csr_rw.1631757853
Directory	/workspace/14.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_intr_test.4098377035
Short name	T991
Test name
Test status
Simulation time	12090459 ps
CPU time	0.66 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	199220 kb
Host	smart-34301e81-901c-4d17-b37b-2895919e3057
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098377035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_intr_test.4098377035
Directory	/workspace/14.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2476305299
Short name	T916
Test name
Test status
Simulation time	50794029 ps
CPU time	0.94 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	201000 kb
Host	smart-fa9afef9-a2d7-4b01-ad77-5a8fe491f45f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476305299 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.clkmgr_same_csr_outstanding.2476305299
Directory	/workspace/14.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.75818037
Short name	T959
Test name
Test status
Simulation time	142647233 ps
CPU time	1.76 seconds
Started	Mar 12 01:01:32 PM PDT 24
Finished	Mar 12 01:01:35 PM PDT 24
Peak memory	201544 kb
Host	smart-c2436c1c-ecc5-41d9-a335-9463c76fd7b2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75818037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_ test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 14.clkmgr_shadow_reg_errors.75818037
Directory	/workspace/14.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.160068029
Short name	T975
Test name
Test status
Simulation time	87005903 ps
CPU time	1.81 seconds
Started	Mar 12 01:00:54 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	217512 kb
Host	smart-730d5ca5-8f85-4b60-a9b0-f3ff4fa1ce43
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160068029 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.160068029
Directory	/workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2413597070
Short name	T984
Test name
Test status
Simulation time	236178147 ps
CPU time	3.38 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:01:01 PM PDT 24
Peak memory	201072 kb
Host	smart-5075ae76-aa9b-4083-bab2-4a3404070402
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413597070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_tl_errors.2413597070
Directory	/workspace/14.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3093416470
Short name	T909
Test name
Test status
Simulation time	819331296 ps
CPU time	3.38 seconds
Started	Mar 12 01:01:05 PM PDT 24
Finished	Mar 12 01:01:08 PM PDT 24
Peak memory	201168 kb
Host	smart-724dd916-e7d9-40b5-891c-c6d078213035
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093416470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 14.clkmgr_tl_intg_err.3093416470
Directory	/workspace/14.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.799270565
Short name	T937
Test name
Test status
Simulation time	37067231 ps
CPU time	1.2 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:01:02 PM PDT 24
Peak memory	200868 kb
Host	smart-9714722d-ce54-4140-82d5-c546d1dd3b71
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799270565 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.799270565
Directory	/workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.982747682
Short name	T888
Test name
Test status
Simulation time	18454958 ps
CPU time	0.83 seconds
Started	Mar 12 01:00:58 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	200940 kb
Host	smart-34adda3a-cb99-4986-973f-2946c40532b7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982747682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. clkmgr_csr_rw.982747682
Directory	/workspace/15.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2210612684
Short name	T940
Test name
Test status
Simulation time	12131475 ps
CPU time	0.68 seconds
Started	Mar 12 01:01:06 PM PDT 24
Finished	Mar 12 01:01:06 PM PDT 24
Peak memory	199344 kb
Host	smart-cc0345ac-cfe8-42ee-8e01-649924655c1a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210612684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl kmgr_intr_test.2210612684
Directory	/workspace/15.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2031680020
Short name	T968
Test name
Test status
Simulation time	33202176 ps
CPU time	1.07 seconds
Started	Mar 12 01:00:58 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	200652 kb
Host	smart-589dca2c-ee4d-4d71-a397-b516f0ec8b00
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031680020 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.clkmgr_same_csr_outstanding.2031680020
Directory	/workspace/15.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3719522715
Short name	T938
Test name
Test status
Simulation time	187890141 ps
CPU time	1.96 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:01:07 PM PDT 24
Peak memory	201504 kb
Host	smart-94086b3c-ef44-4325-8100-223527bb3fbc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719522715 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.clkmgr_shadow_reg_errors.3719522715
Directory	/workspace/15.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3540584849
Short name	T110
Test name
Test status
Simulation time	119514830 ps
CPU time	1.91 seconds
Started	Mar 12 01:00:59 PM PDT 24
Finished	Mar 12 01:01:01 PM PDT 24
Peak memory	201520 kb
Host	smart-e85694a1-b1e1-4823-b6a1-422973f9bc93
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540584849 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.3540584849
Directory	/workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.336297896
Short name	T998
Test name
Test status
Simulation time	75318672 ps
CPU time	1.52 seconds
Started	Mar 12 01:00:54 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	201128 kb
Host	smart-c3160bd5-fa8d-4103-8a38-6705f8cd3db2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336297896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clk mgr_tl_errors.336297896
Directory	/workspace/15.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.470225068
Short name	T152
Test name
Test status
Simulation time	113622264 ps
CPU time	1.76 seconds
Started	Mar 12 01:00:59 PM PDT 24
Finished	Mar 12 01:01:01 PM PDT 24
Peak memory	201120 kb
Host	smart-915dfa1c-f913-4390-a555-3e16168c2d37
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470225068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 15.clkmgr_tl_intg_err.470225068
Directory	/workspace/15.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3852916335
Short name	T949
Test name
Test status
Simulation time	137532284 ps
CPU time	1.49 seconds
Started	Mar 12 01:01:05 PM PDT 24
Finished	Mar 12 01:01:12 PM PDT 24
Peak memory	200944 kb
Host	smart-b8115142-39b2-4864-a904-e02c38bc2139
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852916335 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.3852916335
Directory	/workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3344776442
Short name	T1007
Test name
Test status
Simulation time	48356092 ps
CPU time	0.8 seconds
Started	Mar 12 01:01:00 PM PDT 24
Finished	Mar 12 01:01:01 PM PDT 24
Peak memory	200928 kb
Host	smart-a7df76d8-bb18-403b-89e6-d7972cc951b2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344776442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .clkmgr_csr_rw.3344776442
Directory	/workspace/16.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2229285981
Short name	T904
Test name
Test status
Simulation time	17942783 ps
CPU time	0.66 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	199332 kb
Host	smart-11cba189-bcf2-478c-b9ea-ee9fc98483bc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229285981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl kmgr_intr_test.2229285981
Directory	/workspace/16.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1726332551
Short name	T920
Test name
Test status
Simulation time	147957000 ps
CPU time	1.6 seconds
Started	Mar 12 01:00:58 PM PDT 24
Finished	Mar 12 01:01:00 PM PDT 24
Peak memory	201136 kb
Host	smart-d2901fab-e5e8-4fcb-8b5d-5318f0005694
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726332551 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.clkmgr_same_csr_outstanding.1726332551
Directory	/workspace/16.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2282722226
Short name	T121
Test name
Test status
Simulation time	57575914 ps
CPU time	1.27 seconds
Started	Mar 12 01:00:54 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	201260 kb
Host	smart-763fb593-241e-4a2b-9dd7-dd7d9f58c03f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282722226 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 16.clkmgr_shadow_reg_errors.2282722226
Directory	/workspace/16.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.405219056
Short name	T62
Test name
Test status
Simulation time	112063305 ps
CPU time	2.61 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	209740 kb
Host	smart-7ce0610e-48cd-48e5-aece-faf701041db1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405219056 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.405219056
Directory	/workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1159144580
Short name	T896
Test name
Test status
Simulation time	54276557 ps
CPU time	1.66 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:54 PM PDT 24
Peak memory	201048 kb
Host	smart-55b0564c-4718-4f4c-b0bd-80deca3eaef3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159144580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl kmgr_tl_errors.1159144580
Directory	/workspace/16.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1060834192
Short name	T92
Test name
Test status
Simulation time	56481555 ps
CPU time	1.61 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	201080 kb
Host	smart-fe704e05-6785-43b7-87b7-c7f121fc8a56
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060834192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 16.clkmgr_tl_intg_err.1060834192
Directory	/workspace/16.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3744305062
Short name	T999
Test name
Test status
Simulation time	26269680 ps
CPU time	1.37 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	200900 kb
Host	smart-92705887-ae1f-42ab-b2fb-34ff7eb382e9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744305062 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.3744305062
Directory	/workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.765350002
Short name	T869
Test name
Test status
Simulation time	44762361 ps
CPU time	0.86 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	200896 kb
Host	smart-797082b5-51ad-4e82-b0f3-ab5ce82a77a6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765350002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. clkmgr_csr_rw.765350002
Directory	/workspace/17.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3742481579
Short name	T1009
Test name
Test status
Simulation time	16559087 ps
CPU time	0.66 seconds
Started	Mar 12 01:01:05 PM PDT 24
Finished	Mar 12 01:01:05 PM PDT 24
Peak memory	199260 kb
Host	smart-8b10de75-18fc-475a-b7c3-8150a471e597
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742481579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl kmgr_intr_test.3742481579
Directory	/workspace/17.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3156943736
Short name	T882
Test name
Test status
Simulation time	156168336 ps
CPU time	1.3 seconds
Started	Mar 12 01:00:53 PM PDT 24
Finished	Mar 12 01:00:54 PM PDT 24
Peak memory	200904 kb
Host	smart-4a39f31c-f162-4600-ad1e-a83a25d0c8db
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156943736 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.clkmgr_same_csr_outstanding.3156943736
Directory	/workspace/17.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2922299155
Short name	T118
Test name
Test status
Simulation time	116988485 ps
CPU time	1.4 seconds
Started	Mar 12 01:00:54 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	201344 kb
Host	smart-2b079fc7-a975-463f-8119-5234e8ed7687
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922299155 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.clkmgr_shadow_reg_errors.2922299155
Directory	/workspace/17.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.1671798432
Short name	T876
Test name
Test status
Simulation time	40533636 ps
CPU time	2.31 seconds
Started	Mar 12 01:00:59 PM PDT 24
Finished	Mar 12 01:01:02 PM PDT 24
Peak memory	201108 kb
Host	smart-bbc26463-35cf-4f72-a374-1b50db7004a1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671798432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl kmgr_tl_errors.1671798432
Directory	/workspace/17.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1951641680
Short name	T93
Test name
Test status
Simulation time	120334603 ps
CPU time	2.53 seconds
Started	Mar 12 01:01:18 PM PDT 24
Finished	Mar 12 01:01:21 PM PDT 24
Peak memory	201140 kb
Host	smart-87dfcfa9-52d9-4521-9459-f0d5c634bf72
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951641680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 17.clkmgr_tl_intg_err.1951641680
Directory	/workspace/17.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1615212835
Short name	T860
Test name
Test status
Simulation time	30930703 ps
CPU time	1.49 seconds
Started	Mar 12 01:01:05 PM PDT 24
Finished	Mar 12 01:01:06 PM PDT 24
Peak memory	201152 kb
Host	smart-b6b3e937-192b-42d8-8a5d-af6da7f79749
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615212835 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.1615212835
Directory	/workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.418403092
Short name	T965
Test name
Test status
Simulation time	19177901 ps
CPU time	0.84 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:58 PM PDT 24
Peak memory	200960 kb
Host	smart-f20976e7-6d22-4768-813b-51791d6de93b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418403092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. clkmgr_csr_rw.418403092
Directory	/workspace/18.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_intr_test.644329650
Short name	T868
Test name
Test status
Simulation time	13121384 ps
CPU time	0.66 seconds
Started	Mar 12 01:01:20 PM PDT 24
Finished	Mar 12 01:01:22 PM PDT 24
Peak memory	199180 kb
Host	smart-a0b3b462-4cd6-4a47-8756-a6b70bda5548
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644329650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk mgr_intr_test.644329650
Directory	/workspace/18.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.47373933
Short name	T77
Test name
Test status
Simulation time	24925760 ps
CPU time	0.94 seconds
Started	Mar 12 01:01:04 PM PDT 24
Finished	Mar 12 01:01:10 PM PDT 24
Peak memory	200908 kb
Host	smart-7d5d765f-ca47-4af4-bb03-13cd57c09aa6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47373933 -assert nopostproc +UVM_TESTNAME=clkmgr_ba se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.clkmgr_same_csr_outstanding.47373933
Directory	/workspace/18.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.198881427
Short name	T951
Test name
Test status
Simulation time	148798262 ps
CPU time	1.29 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:58 PM PDT 24
Peak memory	201260 kb
Host	smart-ce2c22c7-c1b0-4f10-b294-10f2aea525c9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198881427 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 18.clkmgr_shadow_reg_errors.198881427
Directory	/workspace/18.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2848223196
Short name	T56
Test name
Test status
Simulation time	455811814 ps
CPU time	3.57 seconds
Started	Mar 12 01:00:58 PM PDT 24
Finished	Mar 12 01:01:02 PM PDT 24
Peak memory	201692 kb
Host	smart-bd71d410-b9aa-452b-bec3-910ca5fc7f80
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848223196 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.2848223196
Directory	/workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.183646892
Short name	T978
Test name
Test status
Simulation time	845809506 ps
CPU time	3.75 seconds
Started	Mar 12 01:00:51 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	200940 kb
Host	smart-bb5f4cdd-2edd-4236-87b1-b8da3cca3c9a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183646892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk mgr_tl_errors.183646892
Directory	/workspace/18.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2198242415
Short name	T901
Test name
Test status
Simulation time	182373552 ps
CPU time	1.84 seconds
Started	Mar 12 01:01:08 PM PDT 24
Finished	Mar 12 01:01:10 PM PDT 24
Peak memory	201112 kb
Host	smart-224f42e3-46cf-486a-8102-125ade9e9d66
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198242415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 18.clkmgr_tl_intg_err.2198242415
Directory	/workspace/18.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1336699784
Short name	T961
Test name
Test status
Simulation time	138810622 ps
CPU time	1.55 seconds
Started	Mar 12 01:01:26 PM PDT 24
Finished	Mar 12 01:01:28 PM PDT 24
Peak memory	200944 kb
Host	smart-a68e5ff5-9684-409f-8473-663e1f2ee68f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336699784 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.1336699784
Directory	/workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.2877089773
Short name	T912
Test name
Test status
Simulation time	34362945 ps
CPU time	0.87 seconds
Started	Mar 12 01:01:22 PM PDT 24
Finished	Mar 12 01:01:23 PM PDT 24
Peak memory	200956 kb
Host	smart-0b629d0f-d714-4a9f-a57b-b7f1fd93498a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877089773 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .clkmgr_csr_rw.2877089773
Directory	/workspace/19.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_intr_test.592911748
Short name	T913
Test name
Test status
Simulation time	12209945 ps
CPU time	0.63 seconds
Started	Mar 12 01:00:51 PM PDT 24
Finished	Mar 12 01:00:51 PM PDT 24
Peak memory	199316 kb
Host	smart-d2fb4db6-d631-4fac-abc6-b4a739a75999
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592911748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clk mgr_intr_test.592911748
Directory	/workspace/19.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1726198323
Short name	T990
Test name
Test status
Simulation time	200011810 ps
CPU time	1.46 seconds
Started	Mar 12 01:01:07 PM PDT 24
Finished	Mar 12 01:01:09 PM PDT 24
Peak memory	200900 kb
Host	smart-fc37746f-e65d-47f5-881d-64d580f8bc79
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726198323 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.clkmgr_same_csr_outstanding.1726198323
Directory	/workspace/19.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2872332268
Short name	T114
Test name
Test status
Simulation time	56195650 ps
CPU time	1.29 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	201320 kb
Host	smart-a485ff62-caae-4395-95bf-7cc05ad2d3de
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872332268 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 19.clkmgr_shadow_reg_errors.2872332268
Directory	/workspace/19.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.278938421
Short name	T887
Test name
Test status
Simulation time	76041858 ps
CPU time	1.7 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:58 PM PDT 24
Peak memory	217908 kb
Host	smart-c1127ef0-7ad8-4e83-9c0f-f1a7fe9d3da6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278938421 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.278938421
Directory	/workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.597292356
Short name	T863
Test name
Test status
Simulation time	26536107 ps
CPU time	1.67 seconds
Started	Mar 12 01:01:09 PM PDT 24
Finished	Mar 12 01:01:16 PM PDT 24
Peak memory	201156 kb
Host	smart-646b6bc4-4483-4bf4-a6fc-ef9e6ef88a6f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597292356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clk mgr_tl_errors.597292356
Directory	/workspace/19.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1416743184
Short name	T101
Test name
Test status
Simulation time	251318597 ps
CPU time	2.59 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	201092 kb
Host	smart-a9a38eb9-dcdf-4155-92cc-010240c58fed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416743184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 19.clkmgr_tl_intg_err.1416743184
Directory	/workspace/19.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1602973834
Short name	T870
Test name
Test status
Simulation time	483827152 ps
CPU time	2.28 seconds
Started	Mar 12 01:00:34 PM PDT 24
Finished	Mar 12 01:00:36 PM PDT 24
Peak memory	200916 kb
Host	smart-738bd735-d6d9-4437-b8f3-b22f867bfce6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602973834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_aliasing.1602973834
Directory	/workspace/2.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1281615015
Short name	T918
Test name
Test status
Simulation time	249233845 ps
CPU time	4.42 seconds
Started	Mar 12 01:00:43 PM PDT 24
Finished	Mar 12 01:00:48 PM PDT 24
Peak memory	201096 kb
Host	smart-dd3224b0-41af-4bb5-b6bc-3015d0b98a2d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281615015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_bit_bash.1281615015
Directory	/workspace/2.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3885652625
Short name	T855
Test name
Test status
Simulation time	54216936 ps
CPU time	0.85 seconds
Started	Mar 12 01:00:36 PM PDT 24
Finished	Mar 12 01:00:37 PM PDT 24
Peak memory	200928 kb
Host	smart-48e706f7-cd01-47d8-84a6-639c2b5db894
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885652625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_hw_reset.3885652625
Directory	/workspace/2.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.2362794074
Short name	T973
Test name
Test status
Simulation time	121708563 ps
CPU time	1.4 seconds
Started	Mar 12 01:00:42 PM PDT 24
Finished	Mar 12 01:00:44 PM PDT 24
Peak memory	200980 kb
Host	smart-443ef38a-3fbb-40fd-a63e-1ee66fa1989c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362794074 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.2362794074
Directory	/workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.4067682165
Short name	T981
Test name
Test status
Simulation time	21124293 ps
CPU time	0.88 seconds
Started	Mar 12 01:00:51 PM PDT 24
Finished	Mar 12 01:00:52 PM PDT 24
Peak memory	200960 kb
Host	smart-08160f87-24ed-4952-8bf6-75a91bef1a65
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067682165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. clkmgr_csr_rw.4067682165
Directory	/workspace/2.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_intr_test.4112276616
Short name	T941
Test name
Test status
Simulation time	32370624 ps
CPU time	0.74 seconds
Started	Mar 12 01:00:41 PM PDT 24
Finished	Mar 12 01:00:42 PM PDT 24
Peak memory	199224 kb
Host	smart-f181c16b-2c9c-4bbf-8a56-64ed02de9ff5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112276616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_intr_test.4112276616
Directory	/workspace/2.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.2632969658
Short name	T934
Test name
Test status
Simulation time	100199892 ps
CPU time	1.28 seconds
Started	Mar 12 01:00:41 PM PDT 24
Finished	Mar 12 01:00:42 PM PDT 24
Peak memory	200920 kb
Host	smart-1236a3d1-d900-4fe5-9e1d-ba97f6e500db
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632969658 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.clkmgr_same_csr_outstanding.2632969658
Directory	/workspace/2.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.3627173046
Short name	T947
Test name
Test status
Simulation time	99023452 ps
CPU time	1.81 seconds
Started	Mar 12 01:00:47 PM PDT 24
Finished	Mar 12 01:00:49 PM PDT 24
Peak memory	209632 kb
Host	smart-bb5a27e9-0de8-4344-8b16-fd643b852aea
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627173046 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.clkmgr_shadow_reg_errors.3627173046
Directory	/workspace/2.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1562357156
Short name	T930
Test name
Test status
Simulation time	210059989 ps
CPU time	2.56 seconds
Started	Mar 12 01:00:44 PM PDT 24
Finished	Mar 12 01:00:47 PM PDT 24
Peak memory	209716 kb
Host	smart-2fc5664f-5f2e-40ff-b81b-d1afd91c97d5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562357156 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.1562357156
Directory	/workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.4196328874
Short name	T917
Test name
Test status
Simulation time	51087559 ps
CPU time	3.02 seconds
Started	Mar 12 01:00:49 PM PDT 24
Finished	Mar 12 01:00:52 PM PDT 24
Peak memory	201116 kb
Host	smart-30005d79-2c42-4c43-b287-f7608ce97401
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196328874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_tl_errors.4196328874
Directory	/workspace/2.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.clkmgr_intr_test.1096539284
Short name	T866
Test name
Test status
Simulation time	25299332 ps
CPU time	0.67 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	199316 kb
Host	smart-f0994c1f-151c-406e-8796-2b8281ef62a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096539284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl kmgr_intr_test.1096539284
Directory	/workspace/20.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.clkmgr_intr_test.1171075124
Short name	T944
Test name
Test status
Simulation time	17252091 ps
CPU time	0.67 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	199376 kb
Host	smart-cc604db6-6dc1-423c-ad57-decfee8e630a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171075124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl kmgr_intr_test.1171075124
Directory	/workspace/21.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.clkmgr_intr_test.22973907
Short name	T992
Test name
Test status
Simulation time	39802635 ps
CPU time	0.7 seconds
Started	Mar 12 01:00:58 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	199308 kb
Host	smart-2c97f223-4051-4d01-bcfd-24ee900c2c07
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22973907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clkm gr_intr_test.22973907
Directory	/workspace/22.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3079798890
Short name	T853
Test name
Test status
Simulation time	140182473 ps
CPU time	0.95 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	199292 kb
Host	smart-e9e07540-f208-4f49-95fa-e352435bed43
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079798890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl kmgr_intr_test.3079798890
Directory	/workspace/23.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2639705383
Short name	T980
Test name
Test status
Simulation time	49833921 ps
CPU time	0.75 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	199356 kb
Host	smart-44d6ff38-840d-4a9a-8586-53787773b2f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639705383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl kmgr_intr_test.2639705383
Directory	/workspace/24.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.clkmgr_intr_test.68801183
Short name	T1008
Test name
Test status
Simulation time	30576049 ps
CPU time	0.67 seconds
Started	Mar 12 01:00:58 PM PDT 24
Finished	Mar 12 01:01:04 PM PDT 24
Peak memory	199308 kb
Host	smart-fd4e16ee-92ea-4d9d-b53e-353b072008ef
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68801183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clkm gr_intr_test.68801183
Directory	/workspace/25.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1852663008
Short name	T858
Test name
Test status
Simulation time	20810907 ps
CPU time	0.67 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	199280 kb
Host	smart-e167b353-f790-4515-948f-409f57865493
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852663008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl kmgr_intr_test.1852663008
Directory	/workspace/26.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2321413517
Short name	T879
Test name
Test status
Simulation time	15139599 ps
CPU time	0.67 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	199276 kb
Host	smart-14b7e371-3939-4ab7-9601-e52d3dbfd176
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321413517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl kmgr_intr_test.2321413517
Directory	/workspace/27.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2304173760
Short name	T893
Test name
Test status
Simulation time	24189573 ps
CPU time	0.66 seconds
Started	Mar 12 01:01:20 PM PDT 24
Finished	Mar 12 01:01:20 PM PDT 24
Peak memory	199328 kb
Host	smart-8bb37cd0-dacf-46a5-8bd0-63837fba581f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304173760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl kmgr_intr_test.2304173760
Directory	/workspace/28.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.clkmgr_intr_test.4010341444
Short name	T867
Test name
Test status
Simulation time	47663548 ps
CPU time	0.72 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:58 PM PDT 24
Peak memory	199288 kb
Host	smart-b569fb91-120c-4e49-9e96-7dbff8e16a0d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010341444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl kmgr_intr_test.4010341444
Directory	/workspace/29.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.2559275224
Short name	T78
Test name
Test status
Simulation time	30620407 ps
CPU time	1.42 seconds
Started	Mar 12 01:01:01 PM PDT 24
Finished	Mar 12 01:01:03 PM PDT 24
Peak memory	201132 kb
Host	smart-bc5b4488-e54e-47ba-babc-55a0be36fe57
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559275224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_aliasing.2559275224
Directory	/workspace/3.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2789019848
Short name	T936
Test name
Test status
Simulation time	265604088 ps
CPU time	6.7 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	201176 kb
Host	smart-2851ec04-0248-4bfe-9cdd-17f4fb8e1734
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789019848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_bit_bash.2789019848
Directory	/workspace/3.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.4171022111
Short name	T864
Test name
Test status
Simulation time	18942122 ps
CPU time	0.83 seconds
Started	Mar 12 01:00:40 PM PDT 24
Finished	Mar 12 01:00:41 PM PDT 24
Peak memory	200824 kb
Host	smart-2bba6e0f-b3f2-47ed-bf38-b04ced652341
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171022111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_hw_reset.4171022111
Directory	/workspace/3.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1339944475
Short name	T967
Test name
Test status
Simulation time	27519944 ps
CPU time	1.03 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	200964 kb
Host	smart-55e2b4e2-dc83-4ccf-9bb9-6e10f76bcd5b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339944475 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.1339944475
Directory	/workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.2260689239
Short name	T976
Test name
Test status
Simulation time	89745895 ps
CPU time	0.9 seconds
Started	Mar 12 01:00:41 PM PDT 24
Finished	Mar 12 01:00:42 PM PDT 24
Peak memory	200788 kb
Host	smart-1449e9bc-f050-4ed8-9f45-e9e213267402
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260689239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. clkmgr_csr_rw.2260689239
Directory	/workspace/3.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_intr_test.1176524060
Short name	T861
Test name
Test status
Simulation time	15812129 ps
CPU time	0.69 seconds
Started	Mar 12 01:00:43 PM PDT 24
Finished	Mar 12 01:00:44 PM PDT 24
Peak memory	199280 kb
Host	smart-a696317c-ac43-4ad6-a107-1ce839f9f12c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176524060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_intr_test.1176524060
Directory	/workspace/3.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.944168173
Short name	T76
Test name
Test status
Simulation time	61843928 ps
CPU time	1.47 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:52 PM PDT 24
Peak memory	201188 kb
Host	smart-836c9457-296a-4a56-ad2b-c5dbcba95482
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944168173 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 3.clkmgr_same_csr_outstanding.944168173
Directory	/workspace/3.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.1265566142
Short name	T120
Test name
Test status
Simulation time	124476558 ps
CPU time	1.56 seconds
Started	Mar 12 01:00:43 PM PDT 24
Finished	Mar 12 01:00:45 PM PDT 24
Peak memory	201340 kb
Host	smart-652753a7-4ed9-421d-8896-61fe66c28f51
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265566142 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.clkmgr_shadow_reg_errors.1265566142
Directory	/workspace/3.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.620048021
Short name	T115
Test name
Test status
Simulation time	124756210 ps
CPU time	1.89 seconds
Started	Mar 12 01:00:47 PM PDT 24
Finished	Mar 12 01:00:49 PM PDT 24
Peak memory	209768 kb
Host	smart-c4900611-71da-4f47-9628-9213bdc9af7c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620048021 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.620048021
Directory	/workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.513818168
Short name	T919
Test name
Test status
Simulation time	247027164 ps
CPU time	2.44 seconds
Started	Mar 12 01:00:48 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	201116 kb
Host	smart-6d88f369-3845-4c75-bb14-7c7b91476f1c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513818168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkm gr_tl_errors.513818168
Directory	/workspace/3.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2594844771
Short name	T891
Test name
Test status
Simulation time	20934327 ps
CPU time	0.69 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	199348 kb
Host	smart-d3733e73-be05-4673-b3e9-b4189db09ded
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594844771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl kmgr_intr_test.2594844771
Directory	/workspace/30.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.clkmgr_intr_test.2192772748
Short name	T946
Test name
Test status
Simulation time	11428596 ps
CPU time	0.65 seconds
Started	Mar 12 01:01:09 PM PDT 24
Finished	Mar 12 01:01:10 PM PDT 24
Peak memory	199272 kb
Host	smart-a33449c7-306c-4d6a-ba25-c706f777e360
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192772748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl kmgr_intr_test.2192772748
Directory	/workspace/31.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1357191669
Short name	T931
Test name
Test status
Simulation time	12981124 ps
CPU time	0.65 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	199288 kb
Host	smart-83479d9b-1b86-41b0-9d7c-fc0b356b6a69
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357191669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl kmgr_intr_test.1357191669
Directory	/workspace/32.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.clkmgr_intr_test.108709027
Short name	T994
Test name
Test status
Simulation time	19809854 ps
CPU time	0.65 seconds
Started	Mar 12 01:01:10 PM PDT 24
Finished	Mar 12 01:01:11 PM PDT 24
Peak memory	199284 kb
Host	smart-b86321f8-80c8-4841-a02c-eb9597d0d14d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108709027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clk mgr_intr_test.108709027
Directory	/workspace/33.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.clkmgr_intr_test.728640716
Short name	T942
Test name
Test status
Simulation time	11975983 ps
CPU time	0.64 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	199276 kb
Host	smart-cacba073-a223-4ff6-8700-8b51a1b5e00c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728640716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clk mgr_intr_test.728640716
Directory	/workspace/34.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.clkmgr_intr_test.702321244
Short name	T898
Test name
Test status
Simulation time	49206545 ps
CPU time	0.73 seconds
Started	Mar 12 01:01:00 PM PDT 24
Finished	Mar 12 01:01:01 PM PDT 24
Peak memory	199228 kb
Host	smart-70406251-0011-4ba5-b327-2c48cd835a64
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702321244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clk mgr_intr_test.702321244
Directory	/workspace/35.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.clkmgr_intr_test.3217429162
Short name	T953
Test name
Test status
Simulation time	33388134 ps
CPU time	0.68 seconds
Started	Mar 12 01:01:11 PM PDT 24
Finished	Mar 12 01:01:13 PM PDT 24
Peak memory	199288 kb
Host	smart-9e3562e6-12bc-4020-a116-e8060383b9ce
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217429162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl kmgr_intr_test.3217429162
Directory	/workspace/36.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.clkmgr_intr_test.3946743378
Short name	T910
Test name
Test status
Simulation time	13863752 ps
CPU time	0.68 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	199284 kb
Host	smart-5a65834f-78d5-4e29-bbdc-135ee4634ce2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946743378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl kmgr_intr_test.3946743378
Directory	/workspace/37.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1279675390
Short name	T872
Test name
Test status
Simulation time	33070699 ps
CPU time	0.67 seconds
Started	Mar 12 01:01:24 PM PDT 24
Finished	Mar 12 01:01:25 PM PDT 24
Peak memory	199328 kb
Host	smart-22a64e66-7cad-405d-90b0-04b2737cdee3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279675390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl kmgr_intr_test.1279675390
Directory	/workspace/38.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3318612112
Short name	T884
Test name
Test status
Simulation time	15644339 ps
CPU time	0.69 seconds
Started	Mar 12 01:00:59 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	199260 kb
Host	smart-59e48a7b-fb1b-4231-861b-919b4b01c787
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318612112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl kmgr_intr_test.3318612112
Directory	/workspace/39.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3366576858
Short name	T897
Test name
Test status
Simulation time	202983822 ps
CPU time	1.63 seconds
Started	Mar 12 01:00:53 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	200964 kb
Host	smart-f0d2b540-2112-4bbd-a634-7280c55a6d45
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366576858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_aliasing.3366576858
Directory	/workspace/4.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1295568914
Short name	T908
Test name
Test status
Simulation time	227118942 ps
CPU time	4.26 seconds
Started	Mar 12 01:00:54 PM PDT 24
Finished	Mar 12 01:01:03 PM PDT 24
Peak memory	201152 kb
Host	smart-e7aab5e2-ff4d-4393-99be-50b739073222
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295568914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_bit_bash.1295568914
Directory	/workspace/4.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.3800307867
Short name	T927
Test name
Test status
Simulation time	20262317 ps
CPU time	0.84 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	200964 kb
Host	smart-c9e8cf12-038b-42e0-9019-ce847ba761ab
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800307867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_hw_reset.3800307867
Directory	/workspace/4.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.2382772459
Short name	T859
Test name
Test status
Simulation time	23160370 ps
CPU time	1.17 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	201032 kb
Host	smart-92a69a52-3b20-4901-ad74-c2f85b57fc0b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382772459 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.2382772459
Directory	/workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.1555754498
Short name	T926
Test name
Test status
Simulation time	24544887 ps
CPU time	0.81 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:51 PM PDT 24
Peak memory	200956 kb
Host	smart-285aa323-a42e-46e4-a040-3e13d839c49f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555754498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. clkmgr_csr_rw.1555754498
Directory	/workspace/4.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_intr_test.3885034899
Short name	T921
Test name
Test status
Simulation time	10528002 ps
CPU time	0.63 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	199340 kb
Host	smart-74114542-efef-4eb0-9099-1c6da10810b5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885034899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_intr_test.3885034899
Directory	/workspace/4.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.509527797
Short name	T889
Test name
Test status
Simulation time	102373880 ps
CPU time	1.22 seconds
Started	Mar 12 01:00:54 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	200880 kb
Host	smart-2a9d5119-f166-4e8c-adfe-5a84581111ce
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509527797 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.clkmgr_same_csr_outstanding.509527797
Directory	/workspace/4.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2069686173
Short name	T972
Test name
Test status
Simulation time	116311034 ps
CPU time	1.4 seconds
Started	Mar 12 01:00:53 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	201284 kb
Host	smart-84139e21-e048-4974-bcb5-1fedf406b12c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069686173 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 4.clkmgr_shadow_reg_errors.2069686173
Directory	/workspace/4.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2113494369
Short name	T962
Test name
Test status
Simulation time	47246567 ps
CPU time	1.49 seconds
Started	Mar 12 01:00:54 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	201560 kb
Host	smart-0fe9be87-b0b8-428d-aad7-ed6f95290fe8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113494369 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.2113494369
Directory	/workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2328834291
Short name	T899
Test name
Test status
Simulation time	136791317 ps
CPU time	2.44 seconds
Started	Mar 12 01:00:47 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	200996 kb
Host	smart-aca2c701-86b0-4da4-b665-e2a2754b2c45
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328834291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_tl_errors.2328834291
Directory	/workspace/4.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2376214852
Short name	T925
Test name
Test status
Simulation time	74650083 ps
CPU time	1.6 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	201108 kb
Host	smart-aa9735ca-dfea-4e42-b5bb-a852d60ffb01
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376214852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 4.clkmgr_tl_intg_err.2376214852
Directory	/workspace/4.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.clkmgr_intr_test.1337994596
Short name	T1004
Test name
Test status
Simulation time	14984927 ps
CPU time	0.7 seconds
Started	Mar 12 01:01:14 PM PDT 24
Finished	Mar 12 01:01:15 PM PDT 24
Peak memory	199312 kb
Host	smart-21cc1ed6-5cd4-45f9-8699-6cc5b3ffe87e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337994596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl kmgr_intr_test.1337994596
Directory	/workspace/40.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.clkmgr_intr_test.990714131
Short name	T954
Test name
Test status
Simulation time	19586815 ps
CPU time	0.67 seconds
Started	Mar 12 01:00:59 PM PDT 24
Finished	Mar 12 01:01:00 PM PDT 24
Peak memory	199324 kb
Host	smart-6cc968fb-a1c0-445c-b6d4-2edd59e1338c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990714131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clk mgr_intr_test.990714131
Directory	/workspace/41.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.clkmgr_intr_test.487601170
Short name	T996
Test name
Test status
Simulation time	22997915 ps
CPU time	0.69 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:58 PM PDT 24
Peak memory	199292 kb
Host	smart-fe83bffc-c44d-48fd-80c6-c0caccb3427a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487601170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clk mgr_intr_test.487601170
Directory	/workspace/42.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1050928392
Short name	T865
Test name
Test status
Simulation time	16100688 ps
CPU time	0.65 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	199380 kb
Host	smart-584d67ef-7b8e-41ad-9e88-b4b768ee0c0b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050928392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl kmgr_intr_test.1050928392
Directory	/workspace/43.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1679383297
Short name	T873
Test name
Test status
Simulation time	19688460 ps
CPU time	0.67 seconds
Started	Mar 12 01:01:13 PM PDT 24
Finished	Mar 12 01:01:14 PM PDT 24
Peak memory	199380 kb
Host	smart-0543e6b4-300e-48d0-a773-af8dc43b682b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679383297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl kmgr_intr_test.1679383297
Directory	/workspace/44.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1215627826
Short name	T1001
Test name
Test status
Simulation time	12183319 ps
CPU time	0.65 seconds
Started	Mar 12 01:01:09 PM PDT 24
Finished	Mar 12 01:01:10 PM PDT 24
Peak memory	199324 kb
Host	smart-1c4b9538-64e5-4d3c-82a5-8c8318435a3d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215627826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl kmgr_intr_test.1215627826
Directory	/workspace/45.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.clkmgr_intr_test.3048649412
Short name	T969
Test name
Test status
Simulation time	12444542 ps
CPU time	0.7 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:58 PM PDT 24
Peak memory	199320 kb
Host	smart-ca1c542f-94c0-4f82-ad66-42bf1cabf800
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048649412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl kmgr_intr_test.3048649412
Directory	/workspace/46.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.clkmgr_intr_test.1916513190
Short name	T903
Test name
Test status
Simulation time	19903059 ps
CPU time	0.7 seconds
Started	Mar 12 01:01:09 PM PDT 24
Finished	Mar 12 01:01:10 PM PDT 24
Peak memory	199380 kb
Host	smart-3a0cea16-3860-400d-b0e5-fbeaa43e29a1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916513190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl kmgr_intr_test.1916513190
Directory	/workspace/47.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1563815597
Short name	T871
Test name
Test status
Simulation time	67653444 ps
CPU time	0.77 seconds
Started	Mar 12 01:01:14 PM PDT 24
Finished	Mar 12 01:01:15 PM PDT 24
Peak memory	199348 kb
Host	smart-38b4df9a-cc13-4e6b-bb00-c93bbc83f515
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563815597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl kmgr_intr_test.1563815597
Directory	/workspace/48.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2754884953
Short name	T955
Test name
Test status
Simulation time	34164509 ps
CPU time	0.7 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	199300 kb
Host	smart-2453d6a1-85e3-47dd-8f89-9d57014788f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754884953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl kmgr_intr_test.2754884953
Directory	/workspace/49.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1962320118
Short name	T1005
Test name
Test status
Simulation time	26927220 ps
CPU time	0.94 seconds
Started	Mar 12 01:00:49 PM PDT 24
Finished	Mar 12 01:00:50 PM PDT 24
Peak memory	200996 kb
Host	smart-24f62994-458a-4002-abdb-9fef2cc8c253
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962320118 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.1962320118
Directory	/workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.3545809987
Short name	T96
Test name
Test status
Simulation time	26461860 ps
CPU time	0.77 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	200932 kb
Host	smart-7fda0115-98fa-4050-aab1-1e54d65ad295
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545809987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. clkmgr_csr_rw.3545809987
Directory	/workspace/5.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_intr_test.657080922
Short name	T890
Test name
Test status
Simulation time	14912563 ps
CPU time	0.67 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	199332 kb
Host	smart-073c126b-2d13-4dc3-a97f-af637d46a8d2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657080922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm gr_intr_test.657080922
Directory	/workspace/5.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.4260541079
Short name	T874
Test name
Test status
Simulation time	25499782 ps
CPU time	1.01 seconds
Started	Mar 12 01:00:47 PM PDT 24
Finished	Mar 12 01:00:48 PM PDT 24
Peak memory	200848 kb
Host	smart-50320e5e-97f5-4f38-8684-b3d7d150e072
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260541079 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.clkmgr_same_csr_outstanding.4260541079
Directory	/workspace/5.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.3076216249
Short name	T55
Test name
Test status
Simulation time	76491003 ps
CPU time	1.29 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:58 PM PDT 24
Peak memory	201316 kb
Host	smart-42caeb2b-49bd-40a4-b6ba-1e5a819b6c93
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076216249 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.clkmgr_shadow_reg_errors.3076216249
Directory	/workspace/5.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.1658199137
Short name	T65
Test name
Test status
Simulation time	139837538 ps
CPU time	2.14 seconds
Started	Mar 12 01:00:47 PM PDT 24
Finished	Mar 12 01:00:49 PM PDT 24
Peak memory	201488 kb
Host	smart-158f90ca-0a98-4023-aaea-49eebc405b3c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658199137 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.1658199137
Directory	/workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.561368256
Short name	T923
Test name
Test status
Simulation time	228356053 ps
CPU time	3.41 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	201120 kb
Host	smart-a0cabcdc-f7c5-413a-b47c-c71d5d852d95
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561368256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm gr_tl_errors.561368256
Directory	/workspace/5.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.125326049
Short name	T1003
Test name
Test status
Simulation time	18666528 ps
CPU time	1.04 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:52 PM PDT 24
Peak memory	200944 kb
Host	smart-409dcf6b-3363-4370-b926-af0c4d6d7ef6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125326049 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.125326049
Directory	/workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.3572101852
Short name	T905
Test name
Test status
Simulation time	14321335 ps
CPU time	0.73 seconds
Started	Mar 12 01:00:51 PM PDT 24
Finished	Mar 12 01:00:51 PM PDT 24
Peak memory	200936 kb
Host	smart-2af07c4b-c235-49e9-a936-5d1974da4457
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572101852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. clkmgr_csr_rw.3572101852
Directory	/workspace/6.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_intr_test.837827584
Short name	T993
Test name
Test status
Simulation time	11328428 ps
CPU time	0.64 seconds
Started	Mar 12 01:00:54 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	199312 kb
Host	smart-d9be3426-daa0-42e9-8d26-ece0e11fb9d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837827584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkm gr_intr_test.837827584
Directory	/workspace/6.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.3582222685
Short name	T922
Test name
Test status
Simulation time	270131746 ps
CPU time	1.48 seconds
Started	Mar 12 01:00:53 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	200964 kb
Host	smart-09c60d03-3cf2-467b-a37d-3c07899828ba
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582222685 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.clkmgr_same_csr_outstanding.3582222685
Directory	/workspace/6.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2235269151
Short name	T112
Test name
Test status
Simulation time	162331860 ps
CPU time	1.43 seconds
Started	Mar 12 01:00:52 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	201260 kb
Host	smart-e78d1f4a-e564-4c58-9d76-328d75d244fb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235269151 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 6.clkmgr_shadow_reg_errors.2235269151
Directory	/workspace/6.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1245090741
Short name	T113
Test name
Test status
Simulation time	383714995 ps
CPU time	3.28 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:01:00 PM PDT 24
Peak memory	201836 kb
Host	smart-c7b297a6-7256-495a-a22b-26b25bb55e16
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245090741 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.1245090741
Directory	/workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.822438497
Short name	T877
Test name
Test status
Simulation time	189491866 ps
CPU time	3.14 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	201144 kb
Host	smart-755336e1-181a-46e3-bb42-d6534d38460a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822438497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkm gr_tl_errors.822438497
Directory	/workspace/6.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3492242338
Short name	T900
Test name
Test status
Simulation time	134432816 ps
CPU time	1.59 seconds
Started	Mar 12 01:00:49 PM PDT 24
Finished	Mar 12 01:00:51 PM PDT 24
Peak memory	200920 kb
Host	smart-f6b0b2ec-323e-482d-872c-3ebc8ca80626
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492242338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 6.clkmgr_tl_intg_err.3492242338
Directory	/workspace/6.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1328312678
Short name	T911
Test name
Test status
Simulation time	106435303 ps
CPU time	1.3 seconds
Started	Mar 12 01:00:49 PM PDT 24
Finished	Mar 12 01:00:50 PM PDT 24
Peak memory	201016 kb
Host	smart-fe7b61f4-53de-461e-899a-28073f27a9ca
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328312678 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.1328312678
Directory	/workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3180100865
Short name	T983
Test name
Test status
Simulation time	13656094 ps
CPU time	0.74 seconds
Started	Mar 12 01:00:53 PM PDT 24
Finished	Mar 12 01:00:54 PM PDT 24
Peak memory	200944 kb
Host	smart-5ee4c531-d3a1-4ee2-a593-cb9cc818db22
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180100865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. clkmgr_csr_rw.3180100865
Directory	/workspace/7.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1710767723
Short name	T1000
Test name
Test status
Simulation time	10939165 ps
CPU time	0.67 seconds
Started	Mar 12 01:00:56 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	199284 kb
Host	smart-3843b1ee-b227-44d3-8b63-72e922d0134c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710767723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk mgr_intr_test.1710767723
Directory	/workspace/7.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.157250512
Short name	T957
Test name
Test status
Simulation time	33065551 ps
CPU time	1.05 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	200924 kb
Host	smart-fd5fffd8-28cd-4374-90cf-250a8a036482
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157250512 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.clkmgr_same_csr_outstanding.157250512
Directory	/workspace/7.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.367165842
Short name	T51
Test name
Test status
Simulation time	74445600 ps
CPU time	1.4 seconds
Started	Mar 12 01:00:53 PM PDT 24
Finished	Mar 12 01:00:54 PM PDT 24
Peak memory	201312 kb
Host	smart-7cd690f0-0636-42ce-ac9b-76dc2a32fcff
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367165842 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 7.clkmgr_shadow_reg_errors.367165842
Directory	/workspace/7.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2518394094
Short name	T63
Test name
Test status
Simulation time	227671050 ps
CPU time	2.07 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:52 PM PDT 24
Peak memory	201516 kb
Host	smart-870d00fb-7e0f-491a-a54d-37babeedcd7b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518394094 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.2518394094
Directory	/workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.2195652419
Short name	T856
Test name
Test status
Simulation time	55745768 ps
CPU time	1.54 seconds
Started	Mar 12 01:00:53 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	201088 kb
Host	smart-21a9f731-66cd-4d34-a51f-7bebc1f1d91b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195652419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk mgr_tl_errors.2195652419
Directory	/workspace/7.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3489249403
Short name	T894
Test name
Test status
Simulation time	93825386 ps
CPU time	1.7 seconds
Started	Mar 12 01:01:02 PM PDT 24
Finished	Mar 12 01:01:04 PM PDT 24
Peak memory	201160 kb
Host	smart-ded3f3e9-3923-4e6e-bd63-eea14d559a58
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489249403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 7.clkmgr_tl_intg_err.3489249403
Directory	/workspace/7.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2572266619
Short name	T1002
Test name
Test status
Simulation time	81261449 ps
CPU time	1.19 seconds
Started	Mar 12 01:00:51 PM PDT 24
Finished	Mar 12 01:00:53 PM PDT 24
Peak memory	200820 kb
Host	smart-80dbfcbf-cd0c-43a6-b1f6-51493dbfccba
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572266619 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.2572266619
Directory	/workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.2779404037
Short name	T985
Test name
Test status
Simulation time	16886618 ps
CPU time	0.8 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:51 PM PDT 24
Peak memory	200908 kb
Host	smart-d92bf2a0-6d68-44ec-bee2-60ddfdf19aed
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779404037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. clkmgr_csr_rw.2779404037
Directory	/workspace/8.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_intr_test.176010748
Short name	T960
Test name
Test status
Simulation time	11100654 ps
CPU time	0.62 seconds
Started	Mar 12 01:00:53 PM PDT 24
Finished	Mar 12 01:00:54 PM PDT 24
Peak memory	199200 kb
Host	smart-fbbe05de-2da1-43b5-8fd4-ce30a60ac19c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176010748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm gr_intr_test.176010748
Directory	/workspace/8.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.721357030
Short name	T75
Test name
Test status
Simulation time	50279531 ps
CPU time	1.28 seconds
Started	Mar 12 01:00:47 PM PDT 24
Finished	Mar 12 01:00:49 PM PDT 24
Peak memory	200956 kb
Host	smart-cb4dfcc2-f923-4de3-8473-0ee783445e6a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721357030 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.clkmgr_same_csr_outstanding.721357030
Directory	/workspace/8.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.3874489498
Short name	T987
Test name
Test status
Simulation time	275424603 ps
CPU time	2.07 seconds
Started	Mar 12 01:00:48 PM PDT 24
Finished	Mar 12 01:00:51 PM PDT 24
Peak memory	201536 kb
Host	smart-c7206e9e-4574-4736-8074-f50d90449944
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874489498 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 8.clkmgr_shadow_reg_errors.3874489498
Directory	/workspace/8.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3609648931
Short name	T61
Test name
Test status
Simulation time	142055736 ps
CPU time	1.96 seconds
Started	Mar 12 01:00:53 PM PDT 24
Finished	Mar 12 01:00:55 PM PDT 24
Peak memory	217772 kb
Host	smart-d7a7c437-c00e-4966-b874-60a2b1959286
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609648931 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.3609648931
Directory	/workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.634399905
Short name	T997
Test name
Test status
Simulation time	31894448 ps
CPU time	1.96 seconds
Started	Mar 12 01:01:03 PM PDT 24
Finished	Mar 12 01:01:05 PM PDT 24
Peak memory	201124 kb
Host	smart-ee931f95-d0ae-4afb-99e5-4bbba0924c8d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634399905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm gr_tl_errors.634399905
Directory	/workspace/8.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2546550294
Short name	T100
Test name
Test status
Simulation time	107394881 ps
CPU time	1.68 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:57 PM PDT 24
Peak memory	201144 kb
Host	smart-16a3f839-bab6-47c4-86f3-068960de6ea0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546550294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 8.clkmgr_tl_intg_err.2546550294
Directory	/workspace/8.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.4029630313
Short name	T862
Test name
Test status
Simulation time	97452050 ps
CPU time	1.54 seconds
Started	Mar 12 01:01:08 PM PDT 24
Finished	Mar 12 01:01:09 PM PDT 24
Peak memory	201244 kb
Host	smart-49b0623c-3496-4aa2-b35f-64c6a79f4f2e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029630313 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.4029630313
Directory	/workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.576344286
Short name	T933
Test name
Test status
Simulation time	16518478 ps
CPU time	0.77 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:51 PM PDT 24
Peak memory	200960 kb
Host	smart-14624ce3-276e-4dfd-8a28-d353709af63c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576344286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.c lkmgr_csr_rw.576344286
Directory	/workspace/9.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1052597751
Short name	T895
Test name
Test status
Simulation time	31649413 ps
CPU time	0.69 seconds
Started	Mar 12 01:00:51 PM PDT 24
Finished	Mar 12 01:00:52 PM PDT 24
Peak memory	199292 kb
Host	smart-d9d4a063-f610-4626-986f-8994f039a355
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052597751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk mgr_intr_test.1052597751
Directory	/workspace/9.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.2987905185
Short name	T956
Test name
Test status
Simulation time	94643315 ps
CPU time	1.46 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:58 PM PDT 24
Peak memory	201124 kb
Host	smart-38e0f2d2-2cd3-4677-8c41-f5436c69529d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987905185 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.clkmgr_same_csr_outstanding.2987905185
Directory	/workspace/9.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3502064689
Short name	T117
Test name
Test status
Simulation time	154077899 ps
CPU time	2.24 seconds
Started	Mar 12 01:00:50 PM PDT 24
Finished	Mar 12 01:00:52 PM PDT 24
Peak memory	217456 kb
Host	smart-a1cc8316-9ebf-410b-8f38-df7bd3f2b96b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502064689 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.clkmgr_shadow_reg_errors.3502064689
Directory	/workspace/9.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1146828214
Short name	T971
Test name
Test status
Simulation time	98911327 ps
CPU time	2.5 seconds
Started	Mar 12 01:01:23 PM PDT 24
Finished	Mar 12 01:01:27 PM PDT 24
Peak memory	201572 kb
Host	smart-81fd73ba-9454-4330-8aa8-fa06f193a102
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146828214 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.1146828214
Directory	/workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1185199295
Short name	T902
Test name
Test status
Simulation time	89109742 ps
CPU time	1.71 seconds
Started	Mar 12 01:00:55 PM PDT 24
Finished	Mar 12 01:00:56 PM PDT 24
Peak memory	201132 kb
Host	smart-ebfb0466-9261-4a21-8aed-aaf2705d790c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185199295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk mgr_tl_errors.1185199295
Directory	/workspace/9.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.703452857
Short name	T928
Test name
Test status
Simulation time	158139991 ps
CPU time	1.96 seconds
Started	Mar 12 01:00:57 PM PDT 24
Finished	Mar 12 01:00:59 PM PDT 24
Peak memory	201072 kb
Host	smart-52d5f776-f7f6-45ee-9481-e61eff2c3e30
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703452857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 9.clkmgr_tl_intg_err.703452857
Directory	/workspace/9.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/0.clkmgr_alert_test.483483744
Short name	T436
Test name
Test status
Simulation time	90282435 ps
CPU time	0.93 seconds
Started	Mar 12 12:46:21 PM PDT 24
Finished	Mar 12 12:46:22 PM PDT 24
Peak memory	200888 kb
Host	smart-838845dd-c639-4706-84f9-d6f6e7f7a944
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483483744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg r_alert_test.483483744
Directory	/workspace/0.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.3945754979
Short name	T142
Test name
Test status
Simulation time	89161335 ps
CPU time	1.07 seconds
Started	Mar 12 12:46:20 PM PDT 24
Finished	Mar 12 12:46:21 PM PDT 24
Peak memory	200568 kb
Host	smart-ec515b81-828b-4697-b3d3-64dd679e6d5b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945754979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.3945754979
Directory	/workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_status.1385216080
Short name	T143
Test name
Test status
Simulation time	14967348 ps
CPU time	0.74 seconds
Started	Mar 12 12:46:20 PM PDT 24
Finished	Mar 12 12:46:21 PM PDT 24
Peak memory	199780 kb
Host	smart-0eb7c3e6-98b7-4ed8-8cec-19656fde2145
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385216080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.1385216080
Directory	/workspace/0.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/0.clkmgr_div_intersig_mubi.2051300709
Short name	T815
Test name
Test status
Simulation time	253485027 ps
CPU time	1.5 seconds
Started	Mar 12 12:46:21 PM PDT 24
Finished	Mar 12 12:46:22 PM PDT 24
Peak memory	200716 kb
Host	smart-b593866c-039c-42ce-9f11-75768f9aaad6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051300709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.2051300709
Directory	/workspace/0.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_extclk.4287818707
Short name	T200
Test name
Test status
Simulation time	29440115 ps
CPU time	0.88 seconds
Started	Mar 12 12:46:22 PM PDT 24
Finished	Mar 12 12:46:24 PM PDT 24
Peak memory	200780 kb
Host	smart-fb1956a2-c358-4c06-9620-22c11e6575a1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287818707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.4287818707
Directory	/workspace/0.clkmgr_extclk/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency.3910449038
Short name	T469
Test name
Test status
Simulation time	1521823574 ps
CPU time	8.5 seconds
Started	Mar 12 12:46:28 PM PDT 24
Finished	Mar 12 12:46:36 PM PDT 24
Peak memory	200828 kb
Host	smart-bde059d1-5493-4d4b-8d4a-02bdb1062c67
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910449038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.3910449038
Directory	/workspace/0.clkmgr_frequency/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency_timeout.3563332933
Short name	T325
Test name
Test status
Simulation time	2189677000 ps
CPU time	12.16 seconds
Started	Mar 12 12:46:26 PM PDT 24
Finished	Mar 12 12:46:38 PM PDT 24
Peak memory	201112 kb
Host	smart-d3b104ee-ca9b-4003-8947-a39aa0945927
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563332933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti meout.3563332933
Directory	/workspace/0.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/0.clkmgr_idle_intersig_mubi.4162597362
Short name	T377
Test name
Test status
Simulation time	113523529 ps
CPU time	1.14 seconds
Started	Mar 12 12:46:20 PM PDT 24
Finished	Mar 12 12:46:21 PM PDT 24
Peak memory	200616 kb
Host	smart-830795df-49e6-4707-9bf8-1ff1d6e350d8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162597362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.4162597362
Directory	/workspace/0.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.611073938
Short name	T662
Test name
Test status
Simulation time	43489412 ps
CPU time	0.79 seconds
Started	Mar 12 12:46:20 PM PDT 24
Finished	Mar 12 12:46:21 PM PDT 24
Peak memory	200760 kb
Host	smart-31a7f4b6-45d1-4e7f-bf94-9f202b79de03
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611073938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.clkmgr_lc_clk_byp_req_intersig_mubi.611073938
Directory	/workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.3074494238
Short name	T450
Test name
Test status
Simulation time	21413656 ps
CPU time	0.81 seconds
Started	Mar 12 12:46:22 PM PDT 24
Finished	Mar 12 12:46:24 PM PDT 24
Peak memory	200816 kb
Host	smart-b728907a-5254-4399-a0a4-dbfde91fcda6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074494238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.clkmgr_lc_ctrl_intersig_mubi.3074494238
Directory	/workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_peri.1342343469
Short name	T22
Test name
Test status
Simulation time	88068163 ps
CPU time	0.96 seconds
Started	Mar 12 12:46:18 PM PDT 24
Finished	Mar 12 12:46:20 PM PDT 24
Peak memory	200688 kb
Host	smart-1e388643-6e7a-4810-b17f-d206c52fefdc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342343469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.1342343469
Directory	/workspace/0.clkmgr_peri/latest

Test location	/workspace/coverage/default/0.clkmgr_regwen.1312760410
Short name	T701
Test name
Test status
Simulation time	244459438 ps
CPU time	1.38 seconds
Started	Mar 12 12:46:28 PM PDT 24
Finished	Mar 12 12:46:29 PM PDT 24
Peak memory	200724 kb
Host	smart-68abe426-1b03-4d02-bde9-a9033cb04e80
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312760410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.1312760410
Directory	/workspace/0.clkmgr_regwen/latest

Test location	/workspace/coverage/default/0.clkmgr_smoke.2950983824
Short name	T625
Test name
Test status
Simulation time	28990189 ps
CPU time	0.88 seconds
Started	Mar 12 12:46:26 PM PDT 24
Finished	Mar 12 12:46:32 PM PDT 24
Peak memory	200804 kb
Host	smart-d0c0e5e1-96e4-4b75-a8fd-1a427ee745bb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950983824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.2950983824
Directory	/workspace/0.clkmgr_smoke/latest

Test location	/workspace/coverage/default/0.clkmgr_trans.2960196849
Short name	T346
Test name
Test status
Simulation time	32035121 ps
CPU time	0.93 seconds
Started	Mar 12 12:46:22 PM PDT 24
Finished	Mar 12 12:46:24 PM PDT 24
Peak memory	200808 kb
Host	smart-d282c412-3a07-45b8-8e90-ef27c64bf82f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960196849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.2960196849
Directory	/workspace/0.clkmgr_trans/latest

Test location	/workspace/coverage/default/1.clkmgr_alert_test.510914145
Short name	T729
Test name
Test status
Simulation time	95835953 ps
CPU time	0.96 seconds
Started	Mar 12 12:46:34 PM PDT 24
Finished	Mar 12 12:46:35 PM PDT 24
Peak memory	200840 kb
Host	smart-d66734c5-3816-4320-b856-62f44f9cec9d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510914145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg r_alert_test.510914145
Directory	/workspace/1.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.1791437316
Short name	T186
Test name
Test status
Simulation time	173447759 ps
CPU time	1.3 seconds
Started	Mar 12 12:46:23 PM PDT 24
Finished	Mar 12 12:46:24 PM PDT 24
Peak memory	200804 kb
Host	smart-7ce49e3c-c16d-4dde-b5b4-87beca6a70a9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791437316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.1791437316
Directory	/workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_status.1333790747
Short name	T478
Test name
Test status
Simulation time	41360120 ps
CPU time	0.76 seconds
Started	Mar 12 12:46:28 PM PDT 24
Finished	Mar 12 12:46:30 PM PDT 24
Peak memory	200716 kb
Host	smart-ff30253b-0217-400d-820d-504bcf231161
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333790747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.1333790747
Directory	/workspace/1.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/1.clkmgr_div_intersig_mubi.2572548102
Short name	T674
Test name
Test status
Simulation time	24830883 ps
CPU time	0.74 seconds
Started	Mar 12 12:46:28 PM PDT 24
Finished	Mar 12 12:46:29 PM PDT 24
Peak memory	200812 kb
Host	smart-af9b2445-5a24-4c2e-a051-8a2075a7fa4c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572548102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.2572548102
Directory	/workspace/1.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_extclk.1509563794
Short name	T7
Test name
Test status
Simulation time	107795638 ps
CPU time	1.13 seconds
Started	Mar 12 12:46:21 PM PDT 24
Finished	Mar 12 12:46:23 PM PDT 24
Peak memory	200772 kb
Host	smart-2d56dba7-cd7b-43f8-8f3f-c2194af89c56
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509563794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1509563794
Directory	/workspace/1.clkmgr_extclk/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency.1475239005
Short name	T483
Test name
Test status
Simulation time	1407391751 ps
CPU time	8.21 seconds
Started	Mar 12 12:46:26 PM PDT 24
Finished	Mar 12 12:46:34 PM PDT 24
Peak memory	200856 kb
Host	smart-f58ea084-0338-4313-8547-91c42fa068f5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475239005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.1475239005
Directory	/workspace/1.clkmgr_frequency/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency_timeout.2991689417
Short name	T182
Test name
Test status
Simulation time	769806472 ps
CPU time	3.56 seconds
Started	Mar 12 12:46:24 PM PDT 24
Finished	Mar 12 12:46:28 PM PDT 24
Peak memory	200848 kb
Host	smart-662e1963-c44b-46f9-9750-179f047c0427
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991689417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti meout.2991689417
Directory	/workspace/1.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/1.clkmgr_idle_intersig_mubi.124230148
Short name	T209
Test name
Test status
Simulation time	12764945 ps
CPU time	0.7 seconds
Started	Mar 12 12:46:27 PM PDT 24
Finished	Mar 12 12:46:28 PM PDT 24
Peak memory	200808 kb
Host	smart-0b60f68b-4be9-46bd-8910-f3a9efbfa546
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124230148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .clkmgr_idle_intersig_mubi.124230148
Directory	/workspace/1.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.4109577850
Short name	T555
Test name
Test status
Simulation time	33004188 ps
CPU time	0.75 seconds
Started	Mar 12 12:46:25 PM PDT 24
Finished	Mar 12 12:46:26 PM PDT 24
Peak memory	200804 kb
Host	smart-0f2c27c0-74f8-4cf4-b7e4-5521c18e80e3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109577850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_clk_byp_req_intersig_mubi.4109577850
Directory	/workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2350995514
Short name	T316
Test name
Test status
Simulation time	53790510 ps
CPU time	0.94 seconds
Started	Mar 12 12:46:24 PM PDT 24
Finished	Mar 12 12:46:26 PM PDT 24
Peak memory	200812 kb
Host	smart-f3f50fb0-4a0c-4d10-9fe7-374134cd7518
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350995514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_ctrl_intersig_mubi.2350995514
Directory	/workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_peri.3251531405
Short name	T259
Test name
Test status
Simulation time	37385141 ps
CPU time	0.79 seconds
Started	Mar 12 12:46:26 PM PDT 24
Finished	Mar 12 12:46:27 PM PDT 24
Peak memory	200708 kb
Host	smart-41038b05-a83a-45c9-883c-660288eed8aa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251531405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.3251531405
Directory	/workspace/1.clkmgr_peri/latest

Test location	/workspace/coverage/default/1.clkmgr_regwen.3447082277
Short name	T348
Test name
Test status
Simulation time	1035532461 ps
CPU time	3.97 seconds
Started	Mar 12 12:46:22 PM PDT 24
Finished	Mar 12 12:46:27 PM PDT 24
Peak memory	200976 kb
Host	smart-56e1b229-e0ba-4245-9b55-4fc86a2a80d7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447082277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.3447082277
Directory	/workspace/1.clkmgr_regwen/latest

Test location	/workspace/coverage/default/1.clkmgr_sec_cm.2326786934
Short name	T37
Test name
Test status
Simulation time	572455222 ps
CPU time	3.26 seconds
Started	Mar 12 12:46:23 PM PDT 24
Finished	Mar 12 12:46:27 PM PDT 24
Peak memory	215724 kb
Host	smart-4811021f-951b-482c-8abb-10017f467d40
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326786934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg r_sec_cm.2326786934
Directory	/workspace/1.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/1.clkmgr_smoke.2838673649
Short name	T122
Test name
Test status
Simulation time	24151194 ps
CPU time	0.88 seconds
Started	Mar 12 12:46:23 PM PDT 24
Finished	Mar 12 12:46:24 PM PDT 24
Peak memory	200868 kb
Host	smart-3dc77e16-6c9c-438a-b7a2-caf76f98a721
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838673649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.2838673649
Directory	/workspace/1.clkmgr_smoke/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.3368857109
Short name	T216
Test name
Test status
Simulation time	105806024035 ps
CPU time	921.26 seconds
Started	Mar 12 12:46:25 PM PDT 24
Finished	Mar 12 01:01:46 PM PDT 24
Peak memory	209524 kb
Host	smart-222d1271-e879-40c6-87df-ad4226fab24a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3368857109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.3368857109
Directory	/workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.clkmgr_trans.2840472965
Short name	T552
Test name
Test status
Simulation time	25296551 ps
CPU time	0.84 seconds
Started	Mar 12 12:46:21 PM PDT 24
Finished	Mar 12 12:46:23 PM PDT 24
Peak memory	200860 kb
Host	smart-f7df751e-ab07-4439-8f79-f3dcf47b09ca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840472965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.2840472965
Directory	/workspace/1.clkmgr_trans/latest

Test location	/workspace/coverage/default/10.clkmgr_alert_test.2647103946
Short name	T546
Test name
Test status
Simulation time	65655411 ps
CPU time	0.93 seconds
Started	Mar 12 12:46:51 PM PDT 24
Finished	Mar 12 12:46:52 PM PDT 24
Peak memory	200820 kb
Host	smart-1a97ef7e-1294-4a44-8b78-a964280194c7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647103946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk mgr_alert_test.2647103946
Directory	/workspace/10.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1545699088
Short name	T141
Test name
Test status
Simulation time	26202057 ps
CPU time	0.79 seconds
Started	Mar 12 12:46:50 PM PDT 24
Finished	Mar 12 12:46:51 PM PDT 24
Peak memory	200684 kb
Host	smart-3bacc17b-980f-4df1-b308-8ae8040bbd69
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545699088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.1545699088
Directory	/workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_status.3229175715
Short name	T639
Test name
Test status
Simulation time	41607354 ps
CPU time	0.77 seconds
Started	Mar 12 12:46:54 PM PDT 24
Finished	Mar 12 12:46:55 PM PDT 24
Peak memory	199704 kb
Host	smart-d3346fcd-6e5d-4d71-9d6e-e5d1e5d834c3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229175715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.3229175715
Directory	/workspace/10.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/10.clkmgr_div_intersig_mubi.3998618904
Short name	T226
Test name
Test status
Simulation time	34036619 ps
CPU time	0.76 seconds
Started	Mar 12 12:46:48 PM PDT 24
Finished	Mar 12 12:46:49 PM PDT 24
Peak memory	200676 kb
Host	smart-06e63802-72cf-4ac8-b4ab-f3bc0b0741df
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998618904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.3998618904
Directory	/workspace/10.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_extclk.1045667125
Short name	T509
Test name
Test status
Simulation time	41231712 ps
CPU time	0.81 seconds
Started	Mar 12 12:46:43 PM PDT 24
Finished	Mar 12 12:46:44 PM PDT 24
Peak memory	200732 kb
Host	smart-932a0ef8-6735-472b-a0be-52480d9d52ae
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045667125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.1045667125
Directory	/workspace/10.clkmgr_extclk/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency.3596741914
Short name	T432
Test name
Test status
Simulation time	2122877493 ps
CPU time	12.16 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:46:55 PM PDT 24
Peak memory	201004 kb
Host	smart-6b760a74-1ddf-4a0d-a923-fd573d5d4c9b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596741914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.3596741914
Directory	/workspace/10.clkmgr_frequency/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency_timeout.216767585
Short name	T758
Test name
Test status
Simulation time	261018942 ps
CPU time	2.28 seconds
Started	Mar 12 12:46:46 PM PDT 24
Finished	Mar 12 12:46:49 PM PDT 24
Peak memory	200772 kb
Host	smart-28e0328b-56f4-4523-8bb0-46d9d65f2bb6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216767585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_ti meout.216767585
Directory	/workspace/10.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/10.clkmgr_idle_intersig_mubi.1648817448
Short name	T615
Test name
Test status
Simulation time	30407169 ps
CPU time	0.89 seconds
Started	Mar 12 12:46:54 PM PDT 24
Finished	Mar 12 12:46:55 PM PDT 24
Peak memory	200776 kb
Host	smart-81745cf2-63ec-49a9-b816-180f7c9094a0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648817448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.1648817448
Directory	/workspace/10.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.1055901176
Short name	T599
Test name
Test status
Simulation time	49095202 ps
CPU time	0.84 seconds
Started	Mar 12 12:46:54 PM PDT 24
Finished	Mar 12 12:46:54 PM PDT 24
Peak memory	200808 kb
Host	smart-4d653c65-5722-4d00-a95f-5e203b833d28
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055901176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_clk_byp_req_intersig_mubi.1055901176
Directory	/workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.2384769754
Short name	T803
Test name
Test status
Simulation time	36254355 ps
CPU time	0.82 seconds
Started	Mar 12 12:46:51 PM PDT 24
Finished	Mar 12 12:46:52 PM PDT 24
Peak memory	200664 kb
Host	smart-3cb4e069-2345-4f7d-8ce9-eec0014ed2aa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384769754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_ctrl_intersig_mubi.2384769754
Directory	/workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_peri.505604515
Short name	T276
Test name
Test status
Simulation time	16011963 ps
CPU time	0.78 seconds
Started	Mar 12 12:46:44 PM PDT 24
Finished	Mar 12 12:46:46 PM PDT 24
Peak memory	200772 kb
Host	smart-ac2a476c-076d-4ce8-ba70-2c40e3d09eaa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505604515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.505604515
Directory	/workspace/10.clkmgr_peri/latest

Test location	/workspace/coverage/default/10.clkmgr_regwen.3653052400
Short name	T73
Test name
Test status
Simulation time	1084906796 ps
CPU time	6.38 seconds
Started	Mar 12 12:46:52 PM PDT 24
Finished	Mar 12 12:46:59 PM PDT 24
Peak memory	201044 kb
Host	smart-35cc5a0a-789b-4491-b73b-a12eae559db2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653052400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.3653052400
Directory	/workspace/10.clkmgr_regwen/latest

Test location	/workspace/coverage/default/10.clkmgr_smoke.843212836
Short name	T387
Test name
Test status
Simulation time	24065658 ps
CPU time	0.83 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:46:44 PM PDT 24
Peak memory	200788 kb
Host	smart-9b17b4bf-8b78-4cde-85e6-4e67470e34f3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843212836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.843212836
Directory	/workspace/10.clkmgr_smoke/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all.2695124921
Short name	T529
Test name
Test status
Simulation time	9811982711 ps
CPU time	74.73 seconds
Started	Mar 12 12:46:55 PM PDT 24
Finished	Mar 12 12:48:10 PM PDT 24
Peak memory	201188 kb
Host	smart-60e516e8-cfa6-4b97-a5e3-ecb90bb11ce3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695124921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.2695124921
Directory	/workspace/10.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.1533075696
Short name	T285
Test name
Test status
Simulation time	68028232022 ps
CPU time	467.11 seconds
Started	Mar 12 12:46:55 PM PDT 24
Finished	Mar 12 12:54:42 PM PDT 24
Peak memory	217668 kb
Host	smart-7ea720a6-f570-44a9-8c09-5e32a7cb9352
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1533075696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.1533075696
Directory	/workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.clkmgr_trans.2367102300
Short name	T250
Test name
Test status
Simulation time	201331519 ps
CPU time	1.41 seconds
Started	Mar 12 12:46:49 PM PDT 24
Finished	Mar 12 12:46:51 PM PDT 24
Peak memory	200836 kb
Host	smart-e2218ac4-3da9-4bbe-8295-e5d54a08ad43
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367102300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2367102300
Directory	/workspace/10.clkmgr_trans/latest

Test location	/workspace/coverage/default/11.clkmgr_alert_test.1251656342
Short name	T566
Test name
Test status
Simulation time	39059846 ps
CPU time	0.77 seconds
Started	Mar 12 12:46:50 PM PDT 24
Finished	Mar 12 12:46:50 PM PDT 24
Peak memory	200872 kb
Host	smart-b7945d74-340d-4203-a142-3ea134ab96b4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251656342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk mgr_alert_test.1251656342
Directory	/workspace/11.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2636126250
Short name	T547
Test name
Test status
Simulation time	21247868 ps
CPU time	0.74 seconds
Started	Mar 12 12:46:48 PM PDT 24
Finished	Mar 12 12:46:48 PM PDT 24
Peak memory	200704 kb
Host	smart-a0aaa077-fe5b-432b-9de4-1e7434e44841
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636126250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.2636126250
Directory	/workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_status.2882160548
Short name	T146
Test name
Test status
Simulation time	14895085 ps
CPU time	0.78 seconds
Started	Mar 12 12:46:49 PM PDT 24
Finished	Mar 12 12:46:50 PM PDT 24
Peak memory	199780 kb
Host	smart-bc1c7f52-6674-403c-b4af-eaf70e3d3afa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882160548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.2882160548
Directory	/workspace/11.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/11.clkmgr_div_intersig_mubi.3953692251
Short name	T579
Test name
Test status
Simulation time	28026338 ps
CPU time	0.93 seconds
Started	Mar 12 12:46:52 PM PDT 24
Finished	Mar 12 12:46:53 PM PDT 24
Peak memory	200788 kb
Host	smart-1d44c201-ca9e-4f1b-9480-1198ef4df4d8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953692251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.3953692251
Directory	/workspace/11.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_extclk.1200725961
Short name	T812
Test name
Test status
Simulation time	29424054 ps
CPU time	0.79 seconds
Started	Mar 12 12:46:51 PM PDT 24
Finished	Mar 12 12:46:52 PM PDT 24
Peak memory	200604 kb
Host	smart-e59f3d26-5196-40c2-8cdf-c5223f93a04c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200725961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.1200725961
Directory	/workspace/11.clkmgr_extclk/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency.74656292
Short name	T558
Test name
Test status
Simulation time	2371526067 ps
CPU time	13.2 seconds
Started	Mar 12 12:46:49 PM PDT 24
Finished	Mar 12 12:47:02 PM PDT 24
Peak memory	201072 kb
Host	smart-8a40083f-5d4b-4d80-8f7b-07baf6f0e54e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74656292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.74656292
Directory	/workspace/11.clkmgr_frequency/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency_timeout.716660911
Short name	T724
Test name
Test status
Simulation time	818036495 ps
CPU time	3.14 seconds
Started	Mar 12 12:46:54 PM PDT 24
Finished	Mar 12 12:46:57 PM PDT 24
Peak memory	200844 kb
Host	smart-12a3af60-a810-4496-818b-0043dc28df11
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716660911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_ti meout.716660911
Directory	/workspace/11.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/11.clkmgr_idle_intersig_mubi.22526771
Short name	T335
Test name
Test status
Simulation time	35012884 ps
CPU time	0.98 seconds
Started	Mar 12 12:46:53 PM PDT 24
Finished	Mar 12 12:46:54 PM PDT 24
Peak memory	200784 kb
Host	smart-9675a713-da28-45bc-bece-d1556c40ad19
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22526771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11 .clkmgr_idle_intersig_mubi.22526771
Directory	/workspace/11.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.3929807809
Short name	T768
Test name
Test status
Simulation time	64118913 ps
CPU time	0.85 seconds
Started	Mar 12 12:46:53 PM PDT 24
Finished	Mar 12 12:46:54 PM PDT 24
Peak memory	200700 kb
Host	smart-c743eba9-ef4f-4a9e-a1f5-9477eb875ed4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929807809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.clkmgr_lc_clk_byp_req_intersig_mubi.3929807809
Directory	/workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.812099001
Short name	T802
Test name
Test status
Simulation time	72212798 ps
CPU time	0.85 seconds
Started	Mar 12 12:46:55 PM PDT 24
Finished	Mar 12 12:46:56 PM PDT 24
Peak memory	200816 kb
Host	smart-eb24837d-0507-4a83-91cc-cffdb1b5bc53
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812099001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.clkmgr_lc_ctrl_intersig_mubi.812099001
Directory	/workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_peri.2217883709
Short name	T384
Test name
Test status
Simulation time	34289906 ps
CPU time	0.84 seconds
Started	Mar 12 12:46:49 PM PDT 24
Finished	Mar 12 12:46:50 PM PDT 24
Peak memory	200696 kb
Host	smart-ee01719b-a144-425f-b26b-06814ba3139e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217883709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.2217883709
Directory	/workspace/11.clkmgr_peri/latest

Test location	/workspace/coverage/default/11.clkmgr_regwen.1895489275
Short name	T41
Test name
Test status
Simulation time	192577624 ps
CPU time	1.25 seconds
Started	Mar 12 12:46:55 PM PDT 24
Finished	Mar 12 12:46:56 PM PDT 24
Peak memory	200824 kb
Host	smart-54bdb097-dc36-4740-84bf-b9b361025d5f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895489275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.1895489275
Directory	/workspace/11.clkmgr_regwen/latest

Test location	/workspace/coverage/default/11.clkmgr_smoke.4258239436
Short name	T403
Test name
Test status
Simulation time	23207822 ps
CPU time	0.83 seconds
Started	Mar 12 12:46:50 PM PDT 24
Finished	Mar 12 12:46:51 PM PDT 24
Peak memory	200824 kb
Host	smart-728715bf-6ac4-4311-a68e-1de4586509c0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258239436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.4258239436
Directory	/workspace/11.clkmgr_smoke/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.3006343247
Short name	T613
Test name
Test status
Simulation time	37394419286 ps
CPU time	391.38 seconds
Started	Mar 12 12:46:50 PM PDT 24
Finished	Mar 12 12:53:22 PM PDT 24
Peak memory	217544 kb
Host	smart-ff068a8a-3fb5-4eb6-aa3f-b7a847bf8a55
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3006343247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.3006343247
Directory	/workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.clkmgr_trans.2465590225
Short name	T636
Test name
Test status
Simulation time	19042512 ps
CPU time	0.7 seconds
Started	Mar 12 12:46:54 PM PDT 24
Finished	Mar 12 12:46:55 PM PDT 24
Peak memory	200840 kb
Host	smart-f4882c80-239e-4e1b-8988-841cb69714fa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465590225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.2465590225
Directory	/workspace/11.clkmgr_trans/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.2574569025
Short name	T479
Test name
Test status
Simulation time	16565618 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:02 PM PDT 24
Finished	Mar 12 12:47:03 PM PDT 24
Peak memory	200720 kb
Host	smart-3b2f9326-26b2-4a47-9254-c313bd510d32
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574569025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.2574569025
Directory	/workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_status.979357449
Short name	T785
Test name
Test status
Simulation time	15920988 ps
CPU time	0.67 seconds
Started	Mar 12 12:46:52 PM PDT 24
Finished	Mar 12 12:46:53 PM PDT 24
Peak memory	199736 kb
Host	smart-a304c09a-9402-4730-819b-63c67fce58e6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979357449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.979357449
Directory	/workspace/12.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/12.clkmgr_div_intersig_mubi.2080165755
Short name	T459
Test name
Test status
Simulation time	20689223 ps
CPU time	0.88 seconds
Started	Mar 12 12:47:01 PM PDT 24
Finished	Mar 12 12:47:02 PM PDT 24
Peak memory	200760 kb
Host	smart-ce8a2d8a-1a2a-4d05-bab1-6b75a012a1d5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080165755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.2080165755
Directory	/workspace/12.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_extclk.868173238
Short name	T183
Test name
Test status
Simulation time	20869924 ps
CPU time	0.81 seconds
Started	Mar 12 12:46:55 PM PDT 24
Finished	Mar 12 12:46:56 PM PDT 24
Peak memory	200780 kb
Host	smart-ea193642-6db5-49c0-bc52-337e240686da
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868173238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.868173238
Directory	/workspace/12.clkmgr_extclk/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency.2112605235
Short name	T598
Test name
Test status
Simulation time	1771244225 ps
CPU time	7.96 seconds
Started	Mar 12 12:46:54 PM PDT 24
Finished	Mar 12 12:47:03 PM PDT 24
Peak memory	200916 kb
Host	smart-87d07628-8af4-41c0-9fd4-52e90a0963c0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112605235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.2112605235
Directory	/workspace/12.clkmgr_frequency/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency_timeout.374499222
Short name	T596
Test name
Test status
Simulation time	1855331257 ps
CPU time	8.08 seconds
Started	Mar 12 12:46:59 PM PDT 24
Finished	Mar 12 12:47:08 PM PDT 24
Peak memory	200768 kb
Host	smart-91b31a5d-5e8c-4e3d-9e97-e422e0afdd6f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374499222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_ti meout.374499222
Directory	/workspace/12.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/12.clkmgr_idle_intersig_mubi.1583485237
Short name	T427
Test name
Test status
Simulation time	113181841 ps
CPU time	1.13 seconds
Started	Mar 12 12:47:00 PM PDT 24
Finished	Mar 12 12:47:01 PM PDT 24
Peak memory	200768 kb
Host	smart-623efd30-7506-4dd0-b896-1a8e6c82dd2f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583485237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.1583485237
Directory	/workspace/12.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.1147257939
Short name	T847
Test name
Test status
Simulation time	44870294 ps
CPU time	0.85 seconds
Started	Mar 12 12:47:00 PM PDT 24
Finished	Mar 12 12:47:01 PM PDT 24
Peak memory	200724 kb
Host	smart-3f92b4be-94ad-4bf0-93b8-885b08742378
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147257939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_clk_byp_req_intersig_mubi.1147257939
Directory	/workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.4241801928
Short name	T192
Test name
Test status
Simulation time	61733041 ps
CPU time	0.98 seconds
Started	Mar 12 12:47:04 PM PDT 24
Finished	Mar 12 12:47:06 PM PDT 24
Peak memory	200772 kb
Host	smart-aa6dcc7e-6abe-4dc1-a468-e5054b5a1978
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241801928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_ctrl_intersig_mubi.4241801928
Directory	/workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_peri.2663373630
Short name	T496
Test name
Test status
Simulation time	35024287 ps
CPU time	0.82 seconds
Started	Mar 12 12:46:47 PM PDT 24
Finished	Mar 12 12:46:49 PM PDT 24
Peak memory	200816 kb
Host	smart-db4cd0c0-f527-4b9a-83b9-18b34659ecb0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663373630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.2663373630
Directory	/workspace/12.clkmgr_peri/latest

Test location	/workspace/coverage/default/12.clkmgr_regwen.3786100300
Short name	T370
Test name
Test status
Simulation time	921395548 ps
CPU time	4.57 seconds
Started	Mar 12 12:47:08 PM PDT 24
Finished	Mar 12 12:47:13 PM PDT 24
Peak memory	201028 kb
Host	smart-8e294639-1c6a-4d7d-8546-c4eecbc7fc53
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786100300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.3786100300
Directory	/workspace/12.clkmgr_regwen/latest

Test location	/workspace/coverage/default/12.clkmgr_smoke.3114590100
Short name	T300
Test name
Test status
Simulation time	72488692 ps
CPU time	1.08 seconds
Started	Mar 12 12:46:50 PM PDT 24
Finished	Mar 12 12:46:51 PM PDT 24
Peak memory	200688 kb
Host	smart-648f5a57-a5c8-46af-9263-2d933a1987fd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114590100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.3114590100
Directory	/workspace/12.clkmgr_smoke/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all.807664121
Short name	T252
Test name
Test status
Simulation time	4590983397 ps
CPU time	32.57 seconds
Started	Mar 12 12:47:08 PM PDT 24
Finished	Mar 12 12:47:40 PM PDT 24
Peak memory	201180 kb
Host	smart-19020744-e66a-4ec4-8282-7c092a767560
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807664121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.807664121
Directory	/workspace/12.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.1124946011
Short name	T480
Test name
Test status
Simulation time	130445494523 ps
CPU time	931.16 seconds
Started	Mar 12 12:47:01 PM PDT 24
Finished	Mar 12 01:02:33 PM PDT 24
Peak memory	214728 kb
Host	smart-da633009-ee61-411a-b3b3-8f7ba9c5f51f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1124946011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.1124946011
Directory	/workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.clkmgr_trans.1559337008
Short name	T755
Test name
Test status
Simulation time	16202485 ps
CPU time	0.69 seconds
Started	Mar 12 12:46:54 PM PDT 24
Finished	Mar 12 12:46:55 PM PDT 24
Peak memory	200840 kb
Host	smart-33c3b971-b0db-49a8-99be-9c8f2edc6ff4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559337008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.1559337008
Directory	/workspace/12.clkmgr_trans/latest

Test location	/workspace/coverage/default/13.clkmgr_alert_test.3219737174
Short name	T435
Test name
Test status
Simulation time	39067603 ps
CPU time	0.83 seconds
Started	Mar 12 12:47:01 PM PDT 24
Finished	Mar 12 12:47:02 PM PDT 24
Peak memory	200784 kb
Host	smart-0b9d956b-b44c-4c39-a61f-03e5b5b25d08
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219737174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk mgr_alert_test.3219737174
Directory	/workspace/13.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.185630233
Short name	T497
Test name
Test status
Simulation time	22080422 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:09 PM PDT 24
Finished	Mar 12 12:47:10 PM PDT 24
Peak memory	200736 kb
Host	smart-7da5fd48-3cfd-469c-98c6-b2034f20aae0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185630233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.185630233
Directory	/workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_status.135502340
Short name	T691
Test name
Test status
Simulation time	60597471 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:09 PM PDT 24
Finished	Mar 12 12:47:10 PM PDT 24
Peak memory	199792 kb
Host	smart-1ef81b75-5e1e-4aca-886e-0793d8318e8f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135502340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.135502340
Directory	/workspace/13.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/13.clkmgr_div_intersig_mubi.541977305
Short name	T411
Test name
Test status
Simulation time	15315891 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:01 PM PDT 24
Finished	Mar 12 12:47:03 PM PDT 24
Peak memory	200704 kb
Host	smart-bcba80da-3a66-4ca5-8ab2-dd57d89bf77f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541977305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.clkmgr_div_intersig_mubi.541977305
Directory	/workspace/13.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_extclk.536536979
Short name	T689
Test name
Test status
Simulation time	14059465 ps
CPU time	0.76 seconds
Started	Mar 12 12:47:01 PM PDT 24
Finished	Mar 12 12:47:03 PM PDT 24
Peak memory	200764 kb
Host	smart-5782f6da-2917-47a5-a5ab-e57c2b575e1e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536536979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.536536979
Directory	/workspace/13.clkmgr_extclk/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency.3014887925
Short name	T541
Test name
Test status
Simulation time	855704646 ps
CPU time	4.16 seconds
Started	Mar 12 12:47:03 PM PDT 24
Finished	Mar 12 12:47:07 PM PDT 24
Peak memory	200868 kb
Host	smart-0e472777-5b31-4b47-8000-98613ed82635
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014887925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.3014887925
Directory	/workspace/13.clkmgr_frequency/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency_timeout.3053482267
Short name	T728
Test name
Test status
Simulation time	753410373 ps
CPU time	3.51 seconds
Started	Mar 12 12:47:05 PM PDT 24
Finished	Mar 12 12:47:08 PM PDT 24
Peak memory	200824 kb
Host	smart-d8720884-d599-448d-af64-e2cea12c1278
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053482267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t imeout.3053482267
Directory	/workspace/13.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.834855068
Short name	T813
Test name
Test status
Simulation time	42585384 ps
CPU time	0.98 seconds
Started	Mar 12 12:47:05 PM PDT 24
Finished	Mar 12 12:47:06 PM PDT 24
Peak memory	200808 kb
Host	smart-5cf5051f-b67f-4269-b81d-b54eb24c27d9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834855068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.clkmgr_lc_clk_byp_req_intersig_mubi.834855068
Directory	/workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.2459736050
Short name	T531
Test name
Test status
Simulation time	34258400 ps
CPU time	0.85 seconds
Started	Mar 12 12:47:08 PM PDT 24
Finished	Mar 12 12:47:09 PM PDT 24
Peak memory	200640 kb
Host	smart-bfddd54c-cdc3-49b9-8a61-5c21f8ce61a8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459736050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_ctrl_intersig_mubi.2459736050
Directory	/workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_peri.2768972220
Short name	T190
Test name
Test status
Simulation time	28200125 ps
CPU time	0.83 seconds
Started	Mar 12 12:47:00 PM PDT 24
Finished	Mar 12 12:47:01 PM PDT 24
Peak memory	200644 kb
Host	smart-17cb4b9f-e51d-43ee-8232-24710ab2469e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768972220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.2768972220
Directory	/workspace/13.clkmgr_peri/latest

Test location	/workspace/coverage/default/13.clkmgr_regwen.586243551
Short name	T181
Test name
Test status
Simulation time	152732152 ps
CPU time	1.21 seconds
Started	Mar 12 12:46:59 PM PDT 24
Finished	Mar 12 12:47:00 PM PDT 24
Peak memory	200764 kb
Host	smart-1e5da2ce-5abd-4bea-a527-8af870b330fd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586243551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.586243551
Directory	/workspace/13.clkmgr_regwen/latest

Test location	/workspace/coverage/default/13.clkmgr_smoke.3893082323
Short name	T747
Test name
Test status
Simulation time	79424704 ps
CPU time	0.98 seconds
Started	Mar 12 12:47:01 PM PDT 24
Finished	Mar 12 12:47:02 PM PDT 24
Peak memory	200556 kb
Host	smart-bb45f9dd-ea33-4015-89be-9ac5d17dde42
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893082323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.3893082323
Directory	/workspace/13.clkmgr_smoke/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all.3334158208
Short name	T617
Test name
Test status
Simulation time	2810805383 ps
CPU time	22.02 seconds
Started	Mar 12 12:47:00 PM PDT 24
Finished	Mar 12 12:47:23 PM PDT 24
Peak memory	201152 kb
Host	smart-65a96f3e-0c3f-40d1-a974-e20388abee38
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334158208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.3334158208
Directory	/workspace/13.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.347354776
Short name	T571
Test name
Test status
Simulation time	224463081935 ps
CPU time	1168.03 seconds
Started	Mar 12 12:46:58 PM PDT 24
Finished	Mar 12 01:06:26 PM PDT 24
Peak memory	209492 kb
Host	smart-bf7cd28a-7272-4840-a574-99481bbf5819
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=347354776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.347354776
Directory	/workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.clkmgr_trans.744106087
Short name	T424
Test name
Test status
Simulation time	82050635 ps
CPU time	1.06 seconds
Started	Mar 12 12:47:02 PM PDT 24
Finished	Mar 12 12:47:04 PM PDT 24
Peak memory	200832 kb
Host	smart-5621c967-30a2-47dd-b240-a42efc9be039
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744106087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.744106087
Directory	/workspace/13.clkmgr_trans/latest

Test location	/workspace/coverage/default/14.clkmgr_alert_test.19419160
Short name	T651
Test name
Test status
Simulation time	15677130 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:03 PM PDT 24
Finished	Mar 12 12:47:04 PM PDT 24
Peak memory	200772 kb
Host	smart-606cda31-2d36-4501-9987-f2565f520a86
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19419160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmg r_alert_test.19419160
Directory	/workspace/14.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.1768065487
Short name	T458
Test name
Test status
Simulation time	18779322 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:05 PM PDT 24
Finished	Mar 12 12:47:06 PM PDT 24
Peak memory	200724 kb
Host	smart-46af9296-abdb-4b58-803a-768e61a9e660
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768065487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.1768065487
Directory	/workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_status.79375113
Short name	T356
Test name
Test status
Simulation time	17109816 ps
CPU time	0.69 seconds
Started	Mar 12 12:47:02 PM PDT 24
Finished	Mar 12 12:47:03 PM PDT 24
Peak memory	200772 kb
Host	smart-1880aacb-1172-4e1c-9cc0-e5e9dee0af88
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79375113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.79375113
Directory	/workspace/14.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/14.clkmgr_div_intersig_mubi.2457022223
Short name	T206
Test name
Test status
Simulation time	28802441 ps
CPU time	0.91 seconds
Started	Mar 12 12:47:07 PM PDT 24
Finished	Mar 12 12:47:08 PM PDT 24
Peak memory	200772 kb
Host	smart-c0dfcdae-4b8c-4e75-9584-c946ec1db8e7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457022223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.2457022223
Directory	/workspace/14.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_extclk.1490291316
Short name	T466
Test name
Test status
Simulation time	13534912 ps
CPU time	0.76 seconds
Started	Mar 12 12:47:05 PM PDT 24
Finished	Mar 12 12:47:06 PM PDT 24
Peak memory	200792 kb
Host	smart-b78c1e21-47c1-407c-b7ed-84bea83d0e6d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490291316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.1490291316
Directory	/workspace/14.clkmgr_extclk/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency.2898778637
Short name	T805
Test name
Test status
Simulation time	918715472 ps
CPU time	6.38 seconds
Started	Mar 12 12:47:00 PM PDT 24
Finished	Mar 12 12:47:06 PM PDT 24
Peak memory	200872 kb
Host	smart-30cba049-61e0-4c01-91c2-9a23110b8c8f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898778637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.2898778637
Directory	/workspace/14.clkmgr_frequency/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency_timeout.3057005339
Short name	T185
Test name
Test status
Simulation time	1099355426 ps
CPU time	6.11 seconds
Started	Mar 12 12:47:00 PM PDT 24
Finished	Mar 12 12:47:07 PM PDT 24
Peak memory	200904 kb
Host	smart-07f461de-de1a-492c-9b62-d5943ad1c1e5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057005339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t imeout.3057005339
Directory	/workspace/14.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/14.clkmgr_idle_intersig_mubi.2040944380
Short name	T162
Test name
Test status
Simulation time	32126299 ps
CPU time	0.94 seconds
Started	Mar 12 12:47:16 PM PDT 24
Finished	Mar 12 12:47:17 PM PDT 24
Peak memory	200808 kb
Host	smart-9de15496-350b-4111-a1d0-adeeb9dd1994
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040944380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.2040944380
Directory	/workspace/14.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.847351757
Short name	T734
Test name
Test status
Simulation time	74508708 ps
CPU time	0.99 seconds
Started	Mar 12 12:47:05 PM PDT 24
Finished	Mar 12 12:47:06 PM PDT 24
Peak memory	200716 kb
Host	smart-5dae0a36-a8e4-49fa-ba43-defc887b84f4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847351757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.clkmgr_lc_clk_byp_req_intersig_mubi.847351757
Directory	/workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.3878973568
Short name	T385
Test name
Test status
Simulation time	21124304 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:27 PM PDT 24
Finished	Mar 12 12:47:28 PM PDT 24
Peak memory	200768 kb
Host	smart-9d248f43-f44e-400b-9244-b2ce10f32eb1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878973568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.clkmgr_lc_ctrl_intersig_mubi.3878973568
Directory	/workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_peri.3428137418
Short name	T345
Test name
Test status
Simulation time	84010181 ps
CPU time	0.92 seconds
Started	Mar 12 12:47:03 PM PDT 24
Finished	Mar 12 12:47:04 PM PDT 24
Peak memory	200580 kb
Host	smart-86ff593c-8375-4ad1-a446-13b65941b101
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428137418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.3428137418
Directory	/workspace/14.clkmgr_peri/latest

Test location	/workspace/coverage/default/14.clkmgr_regwen.3882522537
Short name	T343
Test name
Test status
Simulation time	720659749 ps
CPU time	4.29 seconds
Started	Mar 12 12:47:03 PM PDT 24
Finished	Mar 12 12:47:08 PM PDT 24
Peak memory	201056 kb
Host	smart-58dc79eb-c399-4a61-b77f-c1f5e3499d46
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882522537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.3882522537
Directory	/workspace/14.clkmgr_regwen/latest

Test location	/workspace/coverage/default/14.clkmgr_smoke.2511273030
Short name	T827
Test name
Test status
Simulation time	88601369 ps
CPU time	1.07 seconds
Started	Mar 12 12:47:01 PM PDT 24
Finished	Mar 12 12:47:03 PM PDT 24
Peak memory	200812 kb
Host	smart-6d69af9d-4469-4b33-b25c-8a3e1bb1464e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511273030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.2511273030
Directory	/workspace/14.clkmgr_smoke/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all.3078542520
Short name	T15
Test name
Test status
Simulation time	12374369789 ps
CPU time	43.02 seconds
Started	Mar 12 12:47:09 PM PDT 24
Finished	Mar 12 12:47:53 PM PDT 24
Peak memory	201184 kb
Host	smart-38f1a6d8-3f46-4139-bf86-6f36746a91f5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078542520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.3078542520
Directory	/workspace/14.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.1649711710
Short name	T626
Test name
Test status
Simulation time	26858739505 ps
CPU time	415.78 seconds
Started	Mar 12 12:47:14 PM PDT 24
Finished	Mar 12 12:54:10 PM PDT 24
Peak memory	209572 kb
Host	smart-b369f903-4e6b-4813-9369-d3540141e46e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1649711710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.1649711710
Directory	/workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.clkmgr_trans.591326926
Short name	T567
Test name
Test status
Simulation time	98936432 ps
CPU time	0.94 seconds
Started	Mar 12 12:47:08 PM PDT 24
Finished	Mar 12 12:47:09 PM PDT 24
Peak memory	200780 kb
Host	smart-a54a4421-62ea-40c0-9328-42479ff1ee17
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591326926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.591326926
Directory	/workspace/14.clkmgr_trans/latest

Test location	/workspace/coverage/default/15.clkmgr_alert_test.3288087238
Short name	T341
Test name
Test status
Simulation time	18516400 ps
CPU time	0.74 seconds
Started	Mar 12 12:47:16 PM PDT 24
Finished	Mar 12 12:47:17 PM PDT 24
Peak memory	200856 kb
Host	smart-fa7cd9aa-053c-4485-9f93-5b646fbd3fcc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288087238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk mgr_alert_test.3288087238
Directory	/workspace/15.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.300321620
Short name	T506
Test name
Test status
Simulation time	25225075 ps
CPU time	0.84 seconds
Started	Mar 12 12:47:02 PM PDT 24
Finished	Mar 12 12:47:03 PM PDT 24
Peak memory	200728 kb
Host	smart-151f5d58-2334-42f7-94f8-6a5f3adef6f8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300321620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.300321620
Directory	/workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_status.1226047145
Short name	T148
Test name
Test status
Simulation time	16820374 ps
CPU time	0.71 seconds
Started	Mar 12 12:46:59 PM PDT 24
Finished	Mar 12 12:47:01 PM PDT 24
Peak memory	200744 kb
Host	smart-2d551984-6c6e-4362-a02f-4d4c25206c89
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226047145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.1226047145
Directory	/workspace/15.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/15.clkmgr_div_intersig_mubi.455981675
Short name	T319
Test name
Test status
Simulation time	71660073 ps
CPU time	1.02 seconds
Started	Mar 12 12:47:02 PM PDT 24
Finished	Mar 12 12:47:03 PM PDT 24
Peak memory	200772 kb
Host	smart-3f2c8b5f-0689-4700-a9eb-920cd968b2ac
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455981675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.clkmgr_div_intersig_mubi.455981675
Directory	/workspace/15.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_extclk.3547693237
Short name	T686
Test name
Test status
Simulation time	41663292 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:12 PM PDT 24
Finished	Mar 12 12:47:13 PM PDT 24
Peak memory	200676 kb
Host	smart-a688e1ab-a270-4eba-84c2-13d549423858
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547693237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.3547693237
Directory	/workspace/15.clkmgr_extclk/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency.626258433
Short name	T621
Test name
Test status
Simulation time	2004282546 ps
CPU time	13.71 seconds
Started	Mar 12 12:46:59 PM PDT 24
Finished	Mar 12 12:47:13 PM PDT 24
Peak memory	200988 kb
Host	smart-74bc9cb7-1125-48c9-810e-3004a4ff6866
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626258433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.626258433
Directory	/workspace/15.clkmgr_frequency/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency_timeout.1442762026
Short name	T205
Test name
Test status
Simulation time	2179918551 ps
CPU time	15.38 seconds
Started	Mar 12 12:47:07 PM PDT 24
Finished	Mar 12 12:47:22 PM PDT 24
Peak memory	201168 kb
Host	smart-be38c053-315b-4ca9-ab04-05c9ffe14471
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442762026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t imeout.1442762026
Directory	/workspace/15.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/15.clkmgr_idle_intersig_mubi.2020994013
Short name	T457
Test name
Test status
Simulation time	41100001 ps
CPU time	1.12 seconds
Started	Mar 12 12:47:03 PM PDT 24
Finished	Mar 12 12:47:04 PM PDT 24
Peak memory	200840 kb
Host	smart-8883c02b-c4a3-47d6-b7d4-6bf7c8b73c39
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020994013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.2020994013
Directory	/workspace/15.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.3929781573
Short name	T647
Test name
Test status
Simulation time	13552775 ps
CPU time	0.73 seconds
Started	Mar 12 12:47:05 PM PDT 24
Finished	Mar 12 12:47:06 PM PDT 24
Peak memory	200800 kb
Host	smart-b01df410-c4e7-46fb-be47-89274d547f60
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929781573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_clk_byp_req_intersig_mubi.3929781573
Directory	/workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.2418847728
Short name	T819
Test name
Test status
Simulation time	37312863 ps
CPU time	0.86 seconds
Started	Mar 12 12:47:00 PM PDT 24
Finished	Mar 12 12:47:01 PM PDT 24
Peak memory	200664 kb
Host	smart-cf02b6b8-0168-4e9e-9e8d-d62c7051c785
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418847728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_ctrl_intersig_mubi.2418847728
Directory	/workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_peri.1369451865
Short name	T82
Test name
Test status
Simulation time	19071892 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:08 PM PDT 24
Finished	Mar 12 12:47:09 PM PDT 24
Peak memory	200644 kb
Host	smart-f53be1c6-7377-439d-a96b-4fa587727927
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369451865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.1369451865
Directory	/workspace/15.clkmgr_peri/latest

Test location	/workspace/coverage/default/15.clkmgr_regwen.2757646166
Short name	T821
Test name
Test status
Simulation time	706335746 ps
CPU time	3.34 seconds
Started	Mar 12 12:47:03 PM PDT 24
Finished	Mar 12 12:47:07 PM PDT 24
Peak memory	201048 kb
Host	smart-85317e4e-7f04-4e02-9ed9-e41cd14841f6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757646166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.2757646166
Directory	/workspace/15.clkmgr_regwen/latest

Test location	/workspace/coverage/default/15.clkmgr_smoke.4220023096
Short name	T677
Test name
Test status
Simulation time	32445465 ps
CPU time	0.86 seconds
Started	Mar 12 12:47:02 PM PDT 24
Finished	Mar 12 12:47:03 PM PDT 24
Peak memory	200808 kb
Host	smart-7cd0e562-15cf-4ea6-8ee7-1ad3633aa331
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220023096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.4220023096
Directory	/workspace/15.clkmgr_smoke/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all.2557518906
Short name	T648
Test name
Test status
Simulation time	6246499369 ps
CPU time	27.85 seconds
Started	Mar 12 12:47:01 PM PDT 24
Finished	Mar 12 12:47:29 PM PDT 24
Peak memory	201220 kb
Host	smart-61040a4d-2ea7-49c8-891a-b2b1ad711f10
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557518906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.2557518906
Directory	/workspace/15.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.4249316607
Short name	T767
Test name
Test status
Simulation time	33995057359 ps
CPU time	566.04 seconds
Started	Mar 12 12:47:09 PM PDT 24
Finished	Mar 12 12:56:35 PM PDT 24
Peak memory	217640 kb
Host	smart-b5126ae2-cb6b-4bc2-bd22-4b6a55d3e96a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4249316607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.4249316607
Directory	/workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.clkmgr_trans.2660238783
Short name	T848
Test name
Test status
Simulation time	22087987 ps
CPU time	0.83 seconds
Started	Mar 12 12:47:01 PM PDT 24
Finished	Mar 12 12:47:02 PM PDT 24
Peak memory	200760 kb
Host	smart-e412bea5-fc20-4b22-80cf-14e21d2c5a72
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660238783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.2660238783
Directory	/workspace/15.clkmgr_trans/latest

Test location	/workspace/coverage/default/16.clkmgr_alert_test.3388227479
Short name	T247
Test name
Test status
Simulation time	32921983 ps
CPU time	0.92 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:27 PM PDT 24
Peak memory	200788 kb
Host	smart-84f3353b-4232-4e2f-ad07-96cb4660c02d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388227479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk mgr_alert_test.3388227479
Directory	/workspace/16.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.1679555882
Short name	T88
Test name
Test status
Simulation time	56299042 ps
CPU time	0.99 seconds
Started	Mar 12 12:47:15 PM PDT 24
Finished	Mar 12 12:47:16 PM PDT 24
Peak memory	200724 kb
Host	smart-a4ba6f5b-ed53-400d-8ee4-6bcf7192a394
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679555882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.1679555882
Directory	/workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_status.2338258
Short name	T381
Test name
Test status
Simulation time	23673449 ps
CPU time	0.69 seconds
Started	Mar 12 12:47:24 PM PDT 24
Finished	Mar 12 12:47:25 PM PDT 24
Peak memory	199712 kb
Host	smart-e7c1d165-886a-4749-b2a1-de954f131a01
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.2338258
Directory	/workspace/16.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/16.clkmgr_div_intersig_mubi.3539012689
Short name	T843
Test name
Test status
Simulation time	17923647 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:11 PM PDT 24
Finished	Mar 12 12:47:12 PM PDT 24
Peak memory	200596 kb
Host	smart-36bded6f-d5c3-47d7-ae31-ac371e44cc9b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539012689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.3539012689
Directory	/workspace/16.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_extclk.2539797246
Short name	T453
Test name
Test status
Simulation time	25175853 ps
CPU time	0.88 seconds
Started	Mar 12 12:47:08 PM PDT 24
Finished	Mar 12 12:47:09 PM PDT 24
Peak memory	200804 kb
Host	smart-44c41c5d-bb08-4ae6-b1e0-7fe2c877d838
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539797246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.2539797246
Directory	/workspace/16.clkmgr_extclk/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency.2520286825
Short name	T494
Test name
Test status
Simulation time	1758393385 ps
CPU time	12.92 seconds
Started	Mar 12 12:47:08 PM PDT 24
Finished	Mar 12 12:47:21 PM PDT 24
Peak memory	200860 kb
Host	smart-d828cc26-3ccb-496a-a38a-0c21fe8ee47e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520286825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.2520286825
Directory	/workspace/16.clkmgr_frequency/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency_timeout.646176446
Short name	T817
Test name
Test status
Simulation time	688060359 ps
CPU time	2.78 seconds
Started	Mar 12 12:47:13 PM PDT 24
Finished	Mar 12 12:47:16 PM PDT 24
Peak memory	200924 kb
Host	smart-e7fd7e50-c004-47d5-b007-fab401ddfa3e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646176446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_ti meout.646176446
Directory	/workspace/16.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/16.clkmgr_idle_intersig_mubi.920696
Short name	T846
Test name
Test status
Simulation time	108599907 ps
CPU time	1.2 seconds
Started	Mar 12 12:47:14 PM PDT 24
Finished	Mar 12 12:47:15 PM PDT 24
Peak memory	200784 kb
Host	smart-ac441b92-cfa3-43fd-9b5e-12be048d80cf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.c lkmgr_idle_intersig_mubi.920696
Directory	/workspace/16.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.2967117094
Short name	T336
Test name
Test status
Simulation time	26199209 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:16 PM PDT 24
Finished	Mar 12 12:47:16 PM PDT 24
Peak memory	200660 kb
Host	smart-6bb2fa2a-d777-4469-ba6d-8e409707a967
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967117094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.clkmgr_lc_clk_byp_req_intersig_mubi.2967117094
Directory	/workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3835325404
Short name	T660
Test name
Test status
Simulation time	24305400 ps
CPU time	0.89 seconds
Started	Mar 12 12:47:29 PM PDT 24
Finished	Mar 12 12:47:30 PM PDT 24
Peak memory	200844 kb
Host	smart-528500d7-edb7-48d8-bb52-cbe1e7bb7fa3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835325404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.clkmgr_lc_ctrl_intersig_mubi.3835325404
Directory	/workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_peri.3177634170
Short name	T187
Test name
Test status
Simulation time	30266159 ps
CPU time	0.84 seconds
Started	Mar 12 12:47:02 PM PDT 24
Finished	Mar 12 12:47:03 PM PDT 24
Peak memory	200668 kb
Host	smart-9576b7fb-2482-4e8a-86a1-85b668e7bb4d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177634170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.3177634170
Directory	/workspace/16.clkmgr_peri/latest

Test location	/workspace/coverage/default/16.clkmgr_regwen.1152420642
Short name	T513
Test name
Test status
Simulation time	1476385981 ps
CPU time	5.39 seconds
Started	Mar 12 12:47:15 PM PDT 24
Finished	Mar 12 12:47:20 PM PDT 24
Peak memory	201084 kb
Host	smart-3b752cfd-d320-4fd4-8229-f3dee0571fe2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152420642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.1152420642
Directory	/workspace/16.clkmgr_regwen/latest

Test location	/workspace/coverage/default/16.clkmgr_smoke.4209663240
Short name	T219
Test name
Test status
Simulation time	27852080 ps
CPU time	0.8 seconds
Started	Mar 12 12:47:04 PM PDT 24
Finished	Mar 12 12:47:05 PM PDT 24
Peak memory	200864 kb
Host	smart-12c90e8f-a85e-4622-9bc1-8df54aa9df2e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209663240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.4209663240
Directory	/workspace/16.clkmgr_smoke/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all.189014183
Short name	T746
Test name
Test status
Simulation time	4871526277 ps
CPU time	18.24 seconds
Started	Mar 12 12:47:28 PM PDT 24
Finished	Mar 12 12:47:47 PM PDT 24
Peak memory	201176 kb
Host	smart-3069ba59-cd8d-4afd-89b3-f3c1f9f5361f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189014183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.189014183
Directory	/workspace/16.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.3761962489
Short name	T28
Test name
Test status
Simulation time	74256307483 ps
CPU time	511.94 seconds
Started	Mar 12 12:47:17 PM PDT 24
Finished	Mar 12 12:55:49 PM PDT 24
Peak memory	211628 kb
Host	smart-8358187a-c4db-4f5e-9112-b9ce7eb4e314
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3761962489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.3761962489
Directory	/workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.clkmgr_trans.4261694862
Short name	T170
Test name
Test status
Simulation time	100126217 ps
CPU time	1.15 seconds
Started	Mar 12 12:47:08 PM PDT 24
Finished	Mar 12 12:47:09 PM PDT 24
Peak memory	200808 kb
Host	smart-c9b0c759-86be-432f-b71a-58c728314ff3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261694862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.4261694862
Directory	/workspace/16.clkmgr_trans/latest

Test location	/workspace/coverage/default/17.clkmgr_alert_test.2025265818
Short name	T818
Test name
Test status
Simulation time	11821629 ps
CPU time	0.72 seconds
Started	Mar 12 12:47:14 PM PDT 24
Finished	Mar 12 12:47:14 PM PDT 24
Peak memory	200840 kb
Host	smart-d6d17a83-c969-49bd-9c40-c5039fe7593d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025265818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk mgr_alert_test.2025265818
Directory	/workspace/17.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.3454339934
Short name	T554
Test name
Test status
Simulation time	22227969 ps
CPU time	0.84 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:19 PM PDT 24
Peak memory	200792 kb
Host	smart-81d8ee32-ad16-46e4-b699-1aa6dc5c7b0a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454339934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.3454339934
Directory	/workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_status.2484012281
Short name	T416
Test name
Test status
Simulation time	25240223 ps
CPU time	0.74 seconds
Started	Mar 12 12:47:22 PM PDT 24
Finished	Mar 12 12:47:23 PM PDT 24
Peak memory	199804 kb
Host	smart-b7ddb80e-ff86-4f30-8a3f-c63665f902c1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484012281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.2484012281
Directory	/workspace/17.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/17.clkmgr_div_intersig_mubi.3458011461
Short name	T129
Test name
Test status
Simulation time	34744345 ps
CPU time	0.91 seconds
Started	Mar 12 12:47:17 PM PDT 24
Finished	Mar 12 12:47:18 PM PDT 24
Peak memory	200648 kb
Host	smart-61274610-da88-4f4c-995b-3de9de01acc1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458011461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.3458011461
Directory	/workspace/17.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_extclk.3482332506
Short name	T342
Test name
Test status
Simulation time	16850228 ps
CPU time	0.75 seconds
Started	Mar 12 12:47:34 PM PDT 24
Finished	Mar 12 12:47:35 PM PDT 24
Peak memory	200544 kb
Host	smart-3ddddb30-6344-481d-be60-50c1b955316a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482332506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.3482332506
Directory	/workspace/17.clkmgr_extclk/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency.2764436792
Short name	T106
Test name
Test status
Simulation time	1304044661 ps
CPU time	6.05 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:24 PM PDT 24
Peak memory	200828 kb
Host	smart-394997c0-0d3f-47c5-b7d7-253be67041d7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764436792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.2764436792
Directory	/workspace/17.clkmgr_frequency/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency_timeout.1569580655
Short name	T109
Test name
Test status
Simulation time	2399602093 ps
CPU time	10.21 seconds
Started	Mar 12 12:47:16 PM PDT 24
Finished	Mar 12 12:47:26 PM PDT 24
Peak memory	201136 kb
Host	smart-fbdcda50-60b6-4e33-82fb-49fedbbf1e97
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569580655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t imeout.1569580655
Directory	/workspace/17.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/17.clkmgr_idle_intersig_mubi.3250220021
Short name	T779
Test name
Test status
Simulation time	55042213 ps
CPU time	1.02 seconds
Started	Mar 12 12:47:16 PM PDT 24
Finished	Mar 12 12:47:17 PM PDT 24
Peak memory	200804 kb
Host	smart-fe52c86d-4a26-4494-9254-d4a93ff8bf2c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250220021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.3250220021
Directory	/workspace/17.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.42414755
Short name	T792
Test name
Test status
Simulation time	22436478 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:22 PM PDT 24
Finished	Mar 12 12:47:23 PM PDT 24
Peak memory	200728 kb
Host	smart-95508297-cec0-458d-9f7f-80fd8dc78bf8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42414755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_clk_byp_req_intersig_mubi.42414755
Directory	/workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.306654069
Short name	T218
Test name
Test status
Simulation time	91420434 ps
CPU time	1.04 seconds
Started	Mar 12 12:47:29 PM PDT 24
Finished	Mar 12 12:47:30 PM PDT 24
Peak memory	200536 kb
Host	smart-38e3ecda-5045-4442-854c-281ddec233f2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306654069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.clkmgr_lc_ctrl_intersig_mubi.306654069
Directory	/workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_peri.1557547131
Short name	T487
Test name
Test status
Simulation time	33753579 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:23 PM PDT 24
Finished	Mar 12 12:47:24 PM PDT 24
Peak memory	200724 kb
Host	smart-7360dcd4-932e-44bf-86e0-898c666ad8cf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557547131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.1557547131
Directory	/workspace/17.clkmgr_peri/latest

Test location	/workspace/coverage/default/17.clkmgr_regwen.1488190497
Short name	T135
Test name
Test status
Simulation time	429947395 ps
CPU time	2.8 seconds
Started	Mar 12 12:47:13 PM PDT 24
Finished	Mar 12 12:47:16 PM PDT 24
Peak memory	200772 kb
Host	smart-5a8953ec-211e-4791-89af-5721f2cbd873
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488190497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.1488190497
Directory	/workspace/17.clkmgr_regwen/latest

Test location	/workspace/coverage/default/17.clkmgr_smoke.1197261006
Short name	T228
Test name
Test status
Simulation time	15896144 ps
CPU time	0.85 seconds
Started	Mar 12 12:47:13 PM PDT 24
Finished	Mar 12 12:47:14 PM PDT 24
Peak memory	200840 kb
Host	smart-6f4ea1f6-7535-44f6-9620-5a16195261fd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197261006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.1197261006
Directory	/workspace/17.clkmgr_smoke/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all.2345010734
Short name	T703
Test name
Test status
Simulation time	6906809625 ps
CPU time	27.27 seconds
Started	Mar 12 12:47:16 PM PDT 24
Finished	Mar 12 12:47:43 PM PDT 24
Peak memory	201212 kb
Host	smart-23d6e223-d5f1-4354-9848-30e22e28b7be
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345010734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.2345010734
Directory	/workspace/17.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.2903428257
Short name	T11
Test name
Test status
Simulation time	13574552442 ps
CPU time	129.5 seconds
Started	Mar 12 12:47:16 PM PDT 24
Finished	Mar 12 12:49:26 PM PDT 24
Peak memory	209564 kb
Host	smart-0fd59a19-8f24-4d90-9376-bc72be87f3ba
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2903428257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.2903428257
Directory	/workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.clkmgr_trans.2983004968
Short name	T814
Test name
Test status
Simulation time	21552965 ps
CPU time	0.82 seconds
Started	Mar 12 12:47:11 PM PDT 24
Finished	Mar 12 12:47:12 PM PDT 24
Peak memory	200724 kb
Host	smart-f08bb29a-8573-45f0-ad7d-49504340a4a2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983004968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.2983004968
Directory	/workspace/17.clkmgr_trans/latest

Test location	/workspace/coverage/default/18.clkmgr_alert_test.722243455
Short name	T832
Test name
Test status
Simulation time	18611429 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:23 PM PDT 24
Finished	Mar 12 12:47:24 PM PDT 24
Peak memory	200892 kb
Host	smart-6848fa0d-ef91-4d72-ba57-d2dbcb85a8f3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722243455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkm gr_alert_test.722243455
Directory	/workspace/18.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.509152443
Short name	T393
Test name
Test status
Simulation time	207593633 ps
CPU time	1.5 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:20 PM PDT 24
Peak memory	200860 kb
Host	smart-aecc41c5-33e6-4cb9-b296-e1d1934e0d65
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509152443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.509152443
Directory	/workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_status.1924925006
Short name	T255
Test name
Test status
Simulation time	18386243 ps
CPU time	0.78 seconds
Started	Mar 12 12:47:13 PM PDT 24
Finished	Mar 12 12:47:14 PM PDT 24
Peak memory	200760 kb
Host	smart-d51d7d2f-18bb-4116-b6e4-482abb9d4aed
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924925006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.1924925006
Directory	/workspace/18.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/18.clkmgr_div_intersig_mubi.1487907
Short name	T288
Test name
Test status
Simulation time	91449076 ps
CPU time	1.05 seconds
Started	Mar 12 12:47:17 PM PDT 24
Finished	Mar 12 12:47:18 PM PDT 24
Peak memory	200824 kb
Host	smart-6cefb9d0-a29d-4d62-8252-57f9580b3402
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. clkmgr_div_intersig_mubi.1487907
Directory	/workspace/18.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_extclk.3269871418
Short name	T256
Test name
Test status
Simulation time	47513219 ps
CPU time	0.9 seconds
Started	Mar 12 12:47:17 PM PDT 24
Finished	Mar 12 12:47:18 PM PDT 24
Peak memory	200692 kb
Host	smart-e82f50b6-a867-499f-a87d-b26dcbd89776
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269871418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.3269871418
Directory	/workspace/18.clkmgr_extclk/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency.3264338844
Short name	T533
Test name
Test status
Simulation time	1770227341 ps
CPU time	6.42 seconds
Started	Mar 12 12:47:20 PM PDT 24
Finished	Mar 12 12:47:26 PM PDT 24
Peak memory	200816 kb
Host	smart-6e62cd4a-534b-482a-b6e5-79b6c9e544f5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264338844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.3264338844
Directory	/workspace/18.clkmgr_frequency/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency_timeout.1851737198
Short name	T559
Test name
Test status
Simulation time	997142679 ps
CPU time	4.29 seconds
Started	Mar 12 12:47:30 PM PDT 24
Finished	Mar 12 12:47:35 PM PDT 24
Peak memory	200920 kb
Host	smart-3d328a44-3130-47f9-a60b-003a096ffa27
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851737198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t imeout.1851737198
Directory	/workspace/18.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/18.clkmgr_idle_intersig_mubi.3262586399
Short name	T434
Test name
Test status
Simulation time	32328897 ps
CPU time	0.91 seconds
Started	Mar 12 12:47:27 PM PDT 24
Finished	Mar 12 12:47:28 PM PDT 24
Peak memory	200848 kb
Host	smart-31bb873e-0582-474a-9e1f-5854502fc626
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262586399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.3262586399
Directory	/workspace/18.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.3133822656
Short name	T262
Test name
Test status
Simulation time	29743718 ps
CPU time	0.83 seconds
Started	Mar 12 12:47:29 PM PDT 24
Finished	Mar 12 12:47:30 PM PDT 24
Peak memory	200768 kb
Host	smart-b486c25f-3316-4fef-9a0e-4ad75603a8bc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133822656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.clkmgr_lc_clk_byp_req_intersig_mubi.3133822656
Directory	/workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.649276401
Short name	T695
Test name
Test status
Simulation time	20802401 ps
CPU time	0.86 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:19 PM PDT 24
Peak memory	200780 kb
Host	smart-62189aad-6e79-4916-b0c4-04443e4000cd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649276401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.clkmgr_lc_ctrl_intersig_mubi.649276401
Directory	/workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_peri.2790947207
Short name	T692
Test name
Test status
Simulation time	26408000 ps
CPU time	0.79 seconds
Started	Mar 12 12:47:22 PM PDT 24
Finished	Mar 12 12:47:23 PM PDT 24
Peak memory	200716 kb
Host	smart-9d638040-ae7e-4bd0-9c33-6b769c61a8db
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790947207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2790947207
Directory	/workspace/18.clkmgr_peri/latest

Test location	/workspace/coverage/default/18.clkmgr_regwen.701374833
Short name	T542
Test name
Test status
Simulation time	104662990 ps
CPU time	0.98 seconds
Started	Mar 12 12:47:13 PM PDT 24
Finished	Mar 12 12:47:14 PM PDT 24
Peak memory	200832 kb
Host	smart-0f5fb5f4-7eda-488c-866d-a602ff203006
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701374833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.701374833
Directory	/workspace/18.clkmgr_regwen/latest

Test location	/workspace/coverage/default/18.clkmgr_smoke.2551462255
Short name	T474
Test name
Test status
Simulation time	70844984 ps
CPU time	0.98 seconds
Started	Mar 12 12:47:25 PM PDT 24
Finished	Mar 12 12:47:26 PM PDT 24
Peak memory	200744 kb
Host	smart-06ebecdf-df69-49d1-a95c-acbbc4f1334f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551462255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.2551462255
Directory	/workspace/18.clkmgr_smoke/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all.2986364172
Short name	T640
Test name
Test status
Simulation time	384422441 ps
CPU time	3.86 seconds
Started	Mar 12 12:47:12 PM PDT 24
Finished	Mar 12 12:47:16 PM PDT 24
Peak memory	201152 kb
Host	smart-758d3780-1a42-4a2e-8939-8e7f8aac8a4f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986364172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.2986364172
Directory	/workspace/18.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.801619278
Short name	T32
Test name
Test status
Simulation time	189268619247 ps
CPU time	1100.32 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 01:05:47 PM PDT 24
Peak memory	209344 kb
Host	smart-a6171f46-79ed-4ab9-9c7c-71771c93ea5f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=801619278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.801619278
Directory	/workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.clkmgr_trans.3874516694
Short name	T79
Test name
Test status
Simulation time	20621467 ps
CPU time	0.83 seconds
Started	Mar 12 12:47:24 PM PDT 24
Finished	Mar 12 12:47:25 PM PDT 24
Peak memory	200860 kb
Host	smart-cb2d4d0c-4f55-4c80-9d88-2c6d89fbfd90
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874516694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.3874516694
Directory	/workspace/18.clkmgr_trans/latest

Test location	/workspace/coverage/default/19.clkmgr_alert_test.1318503332
Short name	T398
Test name
Test status
Simulation time	123381449 ps
CPU time	1.07 seconds
Started	Mar 12 12:47:29 PM PDT 24
Finished	Mar 12 12:47:30 PM PDT 24
Peak memory	200864 kb
Host	smart-1b829f2f-0856-4ffc-8495-e98a64ed83fe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318503332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk mgr_alert_test.1318503332
Directory	/workspace/19.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.4144551452
Short name	T780
Test name
Test status
Simulation time	135697353 ps
CPU time	1.29 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:20 PM PDT 24
Peak memory	200816 kb
Host	smart-0209974a-2df6-4faf-b609-8188099256f3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144551452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.4144551452
Directory	/workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_status.1620562042
Short name	T338
Test name
Test status
Simulation time	20493647 ps
CPU time	0.71 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:18 PM PDT 24
Peak memory	199756 kb
Host	smart-f4625d87-338f-45c4-b289-b53d2ff90e32
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620562042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.1620562042
Directory	/workspace/19.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/19.clkmgr_div_intersig_mubi.2298219584
Short name	T556
Test name
Test status
Simulation time	88008826 ps
CPU time	1.05 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200756 kb
Host	smart-b15c2e7c-27a0-4508-99e7-d33bcb980293
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298219584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.2298219584
Directory	/workspace/19.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_extclk.2348888551
Short name	T332
Test name
Test status
Simulation time	82680969 ps
CPU time	1.02 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:19 PM PDT 24
Peak memory	200744 kb
Host	smart-eec1e1c2-fd55-4e13-a5e1-f3661a5a6b63
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348888551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2348888551
Directory	/workspace/19.clkmgr_extclk/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency.2739534790
Short name	T103
Test name
Test status
Simulation time	568954302 ps
CPU time	3.7 seconds
Started	Mar 12 12:47:28 PM PDT 24
Finished	Mar 12 12:47:32 PM PDT 24
Peak memory	200712 kb
Host	smart-4d8c55eb-e0a1-4ef6-824a-0b7893a2229f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739534790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.2739534790
Directory	/workspace/19.clkmgr_frequency/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency_timeout.4167319135
Short name	T739
Test name
Test status
Simulation time	1414213889 ps
CPU time	5.94 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:24 PM PDT 24
Peak memory	200920 kb
Host	smart-b3f0ce0d-c8f5-4bc8-baff-09be46d86de5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167319135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t imeout.4167319135
Directory	/workspace/19.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/19.clkmgr_idle_intersig_mubi.1229545572
Short name	T161
Test name
Test status
Simulation time	87642744 ps
CPU time	1.01 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:27 PM PDT 24
Peak memory	200852 kb
Host	smart-1e11117d-f401-430e-881b-278abc24067d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229545572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.1229545572
Directory	/workspace/19.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.626833538
Short name	T429
Test name
Test status
Simulation time	284057333 ps
CPU time	1.56 seconds
Started	Mar 12 12:47:22 PM PDT 24
Finished	Mar 12 12:47:24 PM PDT 24
Peak memory	200724 kb
Host	smart-5e179132-38f6-4141-87f6-4cf4b9d6cb73
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626833538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.clkmgr_lc_clk_byp_req_intersig_mubi.626833538
Directory	/workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.1966877617
Short name	T642
Test name
Test status
Simulation time	16717862 ps
CPU time	0.79 seconds
Started	Mar 12 12:47:24 PM PDT 24
Finished	Mar 12 12:47:25 PM PDT 24
Peak memory	200756 kb
Host	smart-e2f7456d-48aa-4351-9f94-887a02cec9f8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966877617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.clkmgr_lc_ctrl_intersig_mubi.1966877617
Directory	/workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_peri.3221131697
Short name	T222
Test name
Test status
Simulation time	14293603 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:27 PM PDT 24
Peak memory	200680 kb
Host	smart-1e90ee11-f19d-4808-97aa-fa2a4d5a00cb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221131697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.3221131697
Directory	/workspace/19.clkmgr_peri/latest

Test location	/workspace/coverage/default/19.clkmgr_regwen.2451826944
Short name	T10
Test name
Test status
Simulation time	688921874 ps
CPU time	4.08 seconds
Started	Mar 12 12:47:17 PM PDT 24
Finished	Mar 12 12:47:21 PM PDT 24
Peak memory	201064 kb
Host	smart-4adf50ff-25ab-4502-8717-6e8759079495
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451826944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.2451826944
Directory	/workspace/19.clkmgr_regwen/latest

Test location	/workspace/coverage/default/19.clkmgr_smoke.2725951829
Short name	T657
Test name
Test status
Simulation time	22781428 ps
CPU time	0.86 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:19 PM PDT 24
Peak memory	200764 kb
Host	smart-03888532-a47f-46db-8b47-914ff3fc53e1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725951829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.2725951829
Directory	/workspace/19.clkmgr_smoke/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all.1881483455
Short name	T34
Test name
Test status
Simulation time	7009446378 ps
CPU time	52.8 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	201228 kb
Host	smart-06dadd9a-2454-4e02-845b-cd620f2e71fd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881483455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.1881483455
Directory	/workspace/19.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.4004530895
Short name	T635
Test name
Test status
Simulation time	12781195198 ps
CPU time	196.87 seconds
Started	Mar 12 12:47:29 PM PDT 24
Finished	Mar 12 12:50:46 PM PDT 24
Peak memory	214452 kb
Host	smart-d1b00c31-f525-43a7-966c-6b6aa7611d05
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4004530895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.4004530895
Directory	/workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.clkmgr_trans.1237482129
Short name	T816
Test name
Test status
Simulation time	42533105 ps
CPU time	0.99 seconds
Started	Mar 12 12:47:15 PM PDT 24
Finished	Mar 12 12:47:16 PM PDT 24
Peak memory	200868 kb
Host	smart-b918a2e4-1914-41b9-9fea-1c42b076ab31
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237482129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.1237482129
Directory	/workspace/19.clkmgr_trans/latest

Test location	/workspace/coverage/default/2.clkmgr_alert_test.1404609118
Short name	T380
Test name
Test status
Simulation time	18541881 ps
CPU time	0.83 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:46:44 PM PDT 24
Peak memory	200788 kb
Host	smart-89373645-1ff1-4cef-8983-910b142d5d53
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404609118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm gr_alert_test.1404609118
Directory	/workspace/2.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_status.3209502205
Short name	T145
Test name
Test status
Simulation time	14006105 ps
CPU time	0.69 seconds
Started	Mar 12 12:46:31 PM PDT 24
Finished	Mar 12 12:46:32 PM PDT 24
Peak memory	199544 kb
Host	smart-59241e40-40bb-4536-b0ac-9d9021501f61
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209502205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.3209502205
Directory	/workspace/2.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/2.clkmgr_div_intersig_mubi.1304229672
Short name	T422
Test name
Test status
Simulation time	98941898 ps
CPU time	1.04 seconds
Started	Mar 12 12:46:32 PM PDT 24
Finished	Mar 12 12:46:33 PM PDT 24
Peak memory	200768 kb
Host	smart-59f1eee3-137f-44d5-9bf2-c3567f1a71cd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304229672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.1304229672
Directory	/workspace/2.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_extclk.1020476769
Short name	T609
Test name
Test status
Simulation time	99928550 ps
CPU time	1.03 seconds
Started	Mar 12 12:46:31 PM PDT 24
Finished	Mar 12 12:46:33 PM PDT 24
Peak memory	200804 kb
Host	smart-0f21c585-af87-4152-8c42-5ca37bd4bd3d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020476769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1020476769
Directory	/workspace/2.clkmgr_extclk/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency.1652192869
Short name	T271
Test name
Test status
Simulation time	1277447742 ps
CPU time	9.91 seconds
Started	Mar 12 12:46:33 PM PDT 24
Finished	Mar 12 12:46:43 PM PDT 24
Peak memory	200700 kb
Host	smart-cf83b385-6b0b-45b6-98a5-fb3b4e08c48b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652192869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.1652192869
Directory	/workspace/2.clkmgr_frequency/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency_timeout.1893707084
Short name	T399
Test name
Test status
Simulation time	1215574677 ps
CPU time	8.54 seconds
Started	Mar 12 12:46:28 PM PDT 24
Finished	Mar 12 12:46:37 PM PDT 24
Peak memory	200748 kb
Host	smart-8e3c29a2-9415-402e-b7ca-2bde971f13ff
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893707084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti meout.1893707084
Directory	/workspace/2.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/2.clkmgr_idle_intersig_mubi.3176730199
Short name	T266
Test name
Test status
Simulation time	39385681 ps
CPU time	1.07 seconds
Started	Mar 12 12:46:35 PM PDT 24
Finished	Mar 12 12:46:36 PM PDT 24
Peak memory	200828 kb
Host	smart-809d5c0e-4d20-4971-a542-bc7b3bb25103
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176730199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.3176730199
Directory	/workspace/2.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.2577864708
Short name	T426
Test name
Test status
Simulation time	56341576 ps
CPU time	0.94 seconds
Started	Mar 12 12:46:41 PM PDT 24
Finished	Mar 12 12:46:43 PM PDT 24
Peak memory	200660 kb
Host	smart-a1a15d29-3e3a-411d-b906-c8114fc96a64
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577864708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_clk_byp_req_intersig_mubi.2577864708
Directory	/workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.3702520773
Short name	T583
Test name
Test status
Simulation time	30850252 ps
CPU time	0.91 seconds
Started	Mar 12 12:46:35 PM PDT 24
Finished	Mar 12 12:46:36 PM PDT 24
Peak memory	200748 kb
Host	smart-7128901b-da3f-449e-9eba-93788980536f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702520773 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_ctrl_intersig_mubi.3702520773
Directory	/workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_peri.2373856168
Short name	T608
Test name
Test status
Simulation time	67925489 ps
CPU time	0.87 seconds
Started	Mar 12 12:46:32 PM PDT 24
Finished	Mar 12 12:46:33 PM PDT 24
Peak memory	200676 kb
Host	smart-60f1d9a9-1fac-4092-a29d-f28d86af5010
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373856168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2373856168
Directory	/workspace/2.clkmgr_peri/latest

Test location	/workspace/coverage/default/2.clkmgr_regwen.4119111027
Short name	T339
Test name
Test status
Simulation time	1520333255 ps
CPU time	4.99 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:46:48 PM PDT 24
Peak memory	201016 kb
Host	smart-b4eb3d5e-15cd-4345-8f93-9fe8421128a1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119111027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.4119111027
Directory	/workspace/2.clkmgr_regwen/latest

Test location	/workspace/coverage/default/2.clkmgr_sec_cm.1312680733
Short name	T39
Test name
Test status
Simulation time	164950197 ps
CPU time	1.97 seconds
Started	Mar 12 12:46:39 PM PDT 24
Finished	Mar 12 12:46:43 PM PDT 24
Peak memory	215736 kb
Host	smart-7faeda15-3d5d-41d8-8403-6b1c2b6f4cfd
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312680733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg r_sec_cm.1312680733
Directory	/workspace/2.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/2.clkmgr_smoke.1303645751
Short name	T389
Test name
Test status
Simulation time	70786229 ps
CPU time	0.96 seconds
Started	Mar 12 12:46:36 PM PDT 24
Finished	Mar 12 12:46:37 PM PDT 24
Peak memory	200824 kb
Host	smart-8d0fdaa1-d321-4212-925a-8fb55313d406
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303645751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.1303645751
Directory	/workspace/2.clkmgr_smoke/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all.2467942
Short name	T328
Test name
Test status
Simulation time	2872881398 ps
CPU time	11.59 seconds
Started	Mar 12 12:46:29 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	201048 kb
Host	smart-ca86e713-9526-40a9-9acc-0ec45f67a823
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. clkmgr_stress_all.2467942
Directory	/workspace/2.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.3065506737
Short name	T124
Test name
Test status
Simulation time	79526163857 ps
CPU time	452.3 seconds
Started	Mar 12 12:46:31 PM PDT 24
Finished	Mar 12 12:54:04 PM PDT 24
Peak memory	210924 kb
Host	smart-a021b202-9b80-4ad6-a7f6-53d02fdaf9c6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3065506737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.3065506737
Directory	/workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.clkmgr_trans.208631870
Short name	T743
Test name
Test status
Simulation time	53488248 ps
CPU time	0.84 seconds
Started	Mar 12 12:46:29 PM PDT 24
Finished	Mar 12 12:46:30 PM PDT 24
Peak memory	200764 kb
Host	smart-bca242e5-a88c-4e44-8461-32680754b0b2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208631870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.208631870
Directory	/workspace/2.clkmgr_trans/latest

Test location	/workspace/coverage/default/20.clkmgr_alert_test.1274147608
Short name	T798
Test name
Test status
Simulation time	70726942 ps
CPU time	0.88 seconds
Started	Mar 12 12:47:30 PM PDT 24
Finished	Mar 12 12:47:31 PM PDT 24
Peak memory	200832 kb
Host	smart-ce6e0afe-60d4-4d7a-9381-7a328a4d2753
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274147608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk mgr_alert_test.1274147608
Directory	/workspace/20.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3834882292
Short name	T211
Test name
Test status
Simulation time	64789955 ps
CPU time	0.93 seconds
Started	Mar 12 12:47:20 PM PDT 24
Finished	Mar 12 12:47:21 PM PDT 24
Peak memory	200752 kb
Host	smart-e76195b7-775a-4899-acfe-5480ec4fbebc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834882292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.3834882292
Directory	/workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_status.4294156476
Short name	T737
Test name
Test status
Simulation time	12442712 ps
CPU time	0.66 seconds
Started	Mar 12 12:47:16 PM PDT 24
Finished	Mar 12 12:47:16 PM PDT 24
Peak memory	199756 kb
Host	smart-43a8a796-3258-4af2-aee6-95d140330029
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294156476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.4294156476
Directory	/workspace/20.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/20.clkmgr_div_intersig_mubi.3260037449
Short name	T627
Test name
Test status
Simulation time	14025256 ps
CPU time	0.71 seconds
Started	Mar 12 12:47:20 PM PDT 24
Finished	Mar 12 12:47:21 PM PDT 24
Peak memory	200812 kb
Host	smart-4aedab37-5561-4794-b83f-7754c0ca2b8a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260037449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.3260037449
Directory	/workspace/20.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_extclk.1266998972
Short name	T248
Test name
Test status
Simulation time	26672849 ps
CPU time	0.88 seconds
Started	Mar 12 12:47:23 PM PDT 24
Finished	Mar 12 12:47:24 PM PDT 24
Peak memory	200700 kb
Host	smart-ee3f94bd-f263-4f65-8437-f512457cd706
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266998972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.1266998972
Directory	/workspace/20.clkmgr_extclk/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency.2586622790
Short name	T772
Test name
Test status
Simulation time	673505015 ps
CPU time	5.33 seconds
Started	Mar 12 12:47:28 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200704 kb
Host	smart-25fc5b6a-676a-4b3b-a701-eb1bf04bdfd2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586622790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.2586622790
Directory	/workspace/20.clkmgr_frequency/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency_timeout.200572779
Short name	T587
Test name
Test status
Simulation time	866866550 ps
CPU time	4.81 seconds
Started	Mar 12 12:47:16 PM PDT 24
Finished	Mar 12 12:47:21 PM PDT 24
Peak memory	200908 kb
Host	smart-212aac3c-ad3b-4ee7-9225-fe88c7db6a8e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200572779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_ti meout.200572779
Directory	/workspace/20.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/20.clkmgr_idle_intersig_mubi.3125106884
Short name	T189
Test name
Test status
Simulation time	24145079 ps
CPU time	0.86 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:27 PM PDT 24
Peak memory	200788 kb
Host	smart-d19239fd-d512-45ea-abbb-01044fec2d88
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125106884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.3125106884
Directory	/workspace/20.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.2113769889
Short name	T314
Test name
Test status
Simulation time	15703111 ps
CPU time	0.73 seconds
Started	Mar 12 12:47:28 PM PDT 24
Finished	Mar 12 12:47:29 PM PDT 24
Peak memory	200784 kb
Host	smart-748d5ead-00aa-46c6-8498-37fd9c8fca90
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113769889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_clk_byp_req_intersig_mubi.2113769889
Directory	/workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.485863843
Short name	T322
Test name
Test status
Simulation time	44711774 ps
CPU time	0.82 seconds
Started	Mar 12 12:47:17 PM PDT 24
Finished	Mar 12 12:47:18 PM PDT 24
Peak memory	200812 kb
Host	smart-c081ba42-464c-4903-89e4-d41b8d28f14b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485863843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.clkmgr_lc_ctrl_intersig_mubi.485863843
Directory	/workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_peri.2024994391
Short name	T850
Test name
Test status
Simulation time	22220777 ps
CPU time	0.8 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:19 PM PDT 24
Peak memory	200716 kb
Host	smart-c3fce62c-7d43-41a7-b391-bbf390ae2366
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024994391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.2024994391
Directory	/workspace/20.clkmgr_peri/latest

Test location	/workspace/coverage/default/20.clkmgr_regwen.2365274975
Short name	T732
Test name
Test status
Simulation time	1050747001 ps
CPU time	4.01 seconds
Started	Mar 12 12:47:20 PM PDT 24
Finished	Mar 12 12:47:24 PM PDT 24
Peak memory	201052 kb
Host	smart-dbac1b72-d92f-499d-b4f8-d05ce25b40cb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365274975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.2365274975
Directory	/workspace/20.clkmgr_regwen/latest

Test location	/workspace/coverage/default/20.clkmgr_smoke.2943539190
Short name	T414
Test name
Test status
Simulation time	19880418 ps
CPU time	0.85 seconds
Started	Mar 12 12:47:34 PM PDT 24
Finished	Mar 12 12:47:35 PM PDT 24
Peak memory	200704 kb
Host	smart-0487c8f4-f963-4cab-9a46-a84b35b2bfd8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943539190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.2943539190
Directory	/workspace/20.clkmgr_smoke/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all.2950592518
Short name	T125
Test name
Test status
Simulation time	1630997570 ps
CPU time	7.62 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:26 PM PDT 24
Peak memory	200928 kb
Host	smart-e468ece3-9da0-43cb-ae31-5987b728b038
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950592518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.2950592518
Directory	/workspace/20.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.2988897727
Short name	T650
Test name
Test status
Simulation time	18015835694 ps
CPU time	309.39 seconds
Started	Mar 12 12:47:25 PM PDT 24
Finished	Mar 12 12:52:35 PM PDT 24
Peak memory	216940 kb
Host	smart-767b4eb7-cc2d-4bc3-acca-0edda75cf4a9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2988897727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.2988897727
Directory	/workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.clkmgr_trans.112523198
Short name	T679
Test name
Test status
Simulation time	28354334 ps
CPU time	0.92 seconds
Started	Mar 12 12:47:17 PM PDT 24
Finished	Mar 12 12:47:18 PM PDT 24
Peak memory	200808 kb
Host	smart-8a2019a9-c29b-4978-a237-a0559f5ac58a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112523198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.112523198
Directory	/workspace/20.clkmgr_trans/latest

Test location	/workspace/coverage/default/21.clkmgr_alert_test.1706774728
Short name	T455
Test name
Test status
Simulation time	61848743 ps
CPU time	0.82 seconds
Started	Mar 12 12:47:17 PM PDT 24
Finished	Mar 12 12:47:18 PM PDT 24
Peak memory	200864 kb
Host	smart-9855a29c-d0e5-42c8-ad7a-427b5bc14044
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706774728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk mgr_alert_test.1706774728
Directory	/workspace/21.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.4238880507
Short name	T87
Test name
Test status
Simulation time	16538402 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:19 PM PDT 24
Finished	Mar 12 12:47:20 PM PDT 24
Peak memory	200784 kb
Host	smart-fe24759c-f211-46af-9fc4-0dd7db892228
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238880507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.4238880507
Directory	/workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_status.1261953949
Short name	T147
Test name
Test status
Simulation time	49523005 ps
CPU time	0.8 seconds
Started	Mar 12 12:47:30 PM PDT 24
Finished	Mar 12 12:47:31 PM PDT 24
Peak memory	200756 kb
Host	smart-92ce5f91-6f81-414a-9522-4108a7fa1927
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261953949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.1261953949
Directory	/workspace/21.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/21.clkmgr_div_intersig_mubi.3705581211
Short name	T174
Test name
Test status
Simulation time	201160658 ps
CPU time	1.4 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200756 kb
Host	smart-31a99c46-09e1-4691-aae7-aac58f67fa2f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705581211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.3705581211
Directory	/workspace/21.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_extclk.1804793602
Short name	T468
Test name
Test status
Simulation time	21087859 ps
CPU time	0.84 seconds
Started	Mar 12 12:47:28 PM PDT 24
Finished	Mar 12 12:47:30 PM PDT 24
Peak memory	200700 kb
Host	smart-efd9a9ef-85d2-4a70-a743-bad519e04130
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804793602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.1804793602
Directory	/workspace/21.clkmgr_extclk/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency.434499617
Short name	T538
Test name
Test status
Simulation time	1479858305 ps
CPU time	6.83 seconds
Started	Mar 12 12:47:17 PM PDT 24
Finished	Mar 12 12:47:23 PM PDT 24
Peak memory	200816 kb
Host	smart-1237b61b-eaf8-4d84-b03c-5fef8bb80e5a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434499617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.434499617
Directory	/workspace/21.clkmgr_frequency/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency_timeout.2102154166
Short name	T809
Test name
Test status
Simulation time	756620233 ps
CPU time	3.37 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200864 kb
Host	smart-975ad557-19c7-4c36-a516-7908d0675672
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102154166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t imeout.2102154166
Directory	/workspace/21.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/21.clkmgr_idle_intersig_mubi.3435115629
Short name	T438
Test name
Test status
Simulation time	27238677 ps
CPU time	0.96 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:19 PM PDT 24
Peak memory	200812 kb
Host	smart-7d491299-f698-428f-bcef-7206b06edbff
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435115629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.3435115629
Directory	/workspace/21.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.4285564930
Short name	T796
Test name
Test status
Simulation time	25233160 ps
CPU time	0.9 seconds
Started	Mar 12 12:47:33 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200804 kb
Host	smart-a6d373a9-9fda-4e22-91be-a36c1168fac2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285564930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.clkmgr_lc_clk_byp_req_intersig_mubi.4285564930
Directory	/workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.3687799229
Short name	T160
Test name
Test status
Simulation time	57155213 ps
CPU time	0.97 seconds
Started	Mar 12 12:47:33 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200720 kb
Host	smart-d85754a7-a3e7-4b08-bb18-75ae5dacd6d8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687799229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.clkmgr_lc_ctrl_intersig_mubi.3687799229
Directory	/workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_peri.1999314715
Short name	T789
Test name
Test status
Simulation time	20486640 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:17 PM PDT 24
Finished	Mar 12 12:47:18 PM PDT 24
Peak memory	200780 kb
Host	smart-5ee436eb-b6ba-4fb9-afba-3dea2c647cfa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999314715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.1999314715
Directory	/workspace/21.clkmgr_peri/latest

Test location	/workspace/coverage/default/21.clkmgr_regwen.2456028796
Short name	T134
Test name
Test status
Simulation time	482283452 ps
CPU time	3.03 seconds
Started	Mar 12 12:47:27 PM PDT 24
Finished	Mar 12 12:47:30 PM PDT 24
Peak memory	200792 kb
Host	smart-fe983824-a3a6-4c49-87cd-e86af1f0747f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456028796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.2456028796
Directory	/workspace/21.clkmgr_regwen/latest

Test location	/workspace/coverage/default/21.clkmgr_smoke.4189751254
Short name	T841
Test name
Test status
Simulation time	20571051 ps
CPU time	0.87 seconds
Started	Mar 12 12:47:33 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200780 kb
Host	smart-67c72a36-8874-4998-ad13-232719605982
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189751254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.4189751254
Directory	/workspace/21.clkmgr_smoke/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all.539998952
Short name	T735
Test name
Test status
Simulation time	2815291488 ps
CPU time	21.66 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:40 PM PDT 24
Peak memory	201184 kb
Host	smart-f7fa36c9-8959-4aa5-86b0-09fd2740226d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539998952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.539998952
Directory	/workspace/21.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/21.clkmgr_trans.1431741749
Short name	T676
Test name
Test status
Simulation time	118964883 ps
CPU time	1.21 seconds
Started	Mar 12 12:47:25 PM PDT 24
Finished	Mar 12 12:47:26 PM PDT 24
Peak memory	200840 kb
Host	smart-1b63783f-be5c-4f80-b1de-538d6c6c7171
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431741749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.1431741749
Directory	/workspace/21.clkmgr_trans/latest

Test location	/workspace/coverage/default/22.clkmgr_alert_test.2489615075
Short name	T355
Test name
Test status
Simulation time	45554446 ps
CPU time	0.78 seconds
Started	Mar 12 12:47:35 PM PDT 24
Finished	Mar 12 12:47:36 PM PDT 24
Peak memory	200848 kb
Host	smart-57479471-5525-4e3c-9b84-226951624d44
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489615075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk mgr_alert_test.2489615075
Directory	/workspace/22.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.2766165445
Short name	T704
Test name
Test status
Simulation time	24032738 ps
CPU time	0.8 seconds
Started	Mar 12 12:47:39 PM PDT 24
Finished	Mar 12 12:47:40 PM PDT 24
Peak memory	200736 kb
Host	smart-11aa71d5-3e19-4ad9-9c56-87d9cb039bff
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766165445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.2766165445
Directory	/workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_status.2190477162
Short name	T150
Test name
Test status
Simulation time	38235461 ps
CPU time	0.8 seconds
Started	Mar 12 12:47:09 PM PDT 24
Finished	Mar 12 12:47:10 PM PDT 24
Peak memory	200760 kb
Host	smart-672fece0-5f74-4ef3-be9c-0a726ce3389b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190477162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.2190477162
Directory	/workspace/22.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/22.clkmgr_div_intersig_mubi.1438862113
Short name	T235
Test name
Test status
Simulation time	51425864 ps
CPU time	0.86 seconds
Started	Mar 12 12:47:36 PM PDT 24
Finished	Mar 12 12:47:37 PM PDT 24
Peak memory	200824 kb
Host	smart-6ab5ff86-b53f-4a33-a449-d93a917276f8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438862113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.1438862113
Directory	/workspace/22.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_extclk.2157765224
Short name	T295
Test name
Test status
Simulation time	81824961 ps
CPU time	1.03 seconds
Started	Mar 12 12:47:25 PM PDT 24
Finished	Mar 12 12:47:26 PM PDT 24
Peak memory	200816 kb
Host	smart-b93caa02-8c4b-49ba-8935-458cf65e7bbf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157765224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2157765224
Directory	/workspace/22.clkmgr_extclk/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency.3676707327
Short name	T373
Test name
Test status
Simulation time	441559534 ps
CPU time	4.07 seconds
Started	Mar 12 12:47:16 PM PDT 24
Finished	Mar 12 12:47:21 PM PDT 24
Peak memory	200816 kb
Host	smart-71f39f4f-7d94-46be-86a1-62a584a835e1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676707327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3676707327
Directory	/workspace/22.clkmgr_frequency/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency_timeout.2276810684
Short name	T281
Test name
Test status
Simulation time	619110915 ps
CPU time	3.86 seconds
Started	Mar 12 12:47:17 PM PDT 24
Finished	Mar 12 12:47:21 PM PDT 24
Peak memory	200872 kb
Host	smart-92a68444-5658-404c-bb72-a01c57d7beda
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276810684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t imeout.2276810684
Directory	/workspace/22.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/22.clkmgr_idle_intersig_mubi.423383996
Short name	T175
Test name
Test status
Simulation time	126180430 ps
CPU time	1.26 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:19 PM PDT 24
Peak memory	200816 kb
Host	smart-d9f42ef8-eafe-4d40-830e-28053f9af313
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423383996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.clkmgr_idle_intersig_mubi.423383996
Directory	/workspace/22.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2659956251
Short name	T585
Test name
Test status
Simulation time	57946388 ps
CPU time	0.88 seconds
Started	Mar 12 12:47:33 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200728 kb
Host	smart-6efa349b-f779-4807-ac5e-b6dcdb99f690
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659956251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_clk_byp_req_intersig_mubi.2659956251
Directory	/workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.247118757
Short name	T25
Test name
Test status
Simulation time	167449450 ps
CPU time	1.25 seconds
Started	Mar 12 12:47:23 PM PDT 24
Finished	Mar 12 12:47:25 PM PDT 24
Peak memory	200816 kb
Host	smart-f53eceb7-c528-4f24-bc38-fa9d1140adba
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247118757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.clkmgr_lc_ctrl_intersig_mubi.247118757
Directory	/workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_peri.3283620175
Short name	T297
Test name
Test status
Simulation time	115030316 ps
CPU time	1.02 seconds
Started	Mar 12 12:47:18 PM PDT 24
Finished	Mar 12 12:47:19 PM PDT 24
Peak memory	200680 kb
Host	smart-64c65b0c-9648-433d-8d0f-4fd40d79bcc0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283620175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.3283620175
Directory	/workspace/22.clkmgr_peri/latest

Test location	/workspace/coverage/default/22.clkmgr_regwen.3600021402
Short name	T831
Test name
Test status
Simulation time	1122908811 ps
CPU time	4.48 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:47:37 PM PDT 24
Peak memory	201056 kb
Host	smart-bdd1dfb4-078a-49cc-b0d4-c887db6eaaae
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600021402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.3600021402
Directory	/workspace/22.clkmgr_regwen/latest

Test location	/workspace/coverage/default/22.clkmgr_smoke.1138793988
Short name	T849
Test name
Test status
Simulation time	40977240 ps
CPU time	0.85 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200708 kb
Host	smart-b805ddd7-dbfe-4fc8-9f58-0b74f2abb94b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138793988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1138793988
Directory	/workspace/22.clkmgr_smoke/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all.647672791
Short name	T390
Test name
Test status
Simulation time	62339113 ps
CPU time	0.92 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200804 kb
Host	smart-aef37edb-44cb-49d8-9491-dd2954271665
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647672791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.647672791
Directory	/workspace/22.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/22.clkmgr_trans.3337350319
Short name	T484
Test name
Test status
Simulation time	81981354 ps
CPU time	1.04 seconds
Started	Mar 12 12:47:27 PM PDT 24
Finished	Mar 12 12:47:28 PM PDT 24
Peak memory	200792 kb
Host	smart-49acef48-516e-4550-ba32-d9cebf247bef
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337350319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.3337350319
Directory	/workspace/22.clkmgr_trans/latest

Test location	/workspace/coverage/default/23.clkmgr_alert_test.3496631615
Short name	T249
Test name
Test status
Simulation time	24738452 ps
CPU time	0.78 seconds
Started	Mar 12 12:47:33 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200900 kb
Host	smart-d4301a81-8002-406e-8a3f-42e6b35fd86f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496631615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk mgr_alert_test.3496631615
Directory	/workspace/23.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.1041255498
Short name	T290
Test name
Test status
Simulation time	27280503 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:30 PM PDT 24
Finished	Mar 12 12:47:31 PM PDT 24
Peak memory	200736 kb
Host	smart-d5a7f24b-62c1-49c4-9e4b-00cdd1081885
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041255498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.1041255498
Directory	/workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_status.4022205778
Short name	T45
Test name
Test status
Simulation time	17723358 ps
CPU time	0.75 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:27 PM PDT 24
Peak memory	199768 kb
Host	smart-f6816a8c-e0f8-47e1-bd39-1221778ae508
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022205778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.4022205778
Directory	/workspace/23.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/23.clkmgr_div_intersig_mubi.177706306
Short name	T260
Test name
Test status
Simulation time	102680448 ps
CPU time	0.96 seconds
Started	Mar 12 12:47:29 PM PDT 24
Finished	Mar 12 12:47:31 PM PDT 24
Peak memory	200704 kb
Host	smart-27599dee-3f08-4e3a-8f5a-05eeea4c4e8a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177706306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.clkmgr_div_intersig_mubi.177706306
Directory	/workspace/23.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_extclk.940123799
Short name	T741
Test name
Test status
Simulation time	23535301 ps
CPU time	0.74 seconds
Started	Mar 12 12:47:27 PM PDT 24
Finished	Mar 12 12:47:28 PM PDT 24
Peak memory	200656 kb
Host	smart-9cef1430-69b1-401a-96d4-624e9ee4093a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940123799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.940123799
Directory	/workspace/23.clkmgr_extclk/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency.2885100165
Short name	T107
Test name
Test status
Simulation time	2489581279 ps
CPU time	14.01 seconds
Started	Mar 12 12:47:29 PM PDT 24
Finished	Mar 12 12:47:43 PM PDT 24
Peak memory	201068 kb
Host	smart-503e8581-813f-4247-be85-930ce39a8be7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885100165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.2885100165
Directory	/workspace/23.clkmgr_frequency/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency_timeout.903429058
Short name	T715
Test name
Test status
Simulation time	164917329 ps
CPU time	1.27 seconds
Started	Mar 12 12:47:35 PM PDT 24
Finished	Mar 12 12:47:37 PM PDT 24
Peak memory	200900 kb
Host	smart-cc0a30b0-fe8f-4227-8271-aa3a12ec58df
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903429058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_ti meout.903429058
Directory	/workspace/23.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/23.clkmgr_idle_intersig_mubi.2599500445
Short name	T334
Test name
Test status
Simulation time	31092861 ps
CPU time	0.92 seconds
Started	Mar 12 12:47:23 PM PDT 24
Finished	Mar 12 12:47:24 PM PDT 24
Peak memory	200820 kb
Host	smart-2dd2c9ce-1f61-4e9f-9e49-f8f5318087ff
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599500445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.2599500445
Directory	/workspace/23.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.3535274918
Short name	T412
Test name
Test status
Simulation time	36270682 ps
CPU time	0.87 seconds
Started	Mar 12 12:47:24 PM PDT 24
Finished	Mar 12 12:47:25 PM PDT 24
Peak memory	200760 kb
Host	smart-3821cd18-f893-4b59-bdfc-75fbddb96cff
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535274918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_clk_byp_req_intersig_mubi.3535274918
Directory	/workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.4248632791
Short name	T454
Test name
Test status
Simulation time	17959946 ps
CPU time	0.79 seconds
Started	Mar 12 12:47:37 PM PDT 24
Finished	Mar 12 12:47:38 PM PDT 24
Peak memory	199916 kb
Host	smart-2eb4f5fb-2c8e-4e85-a8cc-6d4824e78abc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248632791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_ctrl_intersig_mubi.4248632791
Directory	/workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_peri.3950438512
Short name	T793
Test name
Test status
Simulation time	29246733 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200680 kb
Host	smart-5f5e0d9c-3f79-42a8-aa27-6817246e6eb5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950438512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.3950438512
Directory	/workspace/23.clkmgr_peri/latest

Test location	/workspace/coverage/default/23.clkmgr_regwen.2915008601
Short name	T720
Test name
Test status
Simulation time	433073748 ps
CPU time	2.13 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200756 kb
Host	smart-a9879625-176c-4872-8a8e-e59abfa30209
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915008601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.2915008601
Directory	/workspace/23.clkmgr_regwen/latest

Test location	/workspace/coverage/default/23.clkmgr_smoke.2536775890
Short name	T828
Test name
Test status
Simulation time	64022976 ps
CPU time	0.96 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:27 PM PDT 24
Peak memory	200848 kb
Host	smart-1fd4c24e-5bc7-4095-b90e-670a5aaf9008
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536775890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.2536775890
Directory	/workspace/23.clkmgr_smoke/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all.899181562
Short name	T756
Test name
Test status
Simulation time	9265675448 ps
CPU time	38.04 seconds
Started	Mar 12 12:47:34 PM PDT 24
Finished	Mar 12 12:48:12 PM PDT 24
Peak memory	201200 kb
Host	smart-502414e8-941a-4634-a4dd-4fa3607488be
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899181562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.899181562
Directory	/workspace/23.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.2908262041
Short name	T845
Test name
Test status
Simulation time	95561441715 ps
CPU time	662.65 seconds
Started	Mar 12 12:47:25 PM PDT 24
Finished	Mar 12 12:58:28 PM PDT 24
Peak memory	209528 kb
Host	smart-30fab7d6-0f0e-4869-8aa9-6222f360dccb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2908262041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.2908262041
Directory	/workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.clkmgr_trans.2140524675
Short name	T361
Test name
Test status
Simulation time	36192218 ps
CPU time	0.86 seconds
Started	Mar 12 12:47:35 PM PDT 24
Finished	Mar 12 12:47:36 PM PDT 24
Peak memory	200816 kb
Host	smart-31fa4959-1f92-4f1a-9e2d-8a6a09390fba
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140524675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2140524675
Directory	/workspace/23.clkmgr_trans/latest

Test location	/workspace/coverage/default/24.clkmgr_alert_test.3968715914
Short name	T31
Test name
Test status
Simulation time	17074521 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:33 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200480 kb
Host	smart-16c07a08-cd9e-4f59-b80a-cdb7c09a317e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968715914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk mgr_alert_test.3968715914
Directory	/workspace/24.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.1202800919
Short name	T23
Test name
Test status
Simulation time	22902662 ps
CPU time	0.83 seconds
Started	Mar 12 12:47:28 PM PDT 24
Finished	Mar 12 12:47:29 PM PDT 24
Peak memory	200784 kb
Host	smart-cd122779-fc0e-4455-b434-6b65c671d92a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202800919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.1202800919
Directory	/workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_status.727029468
Short name	T378
Test name
Test status
Simulation time	17059466 ps
CPU time	0.69 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:47:32 PM PDT 24
Peak memory	199756 kb
Host	smart-7fce71f1-1d9c-4a37-ba21-d6043ffa6dbb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727029468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.727029468
Directory	/workspace/24.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/24.clkmgr_div_intersig_mubi.3101130596
Short name	T406
Test name
Test status
Simulation time	20442971 ps
CPU time	0.82 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200848 kb
Host	smart-fbb62b90-1ad3-4b2e-8ca2-6f2ab58de757
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101130596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.3101130596
Directory	/workspace/24.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_extclk.1832055816
Short name	T225
Test name
Test status
Simulation time	25636059 ps
CPU time	0.91 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200784 kb
Host	smart-5b800deb-15d9-49ca-bc1e-f099dc66fb07
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832055816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.1832055816
Directory	/workspace/24.clkmgr_extclk/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency.2923305309
Short name	T448
Test name
Test status
Simulation time	2254562993 ps
CPU time	9.93 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:36 PM PDT 24
Peak memory	201052 kb
Host	smart-a8841561-8618-49bc-a22f-35d7a386913a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923305309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.2923305309
Directory	/workspace/24.clkmgr_frequency/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency_timeout.3851672916
Short name	T419
Test name
Test status
Simulation time	2297443025 ps
CPU time	16.18 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:47:48 PM PDT 24
Peak memory	201124 kb
Host	smart-ab9658f7-f16b-4b92-808d-35d258ec2f21
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851672916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t imeout.3851672916
Directory	/workspace/24.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/24.clkmgr_idle_intersig_mubi.1980413663
Short name	T643
Test name
Test status
Simulation time	66480915 ps
CPU time	1.09 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:28 PM PDT 24
Peak memory	200848 kb
Host	smart-15ca002e-7483-4406-a6e4-a4c1abecadc7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980413663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.1980413663
Directory	/workspace/24.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.49338800
Short name	T788
Test name
Test status
Simulation time	41509352 ps
CPU time	0.8 seconds
Started	Mar 12 12:47:28 PM PDT 24
Finished	Mar 12 12:47:29 PM PDT 24
Peak memory	200708 kb
Host	smart-41dd5147-4e67-4124-9983-caf6c4590e83
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49338800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_clk_byp_req_intersig_mubi.49338800
Directory	/workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.3924592109
Short name	T284
Test name
Test status
Simulation time	26847127 ps
CPU time	0.78 seconds
Started	Mar 12 12:47:25 PM PDT 24
Finished	Mar 12 12:47:26 PM PDT 24
Peak memory	200768 kb
Host	smart-2b656dec-8707-4f97-bf69-7341e9a06719
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924592109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_ctrl_intersig_mubi.3924592109
Directory	/workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_peri.3873963446
Short name	T241
Test name
Test status
Simulation time	27726274 ps
CPU time	0.79 seconds
Started	Mar 12 12:47:23 PM PDT 24
Finished	Mar 12 12:47:24 PM PDT 24
Peak memory	200784 kb
Host	smart-379cef23-f307-432d-9c9d-1f35396c1892
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873963446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.3873963446
Directory	/workspace/24.clkmgr_peri/latest

Test location	/workspace/coverage/default/24.clkmgr_regwen.3542980876
Short name	T669
Test name
Test status
Simulation time	1139261692 ps
CPU time	4.12 seconds
Started	Mar 12 12:47:36 PM PDT 24
Finished	Mar 12 12:47:40 PM PDT 24
Peak memory	200908 kb
Host	smart-35152fc3-1824-4d74-bd0d-6984b2eb56b5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542980876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3542980876
Directory	/workspace/24.clkmgr_regwen/latest

Test location	/workspace/coverage/default/24.clkmgr_smoke.2942364984
Short name	T199
Test name
Test status
Simulation time	158737143 ps
CPU time	1.21 seconds
Started	Mar 12 12:47:28 PM PDT 24
Finished	Mar 12 12:47:29 PM PDT 24
Peak memory	200812 kb
Host	smart-a6e56d70-4f15-498e-ab1d-6be4a2b541e5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942364984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.2942364984
Directory	/workspace/24.clkmgr_smoke/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all.2875724412
Short name	T629
Test name
Test status
Simulation time	4209419819 ps
CPU time	16.94 seconds
Started	Mar 12 12:47:35 PM PDT 24
Finished	Mar 12 12:47:53 PM PDT 24
Peak memory	201108 kb
Host	smart-0cb6ebf5-f3f1-449a-99f4-f03ff3b17099
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875724412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.2875724412
Directory	/workspace/24.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.3738935014
Short name	T442
Test name
Test status
Simulation time	61708913689 ps
CPU time	419.79 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:54:31 PM PDT 24
Peak memory	209524 kb
Host	smart-a112ffab-c871-45e7-a24e-2339345027a0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3738935014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.3738935014
Directory	/workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.clkmgr_trans.3850195919
Short name	T632
Test name
Test status
Simulation time	26622134 ps
CPU time	0.9 seconds
Started	Mar 12 12:47:24 PM PDT 24
Finished	Mar 12 12:47:25 PM PDT 24
Peak memory	200840 kb
Host	smart-1a58efdd-dc50-40a4-bf33-b7150d63962c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850195919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.3850195919
Directory	/workspace/24.clkmgr_trans/latest

Test location	/workspace/coverage/default/25.clkmgr_alert_test.364867481
Short name	T769
Test name
Test status
Simulation time	17957283 ps
CPU time	0.75 seconds
Started	Mar 12 12:47:28 PM PDT 24
Finished	Mar 12 12:47:29 PM PDT 24
Peak memory	200832 kb
Host	smart-967c8452-9bcc-4d7f-8ccc-d927432c2d0d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364867481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkm gr_alert_test.364867481
Directory	/workspace/25.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.3425066056
Short name	T72
Test name
Test status
Simulation time	27109343 ps
CPU time	0.89 seconds
Started	Mar 12 12:47:28 PM PDT 24
Finished	Mar 12 12:47:29 PM PDT 24
Peak memory	200760 kb
Host	smart-4e6e97fa-3871-4b79-af5a-7ea152c910ec
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425066056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.3425066056
Directory	/workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_status.3601266755
Short name	T306
Test name
Test status
Simulation time	19825787 ps
CPU time	0.69 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200792 kb
Host	smart-b4badd3b-b8e7-4867-a962-d537bf0fcdc9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601266755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.3601266755
Directory	/workspace/25.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/25.clkmgr_div_intersig_mubi.1261743860
Short name	T665
Test name
Test status
Simulation time	19615531 ps
CPU time	0.79 seconds
Started	Mar 12 12:47:27 PM PDT 24
Finished	Mar 12 12:47:28 PM PDT 24
Peak memory	200732 kb
Host	smart-ccd5d571-1e32-46a5-9156-0b13bad4566f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261743860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.1261743860
Directory	/workspace/25.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_extclk.3985431221
Short name	T612
Test name
Test status
Simulation time	118847032 ps
CPU time	1.1 seconds
Started	Mar 12 12:47:37 PM PDT 24
Finished	Mar 12 12:47:39 PM PDT 24
Peak memory	200032 kb
Host	smart-bb315585-d03d-4e5c-8f7e-c4cd3be66c4e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985431221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3985431221
Directory	/workspace/25.clkmgr_extclk/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency.3194155915
Short name	T678
Test name
Test status
Simulation time	1403466858 ps
CPU time	8.2 seconds
Started	Mar 12 12:47:24 PM PDT 24
Finished	Mar 12 12:47:32 PM PDT 24
Peak memory	200816 kb
Host	smart-9ab01495-17c0-43e0-a7d3-bf8ddfa645e0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194155915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.3194155915
Directory	/workspace/25.clkmgr_frequency/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency_timeout.1015797743
Short name	T230
Test name
Test status
Simulation time	2455492899 ps
CPU time	8.65 seconds
Started	Mar 12 12:47:29 PM PDT 24
Finished	Mar 12 12:47:37 PM PDT 24
Peak memory	201120 kb
Host	smart-4b713769-2f4b-43de-8920-70cbc3612050
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015797743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t imeout.1015797743
Directory	/workspace/25.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/25.clkmgr_idle_intersig_mubi.1280228715
Short name	T610
Test name
Test status
Simulation time	86108986 ps
CPU time	1.01 seconds
Started	Mar 12 12:47:30 PM PDT 24
Finished	Mar 12 12:47:32 PM PDT 24
Peak memory	200280 kb
Host	smart-3ae001a3-8891-49af-a940-23b755ff8352
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280228715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.1280228715
Directory	/workspace/25.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.2243088667
Short name	T501
Test name
Test status
Simulation time	12968114 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:39 PM PDT 24
Finished	Mar 12 12:47:41 PM PDT 24
Peak memory	200644 kb
Host	smart-d5ef525d-044a-4db6-a2f5-c048a4323a03
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243088667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_clk_byp_req_intersig_mubi.2243088667
Directory	/workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.4254781990
Short name	T19
Test name
Test status
Simulation time	26693556 ps
CPU time	0.75 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:27 PM PDT 24
Peak memory	200824 kb
Host	smart-92ccea78-8503-4d48-9642-b71a503c98b4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254781990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_ctrl_intersig_mubi.4254781990
Directory	/workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_peri.222063359
Short name	T24
Test name
Test status
Simulation time	54792241 ps
CPU time	0.88 seconds
Started	Mar 12 12:47:24 PM PDT 24
Finished	Mar 12 12:47:25 PM PDT 24
Peak memory	200716 kb
Host	smart-34637f91-380f-4cbc-9ad8-a6ea831714cf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222063359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.222063359
Directory	/workspace/25.clkmgr_peri/latest

Test location	/workspace/coverage/default/25.clkmgr_regwen.3548269905
Short name	T570
Test name
Test status
Simulation time	520010896 ps
CPU time	3.33 seconds
Started	Mar 12 12:47:41 PM PDT 24
Finished	Mar 12 12:47:45 PM PDT 24
Peak memory	200916 kb
Host	smart-95ae13e3-992f-476d-85b2-5ddf4fcbc611
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548269905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3548269905
Directory	/workspace/25.clkmgr_regwen/latest

Test location	/workspace/coverage/default/25.clkmgr_smoke.1687715953
Short name	T447
Test name
Test status
Simulation time	20620796 ps
CPU time	0.84 seconds
Started	Mar 12 12:47:30 PM PDT 24
Finished	Mar 12 12:47:32 PM PDT 24
Peak memory	200820 kb
Host	smart-2dacee90-9dc2-4fd3-90d5-c8e5c9a30000
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687715953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.1687715953
Directory	/workspace/25.clkmgr_smoke/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all.716137530
Short name	T311
Test name
Test status
Simulation time	5414842891 ps
CPU time	19.58 seconds
Started	Mar 12 12:47:33 PM PDT 24
Finished	Mar 12 12:47:53 PM PDT 24
Peak memory	201184 kb
Host	smart-89271f94-f2a7-4c99-a8d7-7ee8abf24d47
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716137530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.716137530
Directory	/workspace/25.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.1380286486
Short name	T138
Test name
Test status
Simulation time	94646025747 ps
CPU time	558.65 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:56:51 PM PDT 24
Peak memory	209564 kb
Host	smart-47ebd91d-1435-41b6-906b-5626998f836b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1380286486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.1380286486
Directory	/workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.clkmgr_trans.1842468545
Short name	T29
Test name
Test status
Simulation time	42318430 ps
CPU time	0.89 seconds
Started	Mar 12 12:47:36 PM PDT 24
Finished	Mar 12 12:47:37 PM PDT 24
Peak memory	200628 kb
Host	smart-f1c86aa6-ed6c-475a-890c-b79ba2ea7082
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842468545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.1842468545
Directory	/workspace/25.clkmgr_trans/latest

Test location	/workspace/coverage/default/26.clkmgr_alert_test.1127701835
Short name	T722
Test name
Test status
Simulation time	99075199 ps
CPU time	1.06 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200880 kb
Host	smart-6dd20427-50a4-42a6-bafc-695f26267ea1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127701835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk mgr_alert_test.1127701835
Directory	/workspace/26.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.2197594198
Short name	T286
Test name
Test status
Simulation time	27614399 ps
CPU time	0.92 seconds
Started	Mar 12 12:47:33 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200808 kb
Host	smart-080afe61-4011-460d-9722-bb4706d0dbfa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197594198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.2197594198
Directory	/workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_status.2217582857
Short name	T401
Test name
Test status
Simulation time	18775034 ps
CPU time	0.71 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:47:31 PM PDT 24
Peak memory	199764 kb
Host	smart-52045f5d-de86-4a77-b1fe-913e0916af7f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217582857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.2217582857
Directory	/workspace/26.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/26.clkmgr_div_intersig_mubi.1362362181
Short name	T239
Test name
Test status
Simulation time	181243649 ps
CPU time	1.33 seconds
Started	Mar 12 12:47:24 PM PDT 24
Finished	Mar 12 12:47:25 PM PDT 24
Peak memory	200744 kb
Host	smart-a27e7f99-10ce-4cd2-9d72-5ffe9db202a7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362362181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.1362362181
Directory	/workspace/26.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_extclk.483240799
Short name	T413
Test name
Test status
Simulation time	110993007 ps
CPU time	1.18 seconds
Started	Mar 12 12:47:36 PM PDT 24
Finished	Mar 12 12:47:37 PM PDT 24
Peak memory	200708 kb
Host	smart-aa560068-74b8-44bb-af09-465455a5291a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483240799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.483240799
Directory	/workspace/26.clkmgr_extclk/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency.358424782
Short name	T593
Test name
Test status
Simulation time	2355542350 ps
CPU time	17.69 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:44 PM PDT 24
Peak memory	201108 kb
Host	smart-06b39b4f-e547-405e-afcc-1c2be3d5f61c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358424782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.358424782
Directory	/workspace/26.clkmgr_frequency/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency_timeout.1886571408
Short name	T810
Test name
Test status
Simulation time	858601314 ps
CPU time	6.77 seconds
Started	Mar 12 12:47:27 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200884 kb
Host	smart-ca4eec25-cffb-4f02-8aad-4f17e48fbc64
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886571408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t imeout.1886571408
Directory	/workspace/26.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/26.clkmgr_idle_intersig_mubi.146419110
Short name	T844
Test name
Test status
Simulation time	53896233 ps
CPU time	1.02 seconds
Started	Mar 12 12:47:33 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200456 kb
Host	smart-446f93df-75e5-41ec-92af-d6765fa111c0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146419110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.clkmgr_idle_intersig_mubi.146419110
Directory	/workspace/26.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.228462701
Short name	T444
Test name
Test status
Simulation time	21163333 ps
CPU time	0.8 seconds
Started	Mar 12 12:47:28 PM PDT 24
Finished	Mar 12 12:47:29 PM PDT 24
Peak memory	200720 kb
Host	smart-078803c0-6607-4145-91a5-67ec00c9b4fd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228462701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.clkmgr_lc_clk_byp_req_intersig_mubi.228462701
Directory	/workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.42135418
Short name	T826
Test name
Test status
Simulation time	109143462 ps
CPU time	1.11 seconds
Started	Mar 12 12:47:35 PM PDT 24
Finished	Mar 12 12:47:36 PM PDT 24
Peak memory	200828 kb
Host	smart-a06f4bc0-909e-4e4d-bf63-41bea3607885
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42135418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_ctrl_intersig_mubi.42135418
Directory	/workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_peri.294774886
Short name	T304
Test name
Test status
Simulation time	35062137 ps
CPU time	0.74 seconds
Started	Mar 12 12:47:35 PM PDT 24
Finished	Mar 12 12:47:36 PM PDT 24
Peak memory	200636 kb
Host	smart-e57dfe7c-4d98-40dc-83e7-bc24b2f3cb91
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294774886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.294774886
Directory	/workspace/26.clkmgr_peri/latest

Test location	/workspace/coverage/default/26.clkmgr_regwen.3190874748
Short name	T783
Test name
Test status
Simulation time	203136977 ps
CPU time	1.27 seconds
Started	Mar 12 12:47:41 PM PDT 24
Finished	Mar 12 12:47:43 PM PDT 24
Peak memory	200808 kb
Host	smart-b5c03301-ec9a-4b12-b5e7-1362561eb7b4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190874748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.3190874748
Directory	/workspace/26.clkmgr_regwen/latest

Test location	/workspace/coverage/default/26.clkmgr_smoke.3883319904
Short name	T663
Test name
Test status
Simulation time	47613358 ps
CPU time	0.87 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200860 kb
Host	smart-d4c3be5b-848f-424a-a9a2-e97201393236
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883319904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.3883319904
Directory	/workspace/26.clkmgr_smoke/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all.671261006
Short name	T418
Test name
Test status
Simulation time	5520986763 ps
CPU time	41 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:48:13 PM PDT 24
Peak memory	201220 kb
Host	smart-020cb729-3257-4655-aa92-48b32e17c5ef
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671261006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.671261006
Directory	/workspace/26.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.1090048928
Short name	T139
Test name
Test status
Simulation time	14330753764 ps
CPU time	192.82 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:50:45 PM PDT 24
Peak memory	215260 kb
Host	smart-7a4b2147-d7f1-44b1-86a5-ec62d642f7d4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1090048928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.1090048928
Directory	/workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.clkmgr_trans.2785464906
Short name	T706
Test name
Test status
Simulation time	36071202 ps
CPU time	1.05 seconds
Started	Mar 12 12:47:30 PM PDT 24
Finished	Mar 12 12:47:32 PM PDT 24
Peak memory	200228 kb
Host	smart-19e7cf54-fa8b-4585-ae03-5f0e1e28ec33
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785464906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.2785464906
Directory	/workspace/26.clkmgr_trans/latest

Test location	/workspace/coverage/default/27.clkmgr_alert_test.1929958642
Short name	T251
Test name
Test status
Simulation time	25917759 ps
CPU time	0.79 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:47:32 PM PDT 24
Peak memory	200876 kb
Host	smart-7c2a4252-3176-4752-8e6f-d529a86ba3db
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929958642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk mgr_alert_test.1929958642
Directory	/workspace/27.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1215475894
Short name	T127
Test name
Test status
Simulation time	53311282 ps
CPU time	0.99 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:27 PM PDT 24
Peak memory	200760 kb
Host	smart-b4686593-c1fd-4d2a-acf0-2d20adac075e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215475894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.1215475894
Directory	/workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_status.507289783
Short name	T591
Test name
Test status
Simulation time	44415714 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:33 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200788 kb
Host	smart-14620332-c60a-4ff2-ba88-ff82318ee822
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507289783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.507289783
Directory	/workspace/27.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/27.clkmgr_div_intersig_mubi.1377482724
Short name	T698
Test name
Test status
Simulation time	47796942 ps
CPU time	0.92 seconds
Started	Mar 12 12:47:46 PM PDT 24
Finished	Mar 12 12:47:47 PM PDT 24
Peak memory	200724 kb
Host	smart-9a167273-e08d-40fc-840e-69baf9246e04
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377482724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.1377482724
Directory	/workspace/27.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_extclk.3059995244
Short name	T272
Test name
Test status
Simulation time	38804520 ps
CPU time	0.86 seconds
Started	Mar 12 12:47:30 PM PDT 24
Finished	Mar 12 12:47:32 PM PDT 24
Peak memory	200728 kb
Host	smart-46f91e51-88a3-4a7e-a990-5f00bf31b2b0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059995244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.3059995244
Directory	/workspace/27.clkmgr_extclk/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency.4025779846
Short name	T683
Test name
Test status
Simulation time	329313119 ps
CPU time	2.13 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200808 kb
Host	smart-f8a39ac0-8fba-4cfc-82e7-cec2b143414e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025779846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.4025779846
Directory	/workspace/27.clkmgr_frequency/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency_timeout.3834835492
Short name	T231
Test name
Test status
Simulation time	1093658646 ps
CPU time	8.32 seconds
Started	Mar 12 12:47:24 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200856 kb
Host	smart-ed1bf07b-e223-4751-9a3b-0302ff360c90
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834835492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t imeout.3834835492
Directory	/workspace/27.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/27.clkmgr_idle_intersig_mubi.2425310404
Short name	T751
Test name
Test status
Simulation time	83666259 ps
CPU time	1.03 seconds
Started	Mar 12 12:47:27 PM PDT 24
Finished	Mar 12 12:47:28 PM PDT 24
Peak memory	200792 kb
Host	smart-e305d112-5ac5-48be-aa4a-78d8f2c79c3d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425310404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.2425310404
Directory	/workspace/27.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.524554278
Short name	T510
Test name
Test status
Simulation time	40815276 ps
CPU time	0.94 seconds
Started	Mar 12 12:47:34 PM PDT 24
Finished	Mar 12 12:47:35 PM PDT 24
Peak memory	200692 kb
Host	smart-c791fbf6-16c6-4632-ae21-05f00c021f49
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524554278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.clkmgr_lc_clk_byp_req_intersig_mubi.524554278
Directory	/workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.3737588711
Short name	T363
Test name
Test status
Simulation time	29343180 ps
CPU time	0.87 seconds
Started	Mar 12 12:47:25 PM PDT 24
Finished	Mar 12 12:47:26 PM PDT 24
Peak memory	200840 kb
Host	smart-b0834b9c-0bd5-49b0-84e7-f9313a2de17c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737588711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.clkmgr_lc_ctrl_intersig_mubi.3737588711
Directory	/workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_peri.3795830130
Short name	T641
Test name
Test status
Simulation time	17658458 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:27 PM PDT 24
Peak memory	200668 kb
Host	smart-a4846c18-2118-49a3-93a3-4ac988764107
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795830130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.3795830130
Directory	/workspace/27.clkmgr_peri/latest

Test location	/workspace/coverage/default/27.clkmgr_regwen.4047221906
Short name	T217
Test name
Test status
Simulation time	57790584 ps
CPU time	0.84 seconds
Started	Mar 12 12:47:26 PM PDT 24
Finished	Mar 12 12:47:27 PM PDT 24
Peak memory	200816 kb
Host	smart-eef8d82c-bca0-4f3a-8350-b9af8f8f36ed
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047221906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.4047221906
Directory	/workspace/27.clkmgr_regwen/latest

Test location	/workspace/coverage/default/27.clkmgr_smoke.3701333068
Short name	T333
Test name
Test status
Simulation time	56302681 ps
CPU time	0.91 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:47:32 PM PDT 24
Peak memory	200812 kb
Host	smart-3e308ac3-76ec-4625-8f36-2c42fa01bb4b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701333068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.3701333068
Directory	/workspace/27.clkmgr_smoke/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all.3379101952
Short name	T1
Test name
Test status
Simulation time	5160681046 ps
CPU time	38.01 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:48:10 PM PDT 24
Peak memory	201248 kb
Host	smart-8aafdf5d-c561-443a-bedc-22df70499cf6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379101952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.3379101952
Directory	/workspace/27.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.136258166
Short name	T477
Test name
Test status
Simulation time	213170582497 ps
CPU time	1456.02 seconds
Started	Mar 12 12:47:28 PM PDT 24
Finished	Mar 12 01:11:44 PM PDT 24
Peak memory	217188 kb
Host	smart-8e9db2d8-5e33-4762-92b8-a6896611880f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=136258166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.136258166
Directory	/workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.clkmgr_trans.1832459398
Short name	T245
Test name
Test status
Simulation time	43528178 ps
CPU time	1.05 seconds
Started	Mar 12 12:47:27 PM PDT 24
Finished	Mar 12 12:47:28 PM PDT 24
Peak memory	200824 kb
Host	smart-a8394490-9078-4508-88bc-7845fc1547ad
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832459398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.1832459398
Directory	/workspace/27.clkmgr_trans/latest

Test location	/workspace/coverage/default/28.clkmgr_alert_test.3764291905
Short name	T326
Test name
Test status
Simulation time	12430706 ps
CPU time	0.73 seconds
Started	Mar 12 12:47:35 PM PDT 24
Finished	Mar 12 12:47:36 PM PDT 24
Peak memory	200800 kb
Host	smart-a0a63a64-15a2-45f9-9f46-531bc5d9379f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764291905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk mgr_alert_test.3764291905
Directory	/workspace/28.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.953241568
Short name	T782
Test name
Test status
Simulation time	35873382 ps
CPU time	0.76 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200808 kb
Host	smart-91704cb5-0f99-4d49-ac6d-04a20d258573
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953241568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.953241568
Directory	/workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_status.1318495240
Short name	T364
Test name
Test status
Simulation time	41593811 ps
CPU time	0.73 seconds
Started	Mar 12 12:47:39 PM PDT 24
Finished	Mar 12 12:47:40 PM PDT 24
Peak memory	200756 kb
Host	smart-da97b533-8a39-4889-982d-373f4ed05261
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318495240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.1318495240
Directory	/workspace/28.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/28.clkmgr_div_intersig_mubi.1944621702
Short name	T43
Test name
Test status
Simulation time	20747180 ps
CPU time	0.72 seconds
Started	Mar 12 12:47:38 PM PDT 24
Finished	Mar 12 12:47:40 PM PDT 24
Peak memory	200504 kb
Host	smart-38628771-3c1c-4b7c-b97f-03bf15fb168a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944621702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.1944621702
Directory	/workspace/28.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_extclk.180240010
Short name	T344
Test name
Test status
Simulation time	80363884 ps
CPU time	1.01 seconds
Started	Mar 12 12:47:39 PM PDT 24
Finished	Mar 12 12:47:41 PM PDT 24
Peak memory	200804 kb
Host	smart-dcdd3c08-3c1e-4eb9-87de-596bd4572fc1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180240010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.180240010
Directory	/workspace/28.clkmgr_extclk/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency.3652144466
Short name	T653
Test name
Test status
Simulation time	1402130871 ps
CPU time	7.73 seconds
Started	Mar 12 12:47:33 PM PDT 24
Finished	Mar 12 12:47:40 PM PDT 24
Peak memory	200856 kb
Host	smart-a9ae1724-1f02-42b2-b7e7-e7acacb5c539
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652144466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.3652144466
Directory	/workspace/28.clkmgr_frequency/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency_timeout.1591198845
Short name	T600
Test name
Test status
Simulation time	735464176 ps
CPU time	5.27 seconds
Started	Mar 12 12:47:36 PM PDT 24
Finished	Mar 12 12:47:42 PM PDT 24
Peak memory	200652 kb
Host	smart-bdc70417-6330-463b-8373-09148fd54044
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591198845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t imeout.1591198845
Directory	/workspace/28.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/28.clkmgr_idle_intersig_mubi.1176162095
Short name	T331
Test name
Test status
Simulation time	15165365 ps
CPU time	0.73 seconds
Started	Mar 12 12:47:43 PM PDT 24
Finished	Mar 12 12:47:44 PM PDT 24
Peak memory	200792 kb
Host	smart-7d379300-b336-482b-b412-39dab3a2a17f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176162095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_idle_intersig_mubi.1176162095
Directory	/workspace/28.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.536020030
Short name	T386
Test name
Test status
Simulation time	78493029 ps
CPU time	0.99 seconds
Started	Mar 12 12:47:33 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200808 kb
Host	smart-ecb34e09-5c57-4393-a41b-8d97fdf7e0be
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536020030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.clkmgr_lc_clk_byp_req_intersig_mubi.536020030
Directory	/workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.4131905998
Short name	T690
Test name
Test status
Simulation time	66990064 ps
CPU time	0.92 seconds
Started	Mar 12 12:47:39 PM PDT 24
Finished	Mar 12 12:47:40 PM PDT 24
Peak memory	200808 kb
Host	smart-6d7af4ae-3ed7-4549-9632-a7beb5f4fd5c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131905998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.clkmgr_lc_ctrl_intersig_mubi.4131905998
Directory	/workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_peri.3921625754
Short name	T700
Test name
Test status
Simulation time	32760363 ps
CPU time	0.79 seconds
Started	Mar 12 12:47:31 PM PDT 24
Finished	Mar 12 12:47:33 PM PDT 24
Peak memory	200684 kb
Host	smart-f23955ec-4c91-49ee-b2cd-987d5ddc29c5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921625754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.3921625754
Directory	/workspace/28.clkmgr_peri/latest

Test location	/workspace/coverage/default/28.clkmgr_regwen.2508260502
Short name	T811
Test name
Test status
Simulation time	1495637146 ps
CPU time	5.6 seconds
Started	Mar 12 12:47:42 PM PDT 24
Finished	Mar 12 12:47:48 PM PDT 24
Peak memory	200992 kb
Host	smart-2c640cbd-405a-41d1-bc7a-c1f9de6c35d6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508260502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2508260502
Directory	/workspace/28.clkmgr_regwen/latest

Test location	/workspace/coverage/default/28.clkmgr_smoke.4215034364
Short name	T261
Test name
Test status
Simulation time	17931434 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:45 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200816 kb
Host	smart-9e7fae95-615e-4783-aa61-ca0ca28ed7a2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215034364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.4215034364
Directory	/workspace/28.clkmgr_smoke/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all.2770027037
Short name	T446
Test name
Test status
Simulation time	1224900411 ps
CPU time	5.1 seconds
Started	Mar 12 12:47:36 PM PDT 24
Finished	Mar 12 12:47:42 PM PDT 24
Peak memory	201068 kb
Host	smart-a83ffcc0-436f-424b-80bb-ef83e760e375
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770027037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.2770027037
Directory	/workspace/28.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.428520758
Short name	T611
Test name
Test status
Simulation time	22231368472 ps
CPU time	408.41 seconds
Started	Mar 12 12:47:40 PM PDT 24
Finished	Mar 12 12:54:30 PM PDT 24
Peak memory	217616 kb
Host	smart-da809c06-c857-4dd4-b847-e274902aa59b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=428520758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.428520758
Directory	/workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.clkmgr_trans.2204556465
Short name	T568
Test name
Test status
Simulation time	41618283 ps
CPU time	0.93 seconds
Started	Mar 12 12:47:38 PM PDT 24
Finished	Mar 12 12:47:40 PM PDT 24
Peak memory	200816 kb
Host	smart-89e02b07-6651-4849-b837-9e8f6255c91f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204556465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.2204556465
Directory	/workspace/28.clkmgr_trans/latest

Test location	/workspace/coverage/default/29.clkmgr_alert_test.3735217283
Short name	T421
Test name
Test status
Simulation time	49482571 ps
CPU time	0.84 seconds
Started	Mar 12 12:47:38 PM PDT 24
Finished	Mar 12 12:47:40 PM PDT 24
Peak memory	200892 kb
Host	smart-b2162d79-ebc9-4bc3-8f64-1f0de1824c0f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735217283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk mgr_alert_test.3735217283
Directory	/workspace/29.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.3083935463
Short name	T89
Test name
Test status
Simulation time	110454045 ps
CPU time	0.97 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:47:45 PM PDT 24
Peak memory	200596 kb
Host	smart-9d0c758b-a295-43a9-a400-5a4794a96bee
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083935463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.3083935463
Directory	/workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_status.2174561635
Short name	T576
Test name
Test status
Simulation time	33574641 ps
CPU time	0.75 seconds
Started	Mar 12 12:47:40 PM PDT 24
Finished	Mar 12 12:47:42 PM PDT 24
Peak memory	199756 kb
Host	smart-b3f5efdf-930c-44f6-bf9f-bb0f86a2d41b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174561635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2174561635
Directory	/workspace/29.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/29.clkmgr_div_intersig_mubi.705048769
Short name	T440
Test name
Test status
Simulation time	17321208 ps
CPU time	0.75 seconds
Started	Mar 12 12:47:37 PM PDT 24
Finished	Mar 12 12:47:38 PM PDT 24
Peak memory	200852 kb
Host	smart-95e092bc-a95e-4bac-b67e-8616b2dacfbe
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705048769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.clkmgr_div_intersig_mubi.705048769
Directory	/workspace/29.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_extclk.3018613736
Short name	T168
Test name
Test status
Simulation time	55321826 ps
CPU time	0.9 seconds
Started	Mar 12 12:47:42 PM PDT 24
Finished	Mar 12 12:47:43 PM PDT 24
Peak memory	200856 kb
Host	smart-b60bc375-c05a-49f8-8886-3beb73a00b93
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018613736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.3018613736
Directory	/workspace/29.clkmgr_extclk/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency.3069136118
Short name	T577
Test name
Test status
Simulation time	2057367636 ps
CPU time	9.13 seconds
Started	Mar 12 12:47:42 PM PDT 24
Finished	Mar 12 12:47:51 PM PDT 24
Peak memory	200996 kb
Host	smart-940b5548-3454-4d85-94d3-9ea5db1d027c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069136118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.3069136118
Directory	/workspace/29.clkmgr_frequency/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency_timeout.3804855826
Short name	T774
Test name
Test status
Simulation time	628416593 ps
CPU time	2.86 seconds
Started	Mar 12 12:47:41 PM PDT 24
Finished	Mar 12 12:47:44 PM PDT 24
Peak memory	200844 kb
Host	smart-b5007b89-df0e-41d8-934d-2fd819dc4823
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804855826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t imeout.3804855826
Directory	/workspace/29.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/29.clkmgr_idle_intersig_mubi.3595998978
Short name	T504
Test name
Test status
Simulation time	16463582 ps
CPU time	0.85 seconds
Started	Mar 12 12:47:43 PM PDT 24
Finished	Mar 12 12:47:44 PM PDT 24
Peak memory	200852 kb
Host	smart-ac8e11f1-90bc-43e5-9257-d61b5b050649
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595998978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.3595998978
Directory	/workspace/29.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.2626437161
Short name	T671
Test name
Test status
Simulation time	15690996 ps
CPU time	0.71 seconds
Started	Mar 12 12:47:40 PM PDT 24
Finished	Mar 12 12:47:41 PM PDT 24
Peak memory	200808 kb
Host	smart-981bbcdf-a74c-4ac4-ab18-dd2a91244b54
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626437161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_clk_byp_req_intersig_mubi.2626437161
Directory	/workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.3749100012
Short name	T49
Test name
Test status
Simulation time	74216225 ps
CPU time	0.99 seconds
Started	Mar 12 12:47:32 PM PDT 24
Finished	Mar 12 12:47:34 PM PDT 24
Peak memory	200792 kb
Host	smart-5c1896a0-ba23-4834-8ab0-87cf2a2b2b14
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749100012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_ctrl_intersig_mubi.3749100012
Directory	/workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_peri.1795819449
Short name	T223
Test name
Test status
Simulation time	50217440 ps
CPU time	0.82 seconds
Started	Mar 12 12:47:40 PM PDT 24
Finished	Mar 12 12:47:42 PM PDT 24
Peak memory	200708 kb
Host	smart-fa5082c5-e40d-4e63-b40a-7ff548152b00
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795819449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.1795819449
Directory	/workspace/29.clkmgr_peri/latest

Test location	/workspace/coverage/default/29.clkmgr_regwen.2863688571
Short name	T797
Test name
Test status
Simulation time	1171519028 ps
CPU time	5.1 seconds
Started	Mar 12 12:47:43 PM PDT 24
Finished	Mar 12 12:47:49 PM PDT 24
Peak memory	201056 kb
Host	smart-c40f97ae-95b8-4e21-9cd5-a86a57d75eab
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863688571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.2863688571
Directory	/workspace/29.clkmgr_regwen/latest

Test location	/workspace/coverage/default/29.clkmgr_smoke.1920548262
Short name	T302
Test name
Test status
Simulation time	14978400 ps
CPU time	0.78 seconds
Started	Mar 12 12:47:38 PM PDT 24
Finished	Mar 12 12:47:40 PM PDT 24
Peak memory	200764 kb
Host	smart-29b92e8d-441a-490a-be84-0179e3b49d66
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920548262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1920548262
Directory	/workspace/29.clkmgr_smoke/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all.3011825253
Short name	T786
Test name
Test status
Simulation time	3026497401 ps
CPU time	16.68 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:48:01 PM PDT 24
Peak memory	201128 kb
Host	smart-4b4e2a28-b33c-44e8-837f-758d40aed9c4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011825253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.3011825253
Directory	/workspace/29.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.2105403173
Short name	T137
Test name
Test status
Simulation time	34423887692 ps
CPU time	478.74 seconds
Started	Mar 12 12:47:35 PM PDT 24
Finished	Mar 12 12:55:34 PM PDT 24
Peak memory	209472 kb
Host	smart-96788cb5-e1b7-4c9f-b48b-5c33c900288f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2105403173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.2105403173
Directory	/workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.clkmgr_trans.4082050341
Short name	T713
Test name
Test status
Simulation time	44232912 ps
CPU time	0.79 seconds
Started	Mar 12 12:47:35 PM PDT 24
Finished	Mar 12 12:47:35 PM PDT 24
Peak memory	200760 kb
Host	smart-e064ae9f-b951-4953-9cff-88f9fdd8db43
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082050341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.4082050341
Directory	/workspace/29.clkmgr_trans/latest

Test location	/workspace/coverage/default/3.clkmgr_alert_test.2756439350
Short name	T196
Test name
Test status
Simulation time	42511318 ps
CPU time	0.8 seconds
Started	Mar 12 12:46:35 PM PDT 24
Finished	Mar 12 12:46:36 PM PDT 24
Peak memory	200884 kb
Host	smart-5e7abcb2-e035-4401-916d-cc6ee6b95244
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756439350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm gr_alert_test.2756439350
Directory	/workspace/3.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.628356531
Short name	T736
Test name
Test status
Simulation time	27826839 ps
CPU time	0.86 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:40 PM PDT 24
Peak memory	200816 kb
Host	smart-7866f92b-929b-48c8-94b1-48bdc4bc7dc0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628356531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.628356531
Directory	/workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_status.58558466
Short name	T475
Test name
Test status
Simulation time	33635536 ps
CPU time	0.72 seconds
Started	Mar 12 12:46:36 PM PDT 24
Finished	Mar 12 12:46:37 PM PDT 24
Peak memory	199800 kb
Host	smart-47ad304e-a13a-4d17-bde5-437e27a46725
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58558466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.58558466
Directory	/workspace/3.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/3.clkmgr_div_intersig_mubi.2205890614
Short name	T283
Test name
Test status
Simulation time	22664060 ps
CPU time	0.82 seconds
Started	Mar 12 12:46:41 PM PDT 24
Finished	Mar 12 12:46:43 PM PDT 24
Peak memory	200604 kb
Host	smart-5ecaf23f-a65a-40bf-8f8c-f85a95a6ce87
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205890614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.2205890614
Directory	/workspace/3.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_extclk.1396426345
Short name	T518
Test name
Test status
Simulation time	28512281 ps
CPU time	0.88 seconds
Started	Mar 12 12:46:32 PM PDT 24
Finished	Mar 12 12:46:33 PM PDT 24
Peak memory	200532 kb
Host	smart-3dccbf40-d561-48f2-9d83-a6f8598bdfaf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396426345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.1396426345
Directory	/workspace/3.clkmgr_extclk/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency.2631480970
Short name	T584
Test name
Test status
Simulation time	242324424 ps
CPU time	1.58 seconds
Started	Mar 12 12:46:33 PM PDT 24
Finished	Mar 12 12:46:35 PM PDT 24
Peak memory	200808 kb
Host	smart-c628608c-a525-4f4a-831d-57ea7645892c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631480970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.2631480970
Directory	/workspace/3.clkmgr_frequency/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency_timeout.232666175
Short name	T6
Test name
Test status
Simulation time	791197554 ps
CPU time	3.61 seconds
Started	Mar 12 12:46:32 PM PDT 24
Finished	Mar 12 12:46:36 PM PDT 24
Peak memory	200812 kb
Host	smart-a547f2e4-735f-48a9-ba99-bdac67718ab6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232666175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_tim eout.232666175
Directory	/workspace/3.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/3.clkmgr_idle_intersig_mubi.939563385
Short name	T693
Test name
Test status
Simulation time	203667725 ps
CPU time	1.4 seconds
Started	Mar 12 12:46:29 PM PDT 24
Finished	Mar 12 12:46:31 PM PDT 24
Peak memory	200736 kb
Host	smart-92ccd7e6-56a9-4359-b0a6-1636aa4c222a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939563385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .clkmgr_idle_intersig_mubi.939563385
Directory	/workspace/3.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.4101443666
Short name	T681
Test name
Test status
Simulation time	80197492 ps
CPU time	0.89 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:40 PM PDT 24
Peak memory	200812 kb
Host	smart-8b5571ba-11f2-4f30-ad38-b7796b848552
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101443666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.clkmgr_lc_clk_byp_req_intersig_mubi.4101443666
Directory	/workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.3753756415
Short name	T452
Test name
Test status
Simulation time	13615061 ps
CPU time	0.72 seconds
Started	Mar 12 12:46:33 PM PDT 24
Finished	Mar 12 12:46:34 PM PDT 24
Peak memory	200660 kb
Host	smart-ac07174a-f5bf-442f-9fba-a25c478c9a34
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753756415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.clkmgr_lc_ctrl_intersig_mubi.3753756415
Directory	/workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_peri.1339321405
Short name	T264
Test name
Test status
Simulation time	33663761 ps
CPU time	0.78 seconds
Started	Mar 12 12:46:33 PM PDT 24
Finished	Mar 12 12:46:34 PM PDT 24
Peak memory	200660 kb
Host	smart-973e37e6-0ba0-4d6e-9667-7de34655b282
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339321405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.1339321405
Directory	/workspace/3.clkmgr_peri/latest

Test location	/workspace/coverage/default/3.clkmgr_regwen.2046903448
Short name	T661
Test name
Test status
Simulation time	518255366 ps
CPU time	3.25 seconds
Started	Mar 12 12:46:34 PM PDT 24
Finished	Mar 12 12:46:38 PM PDT 24
Peak memory	200900 kb
Host	smart-06d2c10a-7c1b-47c2-9ef8-eaea1274d1b4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046903448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.2046903448
Directory	/workspace/3.clkmgr_regwen/latest

Test location	/workspace/coverage/default/3.clkmgr_sec_cm.2581009356
Short name	T38
Test name
Test status
Simulation time	244224657 ps
CPU time	2.23 seconds
Started	Mar 12 12:46:29 PM PDT 24
Finished	Mar 12 12:46:32 PM PDT 24
Peak memory	215872 kb
Host	smart-80f42bc0-1b4f-4f7d-b584-9594f9f738c8
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581009356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg r_sec_cm.2581009356
Directory	/workspace/3.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/3.clkmgr_smoke.2663362050
Short name	T289
Test name
Test status
Simulation time	81568325 ps
CPU time	0.98 seconds
Started	Mar 12 12:46:29 PM PDT 24
Finished	Mar 12 12:46:31 PM PDT 24
Peak memory	200820 kb
Host	smart-f884d604-5d9d-4164-ba38-cf25c2994773
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663362050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.2663362050
Directory	/workspace/3.clkmgr_smoke/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all.2860333734
Short name	T778
Test name
Test status
Simulation time	2497450453 ps
CPU time	8.97 seconds
Started	Mar 12 12:46:32 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	201120 kb
Host	smart-6fa36f9e-b088-47de-a4c6-11a18e5530a0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860333734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.2860333734
Directory	/workspace/3.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.1165952180
Short name	T535
Test name
Test status
Simulation time	145572032026 ps
CPU time	1020.76 seconds
Started	Mar 12 12:46:30 PM PDT 24
Finished	Mar 12 01:03:31 PM PDT 24
Peak memory	217684 kb
Host	smart-97f6e20e-b6b3-4bf8-848d-84ec38e0c3c2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1165952180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.1165952180
Directory	/workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.clkmgr_trans.1819034632
Short name	T784
Test name
Test status
Simulation time	27741936 ps
CPU time	0.91 seconds
Started	Mar 12 12:46:32 PM PDT 24
Finished	Mar 12 12:46:33 PM PDT 24
Peak memory	200748 kb
Host	smart-3b39f309-8855-4161-b342-51d03ee10612
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819034632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.1819034632
Directory	/workspace/3.clkmgr_trans/latest

Test location	/workspace/coverage/default/30.clkmgr_alert_test.3340397818
Short name	T180
Test name
Test status
Simulation time	25107211 ps
CPU time	0.83 seconds
Started	Mar 12 12:47:40 PM PDT 24
Finished	Mar 12 12:47:42 PM PDT 24
Peak memory	200872 kb
Host	smart-1a1713fd-e150-45bf-a1c7-9379dd70e571
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340397818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk mgr_alert_test.3340397818
Directory	/workspace/30.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.165188258
Short name	T307
Test name
Test status
Simulation time	16753263 ps
CPU time	0.75 seconds
Started	Mar 12 12:47:35 PM PDT 24
Finished	Mar 12 12:47:37 PM PDT 24
Peak memory	200572 kb
Host	smart-17f24dfa-f987-47a7-b32a-efbaaa9530c9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165188258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.165188258
Directory	/workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_status.276370777
Short name	T742
Test name
Test status
Simulation time	18261027 ps
CPU time	0.74 seconds
Started	Mar 12 12:47:45 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200736 kb
Host	smart-949fe25d-5ead-4011-b489-43b58171a707
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276370777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.276370777
Directory	/workspace/30.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/30.clkmgr_div_intersig_mubi.378400960
Short name	T165
Test name
Test status
Simulation time	16251379 ps
CPU time	0.76 seconds
Started	Mar 12 12:47:45 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200800 kb
Host	smart-f8f40192-0c26-4bd1-8b7f-b96c6556bd6d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378400960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.clkmgr_div_intersig_mubi.378400960
Directory	/workspace/30.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_extclk.3640783569
Short name	T430
Test name
Test status
Simulation time	19787046 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:36 PM PDT 24
Finished	Mar 12 12:47:37 PM PDT 24
Peak memory	200660 kb
Host	smart-63c9e39d-b631-4445-b871-6e36f0cac19b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640783569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.3640783569
Directory	/workspace/30.clkmgr_extclk/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency.2062306844
Short name	T27
Test name
Test status
Simulation time	202246916 ps
CPU time	2.06 seconds
Started	Mar 12 12:47:38 PM PDT 24
Finished	Mar 12 12:47:41 PM PDT 24
Peak memory	200732 kb
Host	smart-ef8735f8-3c5b-4279-9d1b-99c33fc8f729
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062306844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.2062306844
Directory	/workspace/30.clkmgr_frequency/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency_timeout.4036142776
Short name	T197
Test name
Test status
Simulation time	2038677609 ps
CPU time	6.77 seconds
Started	Mar 12 12:47:40 PM PDT 24
Finished	Mar 12 12:47:48 PM PDT 24
Peak memory	200876 kb
Host	smart-92d0c594-8e53-470b-9347-eb9003b77bcb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036142776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t imeout.4036142776
Directory	/workspace/30.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/30.clkmgr_idle_intersig_mubi.2744014674
Short name	T473
Test name
Test status
Simulation time	43862771 ps
CPU time	1.08 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200800 kb
Host	smart-8ed9b7ab-ad9b-45d6-aaf0-2594106091f7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744014674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.2744014674
Directory	/workspace/30.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.349664052
Short name	T498
Test name
Test status
Simulation time	82226891 ps
CPU time	0.92 seconds
Started	Mar 12 12:47:40 PM PDT 24
Finished	Mar 12 12:47:42 PM PDT 24
Peak memory	200812 kb
Host	smart-02fa2151-7507-466d-bffa-e9dd9e856694
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349664052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.clkmgr_lc_clk_byp_req_intersig_mubi.349664052
Directory	/workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.3554816123
Short name	T257
Test name
Test status
Simulation time	21752999 ps
CPU time	0.8 seconds
Started	Mar 12 12:47:43 PM PDT 24
Finished	Mar 12 12:47:44 PM PDT 24
Peak memory	200656 kb
Host	smart-2f5cd294-33fe-4f0c-aa98-b7ae7449c795
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554816123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 30.clkmgr_lc_ctrl_intersig_mubi.3554816123
Directory	/workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_peri.2869844881
Short name	T630
Test name
Test status
Simulation time	23603383 ps
CPU time	0.73 seconds
Started	Mar 12 12:47:35 PM PDT 24
Finished	Mar 12 12:47:37 PM PDT 24
Peak memory	200668 kb
Host	smart-3f7d5b22-d1ed-45df-bb8a-a4e486291012
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869844881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.2869844881
Directory	/workspace/30.clkmgr_peri/latest

Test location	/workspace/coverage/default/30.clkmgr_regwen.3706983812
Short name	T310
Test name
Test status
Simulation time	508355149 ps
CPU time	2.05 seconds
Started	Mar 12 12:47:42 PM PDT 24
Finished	Mar 12 12:47:44 PM PDT 24
Peak memory	200732 kb
Host	smart-3dac3bda-2477-4567-bf4f-47d5ced506e9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706983812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.3706983812
Directory	/workspace/30.clkmgr_regwen/latest

Test location	/workspace/coverage/default/30.clkmgr_smoke.1454978330
Short name	T604
Test name
Test status
Simulation time	18578786 ps
CPU time	0.79 seconds
Started	Mar 12 12:47:39 PM PDT 24
Finished	Mar 12 12:47:41 PM PDT 24
Peak memory	200812 kb
Host	smart-0cd68b43-5048-44f6-ab71-a1774ab25fcc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454978330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.1454978330
Directory	/workspace/30.clkmgr_smoke/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all.1035709241
Short name	T757
Test name
Test status
Simulation time	2395280601 ps
CPU time	18.81 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:48:03 PM PDT 24
Peak memory	201076 kb
Host	smart-86aaf878-4bc5-461a-92ca-95624913691a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035709241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.1035709241
Directory	/workspace/30.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.725854847
Short name	T16
Test name
Test status
Simulation time	29948659203 ps
CPU time	318.52 seconds
Started	Mar 12 12:47:40 PM PDT 24
Finished	Mar 12 12:52:59 PM PDT 24
Peak memory	217128 kb
Host	smart-d71a9356-b9ff-42a0-9e8d-fa9452f9da23
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=725854847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.725854847
Directory	/workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.clkmgr_trans.78020519
Short name	T776
Test name
Test status
Simulation time	17370112 ps
CPU time	0.79 seconds
Started	Mar 12 12:47:45 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200780 kb
Host	smart-c0bdb1c8-7950-46dc-a24c-344ea4d66789
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78020519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.78020519
Directory	/workspace/30.clkmgr_trans/latest

Test location	/workspace/coverage/default/31.clkmgr_alert_test.491837027
Short name	T822
Test name
Test status
Simulation time	55602495 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:52 PM PDT 24
Finished	Mar 12 12:47:53 PM PDT 24
Peak memory	200892 kb
Host	smart-d8795ebf-a5cc-44c0-b81d-cd557db504e2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491837027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkm gr_alert_test.491837027
Directory	/workspace/31.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.4098009688
Short name	T536
Test name
Test status
Simulation time	45039610 ps
CPU time	0.93 seconds
Started	Mar 12 12:47:47 PM PDT 24
Finished	Mar 12 12:47:48 PM PDT 24
Peak memory	200660 kb
Host	smart-9a5d1805-41bc-43fa-95f8-63e0d4798c44
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098009688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.4098009688
Directory	/workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_status.3302299770
Short name	T752
Test name
Test status
Simulation time	12767568 ps
CPU time	0.68 seconds
Started	Mar 12 12:47:47 PM PDT 24
Finished	Mar 12 12:47:48 PM PDT 24
Peak memory	199664 kb
Host	smart-ad084db2-ce57-4253-a5a7-394b80be7d22
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302299770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.3302299770
Directory	/workspace/31.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/31.clkmgr_div_intersig_mubi.1932955128
Short name	T564
Test name
Test status
Simulation time	136090717 ps
CPU time	1.15 seconds
Started	Mar 12 12:47:46 PM PDT 24
Finished	Mar 12 12:47:47 PM PDT 24
Peak memory	200828 kb
Host	smart-9d0bda5c-4fcb-4df9-81bd-c69748ff0b08
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932955128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.1932955128
Directory	/workspace/31.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_extclk.3615857945
Short name	T407
Test name
Test status
Simulation time	25546160 ps
CPU time	0.72 seconds
Started	Mar 12 12:47:40 PM PDT 24
Finished	Mar 12 12:47:41 PM PDT 24
Peak memory	200660 kb
Host	smart-e91691a6-37b9-456a-9bab-dbf617e01279
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615857945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.3615857945
Directory	/workspace/31.clkmgr_extclk/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency.551928780
Short name	T830
Test name
Test status
Simulation time	921448183 ps
CPU time	7.22 seconds
Started	Mar 12 12:47:38 PM PDT 24
Finished	Mar 12 12:47:47 PM PDT 24
Peak memory	200808 kb
Host	smart-920360ee-5478-4b39-82b5-9bf0f345bb2c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551928780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.551928780
Directory	/workspace/31.clkmgr_frequency/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency_timeout.1690551115
Short name	T443
Test name
Test status
Simulation time	2321811003 ps
CPU time	9.62 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:47:54 PM PDT 24
Peak memory	201112 kb
Host	smart-b199ad37-5b7b-4569-afcd-3b21d9ae4d7e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690551115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t imeout.1690551115
Directory	/workspace/31.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1689827834
Short name	T523
Test name
Test status
Simulation time	31144779 ps
CPU time	0.88 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:47:45 PM PDT 24
Peak memory	200796 kb
Host	smart-995ac390-50b1-4cd7-aa17-32968d520bf6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689827834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.1689827834
Directory	/workspace/31.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.964999368
Short name	T354
Test name
Test status
Simulation time	22840434 ps
CPU time	0.86 seconds
Started	Mar 12 12:47:36 PM PDT 24
Finished	Mar 12 12:47:38 PM PDT 24
Peak memory	200724 kb
Host	smart-acd7005f-3c8a-4539-8cb4-e3bedc86d9f9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964999368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.clkmgr_lc_clk_byp_req_intersig_mubi.964999368
Directory	/workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.1777846753
Short name	T476
Test name
Test status
Simulation time	24620641 ps
CPU time	0.74 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:47:45 PM PDT 24
Peak memory	200792 kb
Host	smart-a694e664-5a7d-4c73-bc82-e5c577908506
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777846753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.clkmgr_lc_ctrl_intersig_mubi.1777846753
Directory	/workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_peri.1085710285
Short name	T425
Test name
Test status
Simulation time	23366110 ps
CPU time	0.72 seconds
Started	Mar 12 12:47:46 PM PDT 24
Finished	Mar 12 12:47:47 PM PDT 24
Peak memory	200580 kb
Host	smart-6534a0b5-78cc-4ad8-b855-41fa0e8e7080
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085710285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.1085710285
Directory	/workspace/31.clkmgr_peri/latest

Test location	/workspace/coverage/default/31.clkmgr_regwen.1997466122
Short name	T673
Test name
Test status
Simulation time	584030743 ps
CPU time	3.67 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:47:48 PM PDT 24
Peak memory	200928 kb
Host	smart-bd9a1131-c2df-4b27-8739-e76243ea7c7b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997466122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.1997466122
Directory	/workspace/31.clkmgr_regwen/latest

Test location	/workspace/coverage/default/31.clkmgr_smoke.4034768803
Short name	T670
Test name
Test status
Simulation time	18188263 ps
CPU time	0.78 seconds
Started	Mar 12 12:47:40 PM PDT 24
Finished	Mar 12 12:47:41 PM PDT 24
Peak memory	200812 kb
Host	smart-ca36a5d2-ada9-4c8d-9c35-5644b158a97a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034768803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.4034768803
Directory	/workspace/31.clkmgr_smoke/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all.441297328
Short name	T685
Test name
Test status
Simulation time	363524575 ps
CPU time	3.34 seconds
Started	Mar 12 12:47:45 PM PDT 24
Finished	Mar 12 12:47:48 PM PDT 24
Peak memory	200452 kb
Host	smart-188c4160-40ed-49c9-8101-525e8d8f4b5a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441297328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.441297328
Directory	/workspace/31.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.4020417879
Short name	T470
Test name
Test status
Simulation time	104355463472 ps
CPU time	663.09 seconds
Started	Mar 12 12:47:43 PM PDT 24
Finished	Mar 12 12:58:47 PM PDT 24
Peak memory	217536 kb
Host	smart-37e57399-ea8b-42af-874d-5fa01010b8f3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4020417879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.4020417879
Directory	/workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.clkmgr_trans.1143351259
Short name	T694
Test name
Test status
Simulation time	22076148 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:36 PM PDT 24
Finished	Mar 12 12:47:37 PM PDT 24
Peak memory	200716 kb
Host	smart-a4b8fbff-07a9-42fb-8e0d-a4b9c649b038
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143351259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.1143351259
Directory	/workspace/31.clkmgr_trans/latest

Test location	/workspace/coverage/default/32.clkmgr_alert_test.3360497303
Short name	T201
Test name
Test status
Simulation time	23626362 ps
CPU time	0.84 seconds
Started	Mar 12 12:47:45 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200872 kb
Host	smart-0ad50d71-7fe4-4dfe-82a9-927ebe1aa34a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360497303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk mgr_alert_test.3360497303
Directory	/workspace/32.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.151327733
Short name	T269
Test name
Test status
Simulation time	16886537 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:50 PM PDT 24
Finished	Mar 12 12:47:51 PM PDT 24
Peak memory	200848 kb
Host	smart-33968fe1-f14f-4e59-be4c-eec51f7e1b72
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151327733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.151327733
Directory	/workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_status.446270189
Short name	T253
Test name
Test status
Simulation time	34630092 ps
CPU time	0.73 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:47:45 PM PDT 24
Peak memory	199660 kb
Host	smart-0bbe0359-b1fa-4e0f-8eb6-245cb36fcd8b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446270189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.446270189
Directory	/workspace/32.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/32.clkmgr_div_intersig_mubi.3425697813
Short name	T237
Test name
Test status
Simulation time	15271003 ps
CPU time	0.74 seconds
Started	Mar 12 12:47:46 PM PDT 24
Finished	Mar 12 12:47:47 PM PDT 24
Peak memory	200620 kb
Host	smart-3b53b5e4-f835-4089-b4c4-2d48c7761ee5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425697813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.3425697813
Directory	/workspace/32.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_extclk.339561529
Short name	T203
Test name
Test status
Simulation time	43760095 ps
CPU time	0.92 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:47:45 PM PDT 24
Peak memory	200712 kb
Host	smart-ffe0247c-dcd0-4309-aaf9-3ea83cd605ca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339561529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.339561529
Directory	/workspace/32.clkmgr_extclk/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency.1958088161
Short name	T265
Test name
Test status
Simulation time	1998527763 ps
CPU time	14.53 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:47:59 PM PDT 24
Peak memory	200924 kb
Host	smart-8b45520f-f17e-481f-b1a6-2da8c86d84be
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958088161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.1958088161
Directory	/workspace/32.clkmgr_frequency/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency_timeout.3409111910
Short name	T834
Test name
Test status
Simulation time	2298908781 ps
CPU time	17.38 seconds
Started	Mar 12 12:47:47 PM PDT 24
Finished	Mar 12 12:48:05 PM PDT 24
Peak memory	201120 kb
Host	smart-f1703b9a-c407-48e6-828c-12f9499ae143
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409111910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t imeout.3409111910
Directory	/workspace/32.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/32.clkmgr_idle_intersig_mubi.29530252
Short name	T396
Test name
Test status
Simulation time	33332469 ps
CPU time	0.95 seconds
Started	Mar 12 12:47:46 PM PDT 24
Finished	Mar 12 12:47:47 PM PDT 24
Peak memory	200864 kb
Host	smart-f91d3f71-b820-45ce-b7f6-0f3f25224c7a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29530252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32 .clkmgr_idle_intersig_mubi.29530252
Directory	/workspace/32.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.3096116898
Short name	T672
Test name
Test status
Simulation time	18168983 ps
CPU time	0.79 seconds
Started	Mar 12 12:47:46 PM PDT 24
Finished	Mar 12 12:47:47 PM PDT 24
Peak memory	200856 kb
Host	smart-e9f58d77-1f9d-4e81-9fd0-a0e917690e72
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096116898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_clk_byp_req_intersig_mubi.3096116898
Directory	/workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.1367808615
Short name	T462
Test name
Test status
Simulation time	18825436 ps
CPU time	0.82 seconds
Started	Mar 12 12:47:45 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200728 kb
Host	smart-adf2e478-c8f2-444d-aa79-e5412d41d14b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367808615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_ctrl_intersig_mubi.1367808615
Directory	/workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_peri.3413141193
Short name	T208
Test name
Test status
Simulation time	30628413 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:43 PM PDT 24
Finished	Mar 12 12:47:44 PM PDT 24
Peak memory	200688 kb
Host	smart-2bbec6d3-5a11-4280-b91b-8c295fbccc5f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413141193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.3413141193
Directory	/workspace/32.clkmgr_peri/latest

Test location	/workspace/coverage/default/32.clkmgr_regwen.83015693
Short name	T132
Test name
Test status
Simulation time	1157035920 ps
CPU time	6.87 seconds
Started	Mar 12 12:47:48 PM PDT 24
Finished	Mar 12 12:47:55 PM PDT 24
Peak memory	201012 kb
Host	smart-641ddaf6-fc0b-465f-891e-d9303fabf936
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83015693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.83015693
Directory	/workspace/32.clkmgr_regwen/latest

Test location	/workspace/coverage/default/32.clkmgr_smoke.3449062607
Short name	T402
Test name
Test status
Simulation time	329020418 ps
CPU time	1.81 seconds
Started	Mar 12 12:47:43 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200844 kb
Host	smart-c2b79dbf-8d6f-4389-b3df-060a50b8ba16
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449062607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3449062607
Directory	/workspace/32.clkmgr_smoke/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all.4083660587
Short name	T296
Test name
Test status
Simulation time	8832514891 ps
CPU time	35.3 seconds
Started	Mar 12 12:47:50 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	201232 kb
Host	smart-18b55ae7-2b35-43a9-a50a-1f1bfe3e4fb4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083660587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.4083660587
Directory	/workspace/32.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.3718008954
Short name	T659
Test name
Test status
Simulation time	31263314538 ps
CPU time	322.03 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:53:06 PM PDT 24
Peak memory	209544 kb
Host	smart-c86f8e09-ae8c-4dba-846c-149cbca4ea8d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3718008954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.3718008954
Directory	/workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.clkmgr_trans.3491886879
Short name	T294
Test name
Test status
Simulation time	15540297 ps
CPU time	0.72 seconds
Started	Mar 12 12:47:45 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200792 kb
Host	smart-12f39981-a606-4d86-b078-88126f8a9c49
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491886879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.3491886879
Directory	/workspace/32.clkmgr_trans/latest

Test location	/workspace/coverage/default/33.clkmgr_alert_test.2419171091
Short name	T489
Test name
Test status
Simulation time	22728433 ps
CPU time	0.74 seconds
Started	Mar 12 12:47:46 PM PDT 24
Finished	Mar 12 12:47:47 PM PDT 24
Peak memory	200880 kb
Host	smart-f63e591c-00f1-4333-8adb-8a04864cd4cb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419171091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk mgr_alert_test.2419171091
Directory	/workspace/33.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.4123587525
Short name	T761
Test name
Test status
Simulation time	83705036 ps
CPU time	1.02 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200752 kb
Host	smart-fddde758-19fd-4bda-9d1a-2f16d33cfd1a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123587525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.4123587525
Directory	/workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_status.3327042624
Short name	T759
Test name
Test status
Simulation time	35879895 ps
CPU time	0.73 seconds
Started	Mar 12 12:47:45 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200788 kb
Host	smart-ea49e135-3e36-4833-aef1-f0cae6e6722f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327042624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.3327042624
Directory	/workspace/33.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/33.clkmgr_div_intersig_mubi.3181443716
Short name	T851
Test name
Test status
Simulation time	92479519 ps
CPU time	1.1 seconds
Started	Mar 12 12:47:45 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200808 kb
Host	smart-02927c24-3d6a-403a-9a60-dd424f4ff04f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181443716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.3181443716
Directory	/workspace/33.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_extclk.1008607937
Short name	T606
Test name
Test status
Simulation time	57417007 ps
CPU time	0.87 seconds
Started	Mar 12 12:47:46 PM PDT 24
Finished	Mar 12 12:47:47 PM PDT 24
Peak memory	200740 kb
Host	smart-c8d36856-9b66-4bcd-ae87-d4e167517907
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008607937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.1008607937
Directory	/workspace/33.clkmgr_extclk/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency.4098599563
Short name	T353
Test name
Test status
Simulation time	214472188 ps
CPU time	1.6 seconds
Started	Mar 12 12:47:43 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200768 kb
Host	smart-17774ede-5be8-4db2-a489-d575c30d01c7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098599563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.4098599563
Directory	/workspace/33.clkmgr_frequency/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency_timeout.2345494616
Short name	T575
Test name
Test status
Simulation time	1222135636 ps
CPU time	7.13 seconds
Started	Mar 12 12:47:49 PM PDT 24
Finished	Mar 12 12:47:56 PM PDT 24
Peak memory	200884 kb
Host	smart-9d35ab28-fb35-42a2-9ea3-2af457b06594
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345494616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t imeout.2345494616
Directory	/workspace/33.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/33.clkmgr_idle_intersig_mubi.4039812618
Short name	T806
Test name
Test status
Simulation time	27951878 ps
CPU time	0.95 seconds
Started	Mar 12 12:47:43 PM PDT 24
Finished	Mar 12 12:47:44 PM PDT 24
Peak memory	200820 kb
Host	smart-e0ff7ed7-89f5-4b51-bdbd-00c6681df187
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039812618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.4039812618
Directory	/workspace/33.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.3361955870
Short name	T573
Test name
Test status
Simulation time	28390170 ps
CPU time	0.8 seconds
Started	Mar 12 12:47:46 PM PDT 24
Finished	Mar 12 12:47:47 PM PDT 24
Peak memory	200756 kb
Host	smart-dc5f9214-c62a-47b4-b147-3f885a2dea88
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361955870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_clk_byp_req_intersig_mubi.3361955870
Directory	/workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.3455980486
Short name	T323
Test name
Test status
Simulation time	81896120 ps
CPU time	1 seconds
Started	Mar 12 12:47:46 PM PDT 24
Finished	Mar 12 12:47:47 PM PDT 24
Peak memory	200728 kb
Host	smart-7a3a1834-9dff-464a-b31f-de18656549c3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455980486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_ctrl_intersig_mubi.3455980486
Directory	/workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_peri.2140329428
Short name	T687
Test name
Test status
Simulation time	19385636 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:47 PM PDT 24
Finished	Mar 12 12:47:48 PM PDT 24
Peak memory	200564 kb
Host	smart-b25c469f-ced0-427a-a18b-75bde7790e1c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140329428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.2140329428
Directory	/workspace/33.clkmgr_peri/latest

Test location	/workspace/coverage/default/33.clkmgr_regwen.3280013109
Short name	T605
Test name
Test status
Simulation time	174956920 ps
CPU time	1.63 seconds
Started	Mar 12 12:47:46 PM PDT 24
Finished	Mar 12 12:47:48 PM PDT 24
Peak memory	200748 kb
Host	smart-1d40ec7b-e6ea-401a-8061-d033433db121
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280013109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.3280013109
Directory	/workspace/33.clkmgr_regwen/latest

Test location	/workspace/coverage/default/33.clkmgr_smoke.3559193744
Short name	T351
Test name
Test status
Simulation time	65750396 ps
CPU time	0.95 seconds
Started	Mar 12 12:47:46 PM PDT 24
Finished	Mar 12 12:47:48 PM PDT 24
Peak memory	200784 kb
Host	smart-246d89d6-8e6f-476e-b190-e20233e3e188
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559193744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.3559193744
Directory	/workspace/33.clkmgr_smoke/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all.1409440641
Short name	T212
Test name
Test status
Simulation time	4462492394 ps
CPU time	33.39 seconds
Started	Mar 12 12:47:41 PM PDT 24
Finished	Mar 12 12:48:15 PM PDT 24
Peak memory	201168 kb
Host	smart-6d1ab238-d4ab-4010-a6e1-e7f91f0c7912
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409440641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.1409440641
Directory	/workspace/33.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.1342172168
Short name	T68
Test name
Test status
Simulation time	55996798208 ps
CPU time	589.57 seconds
Started	Mar 12 12:47:45 PM PDT 24
Finished	Mar 12 12:57:34 PM PDT 24
Peak memory	217316 kb
Host	smart-ebce1619-4e03-46fe-8306-b8edc7db6f53
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1342172168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.1342172168
Directory	/workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.clkmgr_trans.2247035386
Short name	T799
Test name
Test status
Simulation time	132085305 ps
CPU time	1.3 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:47:46 PM PDT 24
Peak memory	200816 kb
Host	smart-54789e8b-4624-4c5f-a2be-133858be891b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247035386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.2247035386
Directory	/workspace/33.clkmgr_trans/latest

Test location	/workspace/coverage/default/34.clkmgr_alert_test.2694251685
Short name	T714
Test name
Test status
Simulation time	31240880 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:59 PM PDT 24
Finished	Mar 12 12:48:00 PM PDT 24
Peak memory	200876 kb
Host	smart-91c883ac-2f7d-42fd-86af-a89396adf37d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694251685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk mgr_alert_test.2694251685
Directory	/workspace/34.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3347545402
Short name	T465
Test name
Test status
Simulation time	54368369 ps
CPU time	0.91 seconds
Started	Mar 12 12:47:54 PM PDT 24
Finished	Mar 12 12:47:55 PM PDT 24
Peak memory	200712 kb
Host	smart-c7740699-32ff-45fd-aa8f-0319b4646ac0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347545402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.3347545402
Directory	/workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_status.2390373433
Short name	T293
Test name
Test status
Simulation time	29345900 ps
CPU time	0.74 seconds
Started	Mar 12 12:48:00 PM PDT 24
Finished	Mar 12 12:48:01 PM PDT 24
Peak memory	199796 kb
Host	smart-72fba654-29e6-484b-b02a-d032c24b5dc3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390373433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.2390373433
Directory	/workspace/34.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/34.clkmgr_div_intersig_mubi.1181031247
Short name	T207
Test name
Test status
Simulation time	81636280 ps
CPU time	1.06 seconds
Started	Mar 12 12:47:59 PM PDT 24
Finished	Mar 12 12:48:00 PM PDT 24
Peak memory	200780 kb
Host	smart-a10c4a90-a982-44cd-ad6d-c73a07930072
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181031247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.1181031247
Directory	/workspace/34.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_extclk.624196025
Short name	T254
Test name
Test status
Simulation time	29435161 ps
CPU time	0.83 seconds
Started	Mar 12 12:47:44 PM PDT 24
Finished	Mar 12 12:47:45 PM PDT 24
Peak memory	200748 kb
Host	smart-3ea3b4c3-c8a8-4634-8785-ea2a87a80b90
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624196025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.624196025
Directory	/workspace/34.clkmgr_extclk/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency.2689496829
Short name	T771
Test name
Test status
Simulation time	869550682 ps
CPU time	4.01 seconds
Started	Mar 12 12:47:50 PM PDT 24
Finished	Mar 12 12:47:54 PM PDT 24
Peak memory	200852 kb
Host	smart-6b9697a5-9b67-4f71-a371-9de6f58b280d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689496829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.2689496829
Directory	/workspace/34.clkmgr_frequency/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency_timeout.427660335
Short name	T395
Test name
Test status
Simulation time	1465862313 ps
CPU time	8.63 seconds
Started	Mar 12 12:47:45 PM PDT 24
Finished	Mar 12 12:47:54 PM PDT 24
Peak memory	200648 kb
Host	smart-10802078-eb8a-4dc6-8b5d-de7226c853dd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427660335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_ti meout.427660335
Directory	/workspace/34.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/34.clkmgr_idle_intersig_mubi.1076921520
Short name	T634
Test name
Test status
Simulation time	26736304 ps
CPU time	0.89 seconds
Started	Mar 12 12:47:53 PM PDT 24
Finished	Mar 12 12:47:54 PM PDT 24
Peak memory	200772 kb
Host	smart-aaeff7d5-7e4e-4de6-81eb-047c5f9a0386
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076921520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.1076921520
Directory	/workspace/34.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.4276220559
Short name	T303
Test name
Test status
Simulation time	26044901 ps
CPU time	0.86 seconds
Started	Mar 12 12:48:10 PM PDT 24
Finished	Mar 12 12:48:12 PM PDT 24
Peak memory	200784 kb
Host	smart-8d175f53-8c49-4cfc-88be-bfdfc06c69cc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276220559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 34.clkmgr_lc_clk_byp_req_intersig_mubi.4276220559
Directory	/workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.82556422
Short name	T507
Test name
Test status
Simulation time	23786526 ps
CPU time	0.87 seconds
Started	Mar 12 12:47:52 PM PDT 24
Finished	Mar 12 12:47:54 PM PDT 24
Peak memory	200756 kb
Host	smart-46309ecc-3309-42ef-8d48-fc7dcc1d009f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82556422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_ctrl_intersig_mubi.82556422
Directory	/workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_peri.3501320468
Short name	T173
Test name
Test status
Simulation time	52677895 ps
CPU time	0.83 seconds
Started	Mar 12 12:47:47 PM PDT 24
Finished	Mar 12 12:47:48 PM PDT 24
Peak memory	200660 kb
Host	smart-f8ef03b7-a68e-4b89-964b-d78d9ead3974
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501320468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.3501320468
Directory	/workspace/34.clkmgr_peri/latest

Test location	/workspace/coverage/default/34.clkmgr_regwen.2546634892
Short name	T471
Test name
Test status
Simulation time	872050938 ps
CPU time	3.96 seconds
Started	Mar 12 12:47:58 PM PDT 24
Finished	Mar 12 12:48:02 PM PDT 24
Peak memory	201064 kb
Host	smart-4063790c-2d0c-4042-8856-d2e49997904b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546634892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2546634892
Directory	/workspace/34.clkmgr_regwen/latest

Test location	/workspace/coverage/default/34.clkmgr_smoke.84337605
Short name	T42
Test name
Test status
Simulation time	86836446 ps
CPU time	1 seconds
Started	Mar 12 12:47:43 PM PDT 24
Finished	Mar 12 12:47:45 PM PDT 24
Peak memory	200760 kb
Host	smart-6b6b401c-a803-49d2-8669-12dd18047641
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84337605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.84337605
Directory	/workspace/34.clkmgr_smoke/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all.2105701124
Short name	T347
Test name
Test status
Simulation time	4265784787 ps
CPU time	30.91 seconds
Started	Mar 12 12:47:54 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	201124 kb
Host	smart-bd34c08b-34b4-486a-9580-d92bb919f0a1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105701124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.2105701124
Directory	/workspace/34.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.3103373568
Short name	T727
Test name
Test status
Simulation time	73969385564 ps
CPU time	638.58 seconds
Started	Mar 12 12:47:55 PM PDT 24
Finished	Mar 12 12:58:34 PM PDT 24
Peak memory	217660 kb
Host	smart-889673a8-265e-4c10-925b-f052bb6103bf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3103373568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.3103373568
Directory	/workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.clkmgr_trans.1340922399
Short name	T379
Test name
Test status
Simulation time	80025761 ps
CPU time	1.07 seconds
Started	Mar 12 12:47:58 PM PDT 24
Finished	Mar 12 12:47:59 PM PDT 24
Peak memory	200768 kb
Host	smart-e94cfe70-828c-4e22-8ea6-eed52e6bb05f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340922399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.1340922399
Directory	/workspace/34.clkmgr_trans/latest

Test location	/workspace/coverage/default/35.clkmgr_alert_test.2852559709
Short name	T318
Test name
Test status
Simulation time	56314304 ps
CPU time	0.97 seconds
Started	Mar 12 12:47:57 PM PDT 24
Finished	Mar 12 12:47:58 PM PDT 24
Peak memory	200812 kb
Host	smart-b397c2dc-ce0d-4ae7-b1d0-ce1bb437a6e8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852559709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk mgr_alert_test.2852559709
Directory	/workspace/35.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.2361295545
Short name	T560
Test name
Test status
Simulation time	16655794 ps
CPU time	0.77 seconds
Started	Mar 12 12:47:56 PM PDT 24
Finished	Mar 12 12:47:57 PM PDT 24
Peak memory	200652 kb
Host	smart-f70a9626-6da0-4136-a6e7-0931573f96b3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361295545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.2361295545
Directory	/workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_status.80484398
Short name	T649
Test name
Test status
Simulation time	19094772 ps
CPU time	0.78 seconds
Started	Mar 12 12:47:54 PM PDT 24
Finished	Mar 12 12:47:55 PM PDT 24
Peak memory	199752 kb
Host	smart-271308d1-dabf-46cf-b70b-efd31a560b6a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80484398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.80484398
Directory	/workspace/35.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/35.clkmgr_div_intersig_mubi.3182809500
Short name	T233
Test name
Test status
Simulation time	21631721 ps
CPU time	0.86 seconds
Started	Mar 12 12:47:55 PM PDT 24
Finished	Mar 12 12:47:56 PM PDT 24
Peak memory	200736 kb
Host	smart-9d5dd4b5-1439-464b-b313-ca8de4017c09
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182809500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.3182809500
Directory	/workspace/35.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_extclk.1694573988
Short name	T213
Test name
Test status
Simulation time	21273780 ps
CPU time	0.84 seconds
Started	Mar 12 12:47:57 PM PDT 24
Finished	Mar 12 12:47:58 PM PDT 24
Peak memory	200820 kb
Host	smart-9d9619e2-08dd-4c07-80da-7376941e6fe8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694573988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.1694573988
Directory	/workspace/35.clkmgr_extclk/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency.1198391508
Short name	T105
Test name
Test status
Simulation time	1754587074 ps
CPU time	13.62 seconds
Started	Mar 12 12:47:55 PM PDT 24
Finished	Mar 12 12:48:09 PM PDT 24
Peak memory	201008 kb
Host	smart-0ea8c0dc-b208-4f7b-8523-5baa49947908
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198391508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1198391508
Directory	/workspace/35.clkmgr_frequency/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency_timeout.298516102
Short name	T532
Test name
Test status
Simulation time	1477373769 ps
CPU time	6.53 seconds
Started	Mar 12 12:48:10 PM PDT 24
Finished	Mar 12 12:48:18 PM PDT 24
Peak memory	200928 kb
Host	smart-8ff8edd4-6564-456b-ad8b-b982ecac21d6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298516102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_ti meout.298516102
Directory	/workspace/35.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3095151019
Short name	T500
Test name
Test status
Simulation time	25041390 ps
CPU time	0.78 seconds
Started	Mar 12 12:47:55 PM PDT 24
Finished	Mar 12 12:47:56 PM PDT 24
Peak memory	200844 kb
Host	smart-55823e19-fba3-4e46-b954-0cf64225815d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095151019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.3095151019
Directory	/workspace/35.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.3474223918
Short name	T561
Test name
Test status
Simulation time	55831799 ps
CPU time	0.91 seconds
Started	Mar 12 12:48:00 PM PDT 24
Finished	Mar 12 12:48:01 PM PDT 24
Peak memory	200724 kb
Host	smart-b0568c6d-2928-4ee1-89f9-6858fc81e53e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474223918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.clkmgr_lc_clk_byp_req_intersig_mubi.3474223918
Directory	/workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.4003979749
Short name	T716
Test name
Test status
Simulation time	45194329 ps
CPU time	0.85 seconds
Started	Mar 12 12:47:54 PM PDT 24
Finished	Mar 12 12:47:55 PM PDT 24
Peak memory	200676 kb
Host	smart-c5bc14d3-5c23-4c43-b431-c752ab17114f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003979749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.clkmgr_lc_ctrl_intersig_mubi.4003979749
Directory	/workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_peri.314701245
Short name	T696
Test name
Test status
Simulation time	14574819 ps
CPU time	0.81 seconds
Started	Mar 12 12:47:55 PM PDT 24
Finished	Mar 12 12:47:56 PM PDT 24
Peak memory	200660 kb
Host	smart-b97e0b3a-8d54-42fd-a6fa-fd58657be0a2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314701245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.314701245
Directory	/workspace/35.clkmgr_peri/latest

Test location	/workspace/coverage/default/35.clkmgr_regwen.208676084
Short name	T490
Test name
Test status
Simulation time	1039380747 ps
CPU time	3.9 seconds
Started	Mar 12 12:48:06 PM PDT 24
Finished	Mar 12 12:48:11 PM PDT 24
Peak memory	201064 kb
Host	smart-ab5a822c-911d-4458-bdfb-cb9af41844ca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208676084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.208676084
Directory	/workspace/35.clkmgr_regwen/latest

Test location	/workspace/coverage/default/35.clkmgr_smoke.942169903
Short name	T804
Test name
Test status
Simulation time	27680839 ps
CPU time	0.82 seconds
Started	Mar 12 12:47:59 PM PDT 24
Finished	Mar 12 12:48:00 PM PDT 24
Peak memory	200796 kb
Host	smart-457aa9df-446c-4ac6-b2ab-f8db4ae76059
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942169903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.942169903
Directory	/workspace/35.clkmgr_smoke/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all.1744375375
Short name	T491
Test name
Test status
Simulation time	40838830 ps
CPU time	0.91 seconds
Started	Mar 12 12:47:53 PM PDT 24
Finished	Mar 12 12:47:55 PM PDT 24
Peak memory	200784 kb
Host	smart-f2ea8e6a-9b62-46f6-a0e1-2b2f2dcc37a0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744375375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.1744375375
Directory	/workspace/35.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.117739132
Short name	T493
Test name
Test status
Simulation time	79364155884 ps
CPU time	717.2 seconds
Started	Mar 12 12:47:59 PM PDT 24
Finished	Mar 12 12:59:56 PM PDT 24
Peak memory	209516 kb
Host	smart-955d675b-a081-4f20-97de-104e26fca8eb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=117739132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.117739132
Directory	/workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.clkmgr_trans.3962897054
Short name	T410
Test name
Test status
Simulation time	36725802 ps
CPU time	0.93 seconds
Started	Mar 12 12:47:52 PM PDT 24
Finished	Mar 12 12:47:54 PM PDT 24
Peak memory	200796 kb
Host	smart-d74ca794-0eaa-42ff-92b0-7f83cc796d89
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962897054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.3962897054
Directory	/workspace/35.clkmgr_trans/latest

Test location	/workspace/coverage/default/36.clkmgr_alert_test.2863653191
Short name	T572
Test name
Test status
Simulation time	42080466 ps
CPU time	0.85 seconds
Started	Mar 12 12:48:05 PM PDT 24
Finished	Mar 12 12:48:07 PM PDT 24
Peak memory	200816 kb
Host	smart-31447e89-6b73-4a31-bac9-9e79100f0cd2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863653191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk mgr_alert_test.2863653191
Directory	/workspace/36.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.3085917093
Short name	T408
Test name
Test status
Simulation time	46614227 ps
CPU time	1 seconds
Started	Mar 12 12:47:55 PM PDT 24
Finished	Mar 12 12:47:56 PM PDT 24
Peak memory	200812 kb
Host	smart-7b325426-174a-4d0a-8dee-f98303bec085
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085917093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.3085917093
Directory	/workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_status.1960920023
Short name	T682
Test name
Test status
Simulation time	24647850 ps
CPU time	0.71 seconds
Started	Mar 12 12:47:57 PM PDT 24
Finished	Mar 12 12:47:58 PM PDT 24
Peak memory	200772 kb
Host	smart-5c54dc9f-7a41-4958-a90d-4ba73cee8619
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960920023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.1960920023
Directory	/workspace/36.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/36.clkmgr_div_intersig_mubi.1672933256
Short name	T433
Test name
Test status
Simulation time	55054061 ps
CPU time	0.84 seconds
Started	Mar 12 12:48:00 PM PDT 24
Finished	Mar 12 12:48:01 PM PDT 24
Peak memory	200856 kb
Host	smart-2a021339-6b77-483f-aa25-7dedebbdb718
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672933256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.1672933256
Directory	/workspace/36.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_extclk.2101522079
Short name	T628
Test name
Test status
Simulation time	21104872 ps
CPU time	0.8 seconds
Started	Mar 12 12:48:00 PM PDT 24
Finished	Mar 12 12:48:01 PM PDT 24
Peak memory	200756 kb
Host	smart-9f851077-2b84-4b54-9762-88bdf752f909
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101522079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.2101522079
Directory	/workspace/36.clkmgr_extclk/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency.3416270849
Short name	T404
Test name
Test status
Simulation time	1642213194 ps
CPU time	11.82 seconds
Started	Mar 12 12:47:58 PM PDT 24
Finished	Mar 12 12:48:09 PM PDT 24
Peak memory	200812 kb
Host	smart-4bc1cb68-2edc-4ef1-ba53-8f4764f1440d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416270849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.3416270849
Directory	/workspace/36.clkmgr_frequency/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency_timeout.3535409797
Short name	T697
Test name
Test status
Simulation time	509280818 ps
CPU time	3.46 seconds
Started	Mar 12 12:48:12 PM PDT 24
Finished	Mar 12 12:48:16 PM PDT 24
Peak memory	200852 kb
Host	smart-0bc22dc3-95d2-4483-993e-37af3ebb38f9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535409797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t imeout.3535409797
Directory	/workspace/36.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/36.clkmgr_idle_intersig_mubi.1845277605
Short name	T730
Test name
Test status
Simulation time	52023388 ps
CPU time	0.84 seconds
Started	Mar 12 12:48:00 PM PDT 24
Finished	Mar 12 12:48:01 PM PDT 24
Peak memory	200840 kb
Host	smart-e0f1978c-32f4-4fa4-b979-57f662138b26
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845277605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.1845277605
Directory	/workspace/36.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.749219459
Short name	T601
Test name
Test status
Simulation time	31207609 ps
CPU time	0.89 seconds
Started	Mar 12 12:47:53 PM PDT 24
Finished	Mar 12 12:47:54 PM PDT 24
Peak memory	200716 kb
Host	smart-88ab094f-de87-401f-b020-6eb400176412
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749219459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.clkmgr_lc_clk_byp_req_intersig_mubi.749219459
Directory	/workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.1377403240
Short name	T244
Test name
Test status
Simulation time	24123820 ps
CPU time	0.83 seconds
Started	Mar 12 12:48:00 PM PDT 24
Finished	Mar 12 12:48:01 PM PDT 24
Peak memory	200836 kb
Host	smart-952e9eb3-540b-4da9-9cc6-819fe7492735
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377403240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.clkmgr_lc_ctrl_intersig_mubi.1377403240
Directory	/workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_peri.1427427267
Short name	T169
Test name
Test status
Simulation time	59471257 ps
CPU time	0.86 seconds
Started	Mar 12 12:48:02 PM PDT 24
Finished	Mar 12 12:48:03 PM PDT 24
Peak memory	200588 kb
Host	smart-98f100da-c8be-4f14-9ff8-d9dc41c31cd1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427427267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.1427427267
Directory	/workspace/36.clkmgr_peri/latest

Test location	/workspace/coverage/default/36.clkmgr_regwen.2801157845
Short name	T133
Test name
Test status
Simulation time	1020264268 ps
CPU time	5.74 seconds
Started	Mar 12 12:47:52 PM PDT 24
Finished	Mar 12 12:47:58 PM PDT 24
Peak memory	201048 kb
Host	smart-5fc6e94c-b709-4976-afa0-2d795be7c661
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801157845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.2801157845
Directory	/workspace/36.clkmgr_regwen/latest

Test location	/workspace/coverage/default/36.clkmgr_smoke.1968898746
Short name	T631
Test name
Test status
Simulation time	63110529 ps
CPU time	0.97 seconds
Started	Mar 12 12:47:57 PM PDT 24
Finished	Mar 12 12:47:58 PM PDT 24
Peak memory	200772 kb
Host	smart-a91fc2ea-d2d9-45f6-bd1a-50de9b6e2a8c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968898746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.1968898746
Directory	/workspace/36.clkmgr_smoke/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all.3467371122
Short name	T108
Test name
Test status
Simulation time	2712886284 ps
CPU time	10.04 seconds
Started	Mar 12 12:47:54 PM PDT 24
Finished	Mar 12 12:48:04 PM PDT 24
Peak memory	201084 kb
Host	smart-081ebad8-4fcd-49a0-9e9a-ca8760707ab0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467371122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.3467371122
Directory	/workspace/36.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.487238760
Short name	T151
Test name
Test status
Simulation time	150545687822 ps
CPU time	1043 seconds
Started	Mar 12 12:47:58 PM PDT 24
Finished	Mar 12 01:05:21 PM PDT 24
Peak memory	217652 kb
Host	smart-cbc5dbf8-51ee-420e-a99d-86b3d69ff66a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=487238760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.487238760
Directory	/workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.clkmgr_trans.2909427814
Short name	T460
Test name
Test status
Simulation time	51284892 ps
CPU time	1.03 seconds
Started	Mar 12 12:47:59 PM PDT 24
Finished	Mar 12 12:48:00 PM PDT 24
Peak memory	200840 kb
Host	smart-75427b64-ff5c-4a1c-81fe-5d5758787df9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909427814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.2909427814
Directory	/workspace/36.clkmgr_trans/latest

Test location	/workspace/coverage/default/37.clkmgr_alert_test.1324223713
Short name	T654
Test name
Test status
Simulation time	18676524 ps
CPU time	0.79 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:23 PM PDT 24
Peak memory	200676 kb
Host	smart-5ad47f1a-b2e3-4e4e-a879-da5e6363d922
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324223713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk mgr_alert_test.1324223713
Directory	/workspace/37.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.670454779
Short name	T86
Test name
Test status
Simulation time	31558657 ps
CPU time	0.95 seconds
Started	Mar 12 12:48:19 PM PDT 24
Finished	Mar 12 12:48:20 PM PDT 24
Peak memory	200776 kb
Host	smart-dd308c9c-40d5-408d-a3a5-16e60772c3c1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670454779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.670454779
Directory	/workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_status.116204577
Short name	T485
Test name
Test status
Simulation time	46335494 ps
CPU time	0.78 seconds
Started	Mar 12 12:48:11 PM PDT 24
Finished	Mar 12 12:48:12 PM PDT 24
Peak memory	199784 kb
Host	smart-c2862714-00ed-4771-9a92-905852c99eeb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116204577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.116204577
Directory	/workspace/37.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/37.clkmgr_div_intersig_mubi.4030731482
Short name	T530
Test name
Test status
Simulation time	17663511 ps
CPU time	0.73 seconds
Started	Mar 12 12:48:07 PM PDT 24
Finished	Mar 12 12:48:10 PM PDT 24
Peak memory	200660 kb
Host	smart-dd97fbed-2df0-4782-be1c-8e37108cf667
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030731482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.4030731482
Directory	/workspace/37.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_extclk.470840792
Short name	T164
Test name
Test status
Simulation time	67986978 ps
CPU time	0.98 seconds
Started	Mar 12 12:48:11 PM PDT 24
Finished	Mar 12 12:48:13 PM PDT 24
Peak memory	200804 kb
Host	smart-69da400b-8bcb-47e5-9caf-963fd8d3a805
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470840792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.470840792
Directory	/workspace/37.clkmgr_extclk/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency.70086342
Short name	T301
Test name
Test status
Simulation time	1881375616 ps
CPU time	10.62 seconds
Started	Mar 12 12:48:08 PM PDT 24
Finished	Mar 12 12:48:21 PM PDT 24
Peak memory	201052 kb
Host	smart-b6fe4687-9874-4b65-9ca6-5a4f1189dccc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70086342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.70086342
Directory	/workspace/37.clkmgr_frequency/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency_timeout.4142264925
Short name	T712
Test name
Test status
Simulation time	862437506 ps
CPU time	4.96 seconds
Started	Mar 12 12:48:04 PM PDT 24
Finished	Mar 12 12:48:09 PM PDT 24
Peak memory	200864 kb
Host	smart-18fbd374-4923-49dd-970c-61ec06c1ffd3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142264925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t imeout.4142264925
Directory	/workspace/37.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/37.clkmgr_idle_intersig_mubi.526919494
Short name	T204
Test name
Test status
Simulation time	26752609 ps
CPU time	0.78 seconds
Started	Mar 12 12:48:07 PM PDT 24
Finished	Mar 12 12:48:10 PM PDT 24
Peak memory	200780 kb
Host	smart-5bf91e08-cf63-4750-9a28-f349d860a935
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526919494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.clkmgr_idle_intersig_mubi.526919494
Directory	/workspace/37.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.883752419
Short name	T775
Test name
Test status
Simulation time	139227709 ps
CPU time	1.15 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200728 kb
Host	smart-01b362f4-4e67-4540-a8b4-5238e95375ef
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883752419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.clkmgr_lc_clk_byp_req_intersig_mubi.883752419
Directory	/workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.713607321
Short name	T723
Test name
Test status
Simulation time	79811887 ps
CPU time	0.9 seconds
Started	Mar 12 12:48:08 PM PDT 24
Finished	Mar 12 12:48:11 PM PDT 24
Peak memory	200732 kb
Host	smart-35125602-b55c-41e7-adc1-49852e25927c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713607321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.clkmgr_lc_ctrl_intersig_mubi.713607321
Directory	/workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_peri.3384390208
Short name	T461
Test name
Test status
Simulation time	43983611 ps
CPU time	0.81 seconds
Started	Mar 12 12:48:09 PM PDT 24
Finished	Mar 12 12:48:11 PM PDT 24
Peak memory	200812 kb
Host	smart-9f92067c-6d8b-4559-866f-a7181054388e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384390208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.3384390208
Directory	/workspace/37.clkmgr_peri/latest

Test location	/workspace/coverage/default/37.clkmgr_regwen.4037520281
Short name	T71
Test name
Test status
Simulation time	1032039587 ps
CPU time	3.91 seconds
Started	Mar 12 12:48:06 PM PDT 24
Finished	Mar 12 12:48:11 PM PDT 24
Peak memory	201004 kb
Host	smart-be6c9ae4-79b5-461c-a824-004326a604de
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037520281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.4037520281
Directory	/workspace/37.clkmgr_regwen/latest

Test location	/workspace/coverage/default/37.clkmgr_smoke.424102907
Short name	T163
Test name
Test status
Simulation time	60591537 ps
CPU time	0.97 seconds
Started	Mar 12 12:47:52 PM PDT 24
Finished	Mar 12 12:47:54 PM PDT 24
Peak memory	200688 kb
Host	smart-7f0aa959-92fb-4ffd-afa3-fea17a69c5b5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424102907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.424102907
Directory	/workspace/37.clkmgr_smoke/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all.2375346245
Short name	T614
Test name
Test status
Simulation time	3742253379 ps
CPU time	17.33 seconds
Started	Mar 12 12:48:12 PM PDT 24
Finished	Mar 12 12:48:31 PM PDT 24
Peak memory	201056 kb
Host	smart-696cf9f1-d0e3-4dbd-b52f-b6521cbbcbeb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375346245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.2375346245
Directory	/workspace/37.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.1419137619
Short name	T274
Test name
Test status
Simulation time	68429671299 ps
CPU time	647.46 seconds
Started	Mar 12 12:48:07 PM PDT 24
Finished	Mar 12 12:58:57 PM PDT 24
Peak memory	212104 kb
Host	smart-efd63642-89c3-4e54-b3d9-26bc251ecc02
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1419137619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.1419137619
Directory	/workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.clkmgr_trans.3743578300
Short name	T744
Test name
Test status
Simulation time	82282809 ps
CPU time	1.03 seconds
Started	Mar 12 12:48:08 PM PDT 24
Finished	Mar 12 12:48:12 PM PDT 24
Peak memory	200812 kb
Host	smart-33dfa07e-cb83-46a3-9801-3587cc5c7ae0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743578300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.3743578300
Directory	/workspace/37.clkmgr_trans/latest

Test location	/workspace/coverage/default/38.clkmgr_alert_test.4070440577
Short name	T721
Test name
Test status
Simulation time	35234604 ps
CPU time	0.77 seconds
Started	Mar 12 12:48:09 PM PDT 24
Finished	Mar 12 12:48:12 PM PDT 24
Peak memory	200888 kb
Host	smart-6951e613-bd03-4992-932b-380171bf7173
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070440577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk mgr_alert_test.4070440577
Directory	/workspace/38.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.448389493
Short name	T46
Test name
Test status
Simulation time	20151022 ps
CPU time	0.84 seconds
Started	Mar 12 12:48:08 PM PDT 24
Finished	Mar 12 12:48:10 PM PDT 24
Peak memory	200808 kb
Host	smart-2c0796d4-1d76-4af5-843c-556983744a40
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448389493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.448389493
Directory	/workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_div_intersig_mubi.1176546104
Short name	T382
Test name
Test status
Simulation time	43064673 ps
CPU time	0.91 seconds
Started	Mar 12 12:48:14 PM PDT 24
Finished	Mar 12 12:48:15 PM PDT 24
Peak memory	200772 kb
Host	smart-4149f4e4-82c6-45c3-9d03-9de8343481c2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176546104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.1176546104
Directory	/workspace/38.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_extclk.1462558707
Short name	T749
Test name
Test status
Simulation time	160173008 ps
CPU time	1.28 seconds
Started	Mar 12 12:48:16 PM PDT 24
Finished	Mar 12 12:48:17 PM PDT 24
Peak memory	200720 kb
Host	smart-0ac72883-ee52-4372-aebf-777d6a83f60e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462558707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.1462558707
Directory	/workspace/38.clkmgr_extclk/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency.3009429122
Short name	T371
Test name
Test status
Simulation time	1168127706 ps
CPU time	6.77 seconds
Started	Mar 12 12:48:08 PM PDT 24
Finished	Mar 12 12:48:17 PM PDT 24
Peak memory	200796 kb
Host	smart-dda12392-0032-4ef2-b14a-95f5471f5fca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009429122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.3009429122
Directory	/workspace/38.clkmgr_frequency/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency_timeout.2604278232
Short name	T5
Test name
Test status
Simulation time	615125416 ps
CPU time	5.02 seconds
Started	Mar 12 12:48:15 PM PDT 24
Finished	Mar 12 12:48:21 PM PDT 24
Peak memory	200776 kb
Host	smart-6d11841a-bd87-4026-a5e1-cf62859f6aa9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604278232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t imeout.2604278232
Directory	/workspace/38.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/38.clkmgr_idle_intersig_mubi.3084751622
Short name	T534
Test name
Test status
Simulation time	23687929 ps
CPU time	0.84 seconds
Started	Mar 12 12:48:10 PM PDT 24
Finished	Mar 12 12:48:12 PM PDT 24
Peak memory	200828 kb
Host	smart-121602e3-7283-44de-afd7-366b4b21794d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084751622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.3084751622
Directory	/workspace/38.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.802298641
Short name	T655
Test name
Test status
Simulation time	41164301 ps
CPU time	0.83 seconds
Started	Mar 12 12:48:05 PM PDT 24
Finished	Mar 12 12:48:07 PM PDT 24
Peak memory	200756 kb
Host	smart-2e8ee027-c752-49b0-9b46-6a91f6438b2b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802298641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.clkmgr_lc_clk_byp_req_intersig_mubi.802298641
Directory	/workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.324970080
Short name	T710
Test name
Test status
Simulation time	17802891 ps
CPU time	0.86 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:23 PM PDT 24
Peak memory	200700 kb
Host	smart-0073f9df-4eb7-4bc5-9dd4-8058e816f7a8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324970080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.clkmgr_lc_ctrl_intersig_mubi.324970080
Directory	/workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_peri.3615374582
Short name	T543
Test name
Test status
Simulation time	27025477 ps
CPU time	0.73 seconds
Started	Mar 12 12:48:14 PM PDT 24
Finished	Mar 12 12:48:15 PM PDT 24
Peak memory	200588 kb
Host	smart-80237c84-2e25-43bd-819e-51b742a5e0d1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615374582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.3615374582
Directory	/workspace/38.clkmgr_peri/latest

Test location	/workspace/coverage/default/38.clkmgr_regwen.44496435
Short name	T588
Test name
Test status
Simulation time	1375453036 ps
CPU time	4.51 seconds
Started	Mar 12 12:48:08 PM PDT 24
Finished	Mar 12 12:48:15 PM PDT 24
Peak memory	201016 kb
Host	smart-ae14be3e-48d0-40b6-9353-12eebb00c65c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44496435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.44496435
Directory	/workspace/38.clkmgr_regwen/latest

Test location	/workspace/coverage/default/38.clkmgr_smoke.900145580
Short name	T273
Test name
Test status
Simulation time	58818347 ps
CPU time	0.88 seconds
Started	Mar 12 12:48:08 PM PDT 24
Finished	Mar 12 12:48:11 PM PDT 24
Peak memory	200820 kb
Host	smart-508b18a6-cc4a-4336-b92d-77d382432189
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900145580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.900145580
Directory	/workspace/38.clkmgr_smoke/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all.1829374249
Short name	T592
Test name
Test status
Simulation time	9060113338 ps
CPU time	65.78 seconds
Started	Mar 12 12:48:13 PM PDT 24
Finished	Mar 12 12:49:20 PM PDT 24
Peak memory	201224 kb
Host	smart-6b1e6db3-54f9-4d3b-8e2a-994b42b8eded
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829374249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.1829374249
Directory	/workspace/38.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.3051353689
Short name	T428
Test name
Test status
Simulation time	126446291395 ps
CPU time	752.1 seconds
Started	Mar 12 12:48:08 PM PDT 24
Finished	Mar 12 01:00:43 PM PDT 24
Peak memory	209488 kb
Host	smart-a5f01323-a6f6-4857-b8ba-71db3803d59a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3051353689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.3051353689
Directory	/workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.clkmgr_trans.1670907268
Short name	T574
Test name
Test status
Simulation time	25118762 ps
CPU time	0.94 seconds
Started	Mar 12 12:48:11 PM PDT 24
Finished	Mar 12 12:48:13 PM PDT 24
Peak memory	200812 kb
Host	smart-34a375fa-35d4-4102-aa12-c62b968139dd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670907268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.1670907268
Directory	/workspace/38.clkmgr_trans/latest

Test location	/workspace/coverage/default/39.clkmgr_alert_test.2962908196
Short name	T358
Test name
Test status
Simulation time	105726905 ps
CPU time	1.03 seconds
Started	Mar 12 12:48:12 PM PDT 24
Finished	Mar 12 12:48:14 PM PDT 24
Peak memory	200924 kb
Host	smart-40bc5b37-6ae5-4020-bc3a-ca9dc9cf06b7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962908196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk mgr_alert_test.2962908196
Directory	/workspace/39.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.4276563480
Short name	T842
Test name
Test status
Simulation time	26805108 ps
CPU time	0.91 seconds
Started	Mar 12 12:48:25 PM PDT 24
Finished	Mar 12 12:48:27 PM PDT 24
Peak memory	200708 kb
Host	smart-da66a97b-0060-47f7-9472-2a1b4585c44e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276563480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.4276563480
Directory	/workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_status.2815784915
Short name	T149
Test name
Test status
Simulation time	16817624 ps
CPU time	0.72 seconds
Started	Mar 12 12:48:17 PM PDT 24
Finished	Mar 12 12:48:18 PM PDT 24
Peak memory	200648 kb
Host	smart-67629039-ac51-4c54-9e5e-389ce24df9aa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815784915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.2815784915
Directory	/workspace/39.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/39.clkmgr_div_intersig_mubi.1651405502
Short name	T388
Test name
Test status
Simulation time	112498628 ps
CPU time	1.03 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:23 PM PDT 24
Peak memory	200780 kb
Host	smart-91ff5a39-7774-4d57-bbd5-12fe5d347e33
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651405502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.1651405502
Directory	/workspace/39.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_extclk.2313339690
Short name	T357
Test name
Test status
Simulation time	23963464 ps
CPU time	0.83 seconds
Started	Mar 12 12:48:08 PM PDT 24
Finished	Mar 12 12:48:11 PM PDT 24
Peak memory	200868 kb
Host	smart-f0c359d3-d76a-4a6c-b23b-dd5330496d29
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313339690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.2313339690
Directory	/workspace/39.clkmgr_extclk/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency.3451933701
Short name	T597
Test name
Test status
Simulation time	1527534433 ps
CPU time	9.08 seconds
Started	Mar 12 12:48:07 PM PDT 24
Finished	Mar 12 12:48:18 PM PDT 24
Peak memory	200812 kb
Host	smart-356cb371-40a9-4457-9add-b66a60d22557
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451933701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.3451933701
Directory	/workspace/39.clkmgr_frequency/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency_timeout.2053675582
Short name	T159
Test name
Test status
Simulation time	2155651653 ps
CPU time	9 seconds
Started	Mar 12 12:48:14 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200916 kb
Host	smart-5f089d82-6af9-4c51-b4c9-f6896bb8df8c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053675582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t imeout.2053675582
Directory	/workspace/39.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/39.clkmgr_idle_intersig_mubi.555617494
Short name	T350
Test name
Test status
Simulation time	71442883 ps
CPU time	1 seconds
Started	Mar 12 12:48:16 PM PDT 24
Finished	Mar 12 12:48:17 PM PDT 24
Peak memory	200856 kb
Host	smart-bf8354e1-e3f7-4dbe-9667-955d5f0633e9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555617494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.clkmgr_idle_intersig_mubi.555617494
Directory	/workspace/39.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.1435713414
Short name	T214
Test name
Test status
Simulation time	23593919 ps
CPU time	0.86 seconds
Started	Mar 12 12:48:09 PM PDT 24
Finished	Mar 12 12:48:11 PM PDT 24
Peak memory	200772 kb
Host	smart-1f79cc65-42c7-4730-90f9-2b9426d6930e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435713414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.clkmgr_lc_clk_byp_req_intersig_mubi.1435713414
Directory	/workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.984506574
Short name	T563
Test name
Test status
Simulation time	78041518 ps
CPU time	0.99 seconds
Started	Mar 12 12:48:16 PM PDT 24
Finished	Mar 12 12:48:17 PM PDT 24
Peak memory	200820 kb
Host	smart-ecc72d2a-2ea9-41ec-b2b5-82b99fe67120
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984506574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.clkmgr_lc_ctrl_intersig_mubi.984506574
Directory	/workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_peri.4199434141
Short name	T794
Test name
Test status
Simulation time	14715067 ps
CPU time	0.75 seconds
Started	Mar 12 12:48:08 PM PDT 24
Finished	Mar 12 12:48:10 PM PDT 24
Peak memory	200680 kb
Host	smart-8a22e9c8-cb59-4f51-bce8-4226546f7c8d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199434141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.4199434141
Directory	/workspace/39.clkmgr_peri/latest

Test location	/workspace/coverage/default/39.clkmgr_regwen.182184416
Short name	T94
Test name
Test status
Simulation time	1129237561 ps
CPU time	4.05 seconds
Started	Mar 12 12:48:14 PM PDT 24
Finished	Mar 12 12:48:19 PM PDT 24
Peak memory	201040 kb
Host	smart-b53d4f78-04fe-46aa-a06c-4d045c54651e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182184416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.182184416
Directory	/workspace/39.clkmgr_regwen/latest

Test location	/workspace/coverage/default/39.clkmgr_smoke.1241034684
Short name	T123
Test name
Test status
Simulation time	76937093 ps
CPU time	1.06 seconds
Started	Mar 12 12:48:04 PM PDT 24
Finished	Mar 12 12:48:05 PM PDT 24
Peak memory	200804 kb
Host	smart-15f81ae9-bc5f-41a3-a696-d593c6b013f8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241034684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.1241034684
Directory	/workspace/39.clkmgr_smoke/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all.3765575569
Short name	T467
Test name
Test status
Simulation time	9652339164 ps
CPU time	40.19 seconds
Started	Mar 12 12:48:07 PM PDT 24
Finished	Mar 12 12:48:49 PM PDT 24
Peak memory	201276 kb
Host	smart-801e8aba-45d9-4049-897f-8ed3e13b3ae4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765575569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.3765575569
Directory	/workspace/39.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.3829326011
Short name	T684
Test name
Test status
Simulation time	17191100677 ps
CPU time	245.37 seconds
Started	Mar 12 12:48:12 PM PDT 24
Finished	Mar 12 12:52:18 PM PDT 24
Peak memory	209496 kb
Host	smart-a2343354-c195-4fcb-a133-1cc06de1fc3e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3829326011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.3829326011
Directory	/workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.clkmgr_trans.2042620716
Short name	T178
Test name
Test status
Simulation time	233025614 ps
CPU time	1.5 seconds
Started	Mar 12 12:48:19 PM PDT 24
Finished	Mar 12 12:48:21 PM PDT 24
Peak memory	200772 kb
Host	smart-c8037289-ed1b-49ca-9a7b-baded4672d0e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042620716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.2042620716
Directory	/workspace/39.clkmgr_trans/latest

Test location	/workspace/coverage/default/4.clkmgr_alert_test.2694783289
Short name	T317
Test name
Test status
Simulation time	24281539 ps
CPU time	0.87 seconds
Started	Mar 12 12:46:30 PM PDT 24
Finished	Mar 12 12:46:31 PM PDT 24
Peak memory	200920 kb
Host	smart-0ead1d06-62e9-437b-8f73-e68ac6e19130
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694783289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm gr_alert_test.2694783289
Directory	/workspace/4.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.432246005
Short name	T762
Test name
Test status
Simulation time	18813200 ps
CPU time	0.85 seconds
Started	Mar 12 12:46:33 PM PDT 24
Finished	Mar 12 12:46:34 PM PDT 24
Peak memory	200828 kb
Host	smart-61f5d279-6b09-469f-bbed-07c29199d671
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432246005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.432246005
Directory	/workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_status.1710400286
Short name	T48
Test name
Test status
Simulation time	24837981 ps
CPU time	0.76 seconds
Started	Mar 12 12:46:32 PM PDT 24
Finished	Mar 12 12:46:33 PM PDT 24
Peak memory	199780 kb
Host	smart-feb54019-31f6-40d2-8f1b-8c635b08d79c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710400286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.1710400286
Directory	/workspace/4.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/4.clkmgr_div_intersig_mubi.2550128407
Short name	T511
Test name
Test status
Simulation time	15429358 ps
CPU time	0.72 seconds
Started	Mar 12 12:46:32 PM PDT 24
Finished	Mar 12 12:46:33 PM PDT 24
Peak memory	200688 kb
Host	smart-1b287fb6-dc96-4243-b7d9-03abce9094ac
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550128407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.2550128407
Directory	/workspace/4.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_extclk.1315652714
Short name	T313
Test name
Test status
Simulation time	56224985 ps
CPU time	0.88 seconds
Started	Mar 12 12:46:30 PM PDT 24
Finished	Mar 12 12:46:31 PM PDT 24
Peak memory	200760 kb
Host	smart-7c191a21-8812-4768-91df-f9099857e3f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315652714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.1315652714
Directory	/workspace/4.clkmgr_extclk/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency.2013721382
Short name	T731
Test name
Test status
Simulation time	2640630343 ps
CPU time	10.18 seconds
Started	Mar 12 12:46:30 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	201108 kb
Host	smart-56f205da-226b-4714-b9b2-5ede341b84af
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013721382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.2013721382
Directory	/workspace/4.clkmgr_frequency/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency_timeout.402176712
Short name	T464
Test name
Test status
Simulation time	135131030 ps
CPU time	1.68 seconds
Started	Mar 12 12:46:36 PM PDT 24
Finished	Mar 12 12:46:38 PM PDT 24
Peak memory	200816 kb
Host	smart-ac3fcf73-da75-4c0a-8f42-2f98fa9ddf19
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402176712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_tim eout.402176712
Directory	/workspace/4.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/4.clkmgr_idle_intersig_mubi.19332879
Short name	T770
Test name
Test status
Simulation time	37035613 ps
CPU time	0.97 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	200816 kb
Host	smart-1ed70a9d-0c38-4053-a46b-d5f42a6fc850
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19332879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. clkmgr_idle_intersig_mubi.19332879
Directory	/workspace/4.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.3423935160
Short name	T718
Test name
Test status
Simulation time	93974185 ps
CPU time	1.07 seconds
Started	Mar 12 12:46:39 PM PDT 24
Finished	Mar 12 12:46:43 PM PDT 24
Peak memory	200824 kb
Host	smart-887203bc-82ef-46fb-83c7-304277da3373
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423935160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_clk_byp_req_intersig_mubi.3423935160
Directory	/workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.3798757824
Short name	T548
Test name
Test status
Simulation time	38153326 ps
CPU time	0.84 seconds
Started	Mar 12 12:46:32 PM PDT 24
Finished	Mar 12 12:46:33 PM PDT 24
Peak memory	200824 kb
Host	smart-5c71bb35-bbce-4000-a13c-725835fa67cb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798757824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_ctrl_intersig_mubi.3798757824
Directory	/workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_peri.2659569610
Short name	T618
Test name
Test status
Simulation time	18943727 ps
CPU time	0.76 seconds
Started	Mar 12 12:46:34 PM PDT 24
Finished	Mar 12 12:46:35 PM PDT 24
Peak memory	200656 kb
Host	smart-25d7cafd-09ea-4100-baac-532f88e15ec9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659569610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.2659569610
Directory	/workspace/4.clkmgr_peri/latest

Test location	/workspace/coverage/default/4.clkmgr_sec_cm.3192463821
Short name	T50
Test name
Test status
Simulation time	400038027 ps
CPU time	2.54 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:42 PM PDT 24
Peak memory	215820 kb
Host	smart-3ca1d3c2-631d-4479-b326-34edc841da80
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192463821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg r_sec_cm.3192463821
Directory	/workspace/4.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/4.clkmgr_smoke.2695357223
Short name	T417
Test name
Test status
Simulation time	40514686 ps
CPU time	0.89 seconds
Started	Mar 12 12:46:35 PM PDT 24
Finished	Mar 12 12:46:36 PM PDT 24
Peak memory	200780 kb
Host	smart-e7eb31d3-5387-4f0d-a043-dff281d9f7b3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695357223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.2695357223
Directory	/workspace/4.clkmgr_smoke/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all.55376489
Short name	T808
Test name
Test status
Simulation time	3789550525 ps
CPU time	18.93 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:58 PM PDT 24
Peak memory	201132 kb
Host	smart-a24a0450-5b64-4f01-8cce-e5316389142b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55376489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .clkmgr_stress_all.55376489
Directory	/workspace/4.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.1944534481
Short name	T668
Test name
Test status
Simulation time	194649244730 ps
CPU time	1097.14 seconds
Started	Mar 12 12:46:40 PM PDT 24
Finished	Mar 12 01:04:59 PM PDT 24
Peak memory	209556 kb
Host	smart-5fad93a3-76f7-4cbd-b621-5776ae0f8680
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1944534481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.1944534481
Directory	/workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.clkmgr_trans.2718739218
Short name	T829
Test name
Test status
Simulation time	24310981 ps
CPU time	0.75 seconds
Started	Mar 12 12:46:36 PM PDT 24
Finished	Mar 12 12:46:38 PM PDT 24
Peak memory	200804 kb
Host	smart-537e58cc-b67f-4bda-8b67-0a5b719db473
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718739218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.2718739218
Directory	/workspace/4.clkmgr_trans/latest

Test location	/workspace/coverage/default/40.clkmgr_alert_test.7657876
Short name	T30
Test name
Test status
Simulation time	22802821 ps
CPU time	0.85 seconds
Started	Mar 12 12:48:19 PM PDT 24
Finished	Mar 12 12:48:20 PM PDT 24
Peak memory	200916 kb
Host	smart-935f4857-b9cd-416b-8d68-fdd1ebc42a67
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7657876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr _alert_test.7657876
Directory	/workspace/40.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.266741402
Short name	T220
Test name
Test status
Simulation time	21207372 ps
CPU time	0.85 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200704 kb
Host	smart-f7dbba30-a4d8-4787-a953-6d000d75535e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266741402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.266741402
Directory	/workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_status.1587858103
Short name	T405
Test name
Test status
Simulation time	16895369 ps
CPU time	0.79 seconds
Started	Mar 12 12:48:11 PM PDT 24
Finished	Mar 12 12:48:13 PM PDT 24
Peak memory	199756 kb
Host	smart-47c129e9-d650-4b99-ae54-1487f48a599e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587858103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1587858103
Directory	/workspace/40.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/40.clkmgr_div_intersig_mubi.2629945163
Short name	T340
Test name
Test status
Simulation time	36825051 ps
CPU time	0.81 seconds
Started	Mar 12 12:48:18 PM PDT 24
Finished	Mar 12 12:48:19 PM PDT 24
Peak memory	200788 kb
Host	smart-d5e1604d-2a95-4e90-a58e-924822178da4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629945163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.2629945163
Directory	/workspace/40.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_extclk.4223079857
Short name	T215
Test name
Test status
Simulation time	84615278 ps
CPU time	1.01 seconds
Started	Mar 12 12:48:11 PM PDT 24
Finished	Mar 12 12:48:13 PM PDT 24
Peak memory	200800 kb
Host	smart-0cbde438-31fd-4e81-a0d7-241484d491b5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223079857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.4223079857
Directory	/workspace/40.clkmgr_extclk/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency.1757960766
Short name	T675
Test name
Test status
Simulation time	2009862680 ps
CPU time	10.65 seconds
Started	Mar 12 12:48:08 PM PDT 24
Finished	Mar 12 12:48:21 PM PDT 24
Peak memory	200988 kb
Host	smart-292372b8-c1d1-4137-b1b6-775641e3812b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757960766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.1757960766
Directory	/workspace/40.clkmgr_frequency/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency_timeout.3760184914
Short name	T773
Test name
Test status
Simulation time	734315330 ps
CPU time	5.97 seconds
Started	Mar 12 12:48:07 PM PDT 24
Finished	Mar 12 12:48:16 PM PDT 24
Peak memory	200860 kb
Host	smart-6916e03b-84be-4d2d-bc84-5c30e437524b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760184914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t imeout.3760184914
Directory	/workspace/40.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/40.clkmgr_idle_intersig_mubi.578012439
Short name	T102
Test name
Test status
Simulation time	79681078 ps
CPU time	0.99 seconds
Started	Mar 12 12:48:21 PM PDT 24
Finished	Mar 12 12:48:22 PM PDT 24
Peak memory	200844 kb
Host	smart-7b7ff9b2-9b89-4d2c-80ff-c89b044a048d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578012439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.clkmgr_idle_intersig_mubi.578012439
Directory	/workspace/40.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.3195293471
Short name	T291
Test name
Test status
Simulation time	16254323 ps
CPU time	0.77 seconds
Started	Mar 12 12:48:09 PM PDT 24
Finished	Mar 12 12:48:11 PM PDT 24
Peak memory	200808 kb
Host	smart-96fee8a1-0a3a-4db2-8c8d-c2bddf225c88
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195293471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_clk_byp_req_intersig_mubi.3195293471
Directory	/workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.1357945422
Short name	T193
Test name
Test status
Simulation time	17902985 ps
CPU time	0.83 seconds
Started	Mar 12 12:48:09 PM PDT 24
Finished	Mar 12 12:48:11 PM PDT 24
Peak memory	200732 kb
Host	smart-6223aa55-8ef6-4b6d-a054-749977c9777e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357945422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_ctrl_intersig_mubi.1357945422
Directory	/workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_peri.1616882605
Short name	T740
Test name
Test status
Simulation time	19459103 ps
CPU time	0.8 seconds
Started	Mar 12 12:48:13 PM PDT 24
Finished	Mar 12 12:48:14 PM PDT 24
Peak memory	200748 kb
Host	smart-e72415d9-0f7d-46cd-be17-6f6e05b29c0d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616882605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.1616882605
Directory	/workspace/40.clkmgr_peri/latest

Test location	/workspace/coverage/default/40.clkmgr_regwen.103344019
Short name	T70
Test name
Test status
Simulation time	1342057037 ps
CPU time	4.52 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:28 PM PDT 24
Peak memory	200916 kb
Host	smart-ce595298-c913-4eff-b842-74b347b6a60e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103344019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.103344019
Directory	/workspace/40.clkmgr_regwen/latest

Test location	/workspace/coverage/default/40.clkmgr_smoke.692245353
Short name	T515
Test name
Test status
Simulation time	71989137 ps
CPU time	0.98 seconds
Started	Mar 12 12:48:19 PM PDT 24
Finished	Mar 12 12:48:20 PM PDT 24
Peak memory	200800 kb
Host	smart-75160453-396b-4825-95fb-75744fedc070
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692245353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.692245353
Directory	/workspace/40.clkmgr_smoke/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all.1200331231
Short name	T840
Test name
Test status
Simulation time	5356601882 ps
CPU time	22.84 seconds
Started	Mar 12 12:48:09 PM PDT 24
Finished	Mar 12 12:48:33 PM PDT 24
Peak memory	201172 kb
Host	smart-b1201c34-23ed-45cf-b8a7-ba34ec30ce3f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200331231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.1200331231
Directory	/workspace/40.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.3489820502
Short name	T140
Test name
Test status
Simulation time	283955670144 ps
CPU time	1127.25 seconds
Started	Mar 12 12:48:08 PM PDT 24
Finished	Mar 12 01:06:58 PM PDT 24
Peak memory	212444 kb
Host	smart-a614d77d-8153-46b3-af6b-26a6ba616671
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3489820502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.3489820502
Directory	/workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.clkmgr_trans.1307136131
Short name	T278
Test name
Test status
Simulation time	217728558 ps
CPU time	1.35 seconds
Started	Mar 12 12:48:14 PM PDT 24
Finished	Mar 12 12:48:15 PM PDT 24
Peak memory	200748 kb
Host	smart-10f7d717-2582-454c-922a-0e6da20ce1da
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307136131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.1307136131
Directory	/workspace/40.clkmgr_trans/latest

Test location	/workspace/coverage/default/41.clkmgr_alert_test.4175177004
Short name	T820
Test name
Test status
Simulation time	20717969 ps
CPU time	0.76 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	200840 kb
Host	smart-fd4a76d1-7eb2-4678-98f0-d047d1d76c58
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175177004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk mgr_alert_test.4175177004
Directory	/workspace/41.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1800316336
Short name	T825
Test name
Test status
Simulation time	43623814 ps
CPU time	0.92 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200808 kb
Host	smart-1093b1da-4bc6-4d6e-9e52-239e03cdce42
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800316336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.1800316336
Directory	/workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_status.952177341
Short name	T539
Test name
Test status
Simulation time	14255956 ps
CPU time	0.67 seconds
Started	Mar 12 12:48:17 PM PDT 24
Finished	Mar 12 12:48:18 PM PDT 24
Peak memory	199716 kb
Host	smart-ba249052-aa50-472a-af3a-50f78e890bae
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952177341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.952177341
Directory	/workspace/41.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/41.clkmgr_div_intersig_mubi.1660058015
Short name	T400
Test name
Test status
Simulation time	48176819 ps
CPU time	0.97 seconds
Started	Mar 12 12:48:25 PM PDT 24
Finished	Mar 12 12:48:27 PM PDT 24
Peak memory	200744 kb
Host	smart-3efd6bd5-d6b8-42ea-8429-287f59525bea
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660058015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.1660058015
Directory	/workspace/41.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_extclk.494390309
Short name	T26
Test name
Test status
Simulation time	23030057 ps
CPU time	0.85 seconds
Started	Mar 12 12:48:11 PM PDT 24
Finished	Mar 12 12:48:13 PM PDT 24
Peak memory	200804 kb
Host	smart-1339c91b-4e37-44f3-86db-bf25f6b38d8a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494390309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.494390309
Directory	/workspace/41.clkmgr_extclk/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency.1755027736
Short name	T258
Test name
Test status
Simulation time	1642865601 ps
CPU time	12.34 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:36 PM PDT 24
Peak memory	200848 kb
Host	smart-c4e1328c-b232-45d1-807e-a119059337eb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755027736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1755027736
Directory	/workspace/41.clkmgr_frequency/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency_timeout.1107044065
Short name	T738
Test name
Test status
Simulation time	1939684441 ps
CPU time	13.87 seconds
Started	Mar 12 12:48:09 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200880 kb
Host	smart-196348c8-a8f4-47cd-bd13-b4e01739e5f9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107044065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t imeout.1107044065
Directory	/workspace/41.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/41.clkmgr_idle_intersig_mubi.4023406126
Short name	T80
Test name
Test status
Simulation time	28052633 ps
CPU time	0.99 seconds
Started	Mar 12 12:48:18 PM PDT 24
Finished	Mar 12 12:48:19 PM PDT 24
Peak memory	200816 kb
Host	smart-f604ce0b-8e62-421d-8f07-823b84c60a7e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023406126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.4023406126
Directory	/workspace/41.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.1218658382
Short name	T699
Test name
Test status
Simulation time	20405685 ps
CPU time	0.8 seconds
Started	Mar 12 12:48:20 PM PDT 24
Finished	Mar 12 12:48:21 PM PDT 24
Peak memory	200728 kb
Host	smart-52756473-68f3-4c6b-8f4e-9c761f7e3807
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218658382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_clk_byp_req_intersig_mubi.1218658382
Directory	/workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.3652740111
Short name	T195
Test name
Test status
Simulation time	13012235 ps
CPU time	0.68 seconds
Started	Mar 12 12:48:21 PM PDT 24
Finished	Mar 12 12:48:22 PM PDT 24
Peak memory	200656 kb
Host	smart-2016f59c-aef1-40ae-acf7-7422ee58f020
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652740111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_ctrl_intersig_mubi.3652740111
Directory	/workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_peri.1000577046
Short name	T537
Test name
Test status
Simulation time	15726550 ps
CPU time	0.76 seconds
Started	Mar 12 12:48:25 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200836 kb
Host	smart-6e0bbdc3-85bd-45a1-8d3a-d14e58b2dc42
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000577046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.1000577046
Directory	/workspace/41.clkmgr_peri/latest

Test location	/workspace/coverage/default/41.clkmgr_regwen.39627457
Short name	T717
Test name
Test status
Simulation time	912507996 ps
CPU time	4.43 seconds
Started	Mar 12 12:48:19 PM PDT 24
Finished	Mar 12 12:48:23 PM PDT 24
Peak memory	200928 kb
Host	smart-26c14127-da3e-427b-9564-bafa2f058563
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39627457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.39627457
Directory	/workspace/41.clkmgr_regwen/latest

Test location	/workspace/coverage/default/41.clkmgr_smoke.416241046
Short name	T705
Test name
Test status
Simulation time	71991828 ps
CPU time	0.99 seconds
Started	Mar 12 12:48:07 PM PDT 24
Finished	Mar 12 12:48:10 PM PDT 24
Peak memory	200756 kb
Host	smart-069610bb-b5f0-40db-bf95-16c37319a528
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416241046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.416241046
Directory	/workspace/41.clkmgr_smoke/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all.2582006557
Short name	T519
Test name
Test status
Simulation time	8953114117 ps
CPU time	44.47 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:49:09 PM PDT 24
Peak memory	201208 kb
Host	smart-3106786e-0066-4bcc-88a0-72530eddd00e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582006557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.2582006557
Directory	/workspace/41.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.2115231699
Short name	T85
Test name
Test status
Simulation time	33957217205 ps
CPU time	463.41 seconds
Started	Mar 12 12:48:26 PM PDT 24
Finished	Mar 12 12:56:10 PM PDT 24
Peak memory	209456 kb
Host	smart-7797f9ca-fced-4920-b859-9c19f766d45a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2115231699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.2115231699
Directory	/workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.clkmgr_trans.2201052787
Short name	T352
Test name
Test status
Simulation time	179695109 ps
CPU time	1.26 seconds
Started	Mar 12 12:48:27 PM PDT 24
Finished	Mar 12 12:48:28 PM PDT 24
Peak memory	200692 kb
Host	smart-eb0008bb-7e00-4a5d-b6a0-9b546c82166c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201052787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.2201052787
Directory	/workspace/41.clkmgr_trans/latest

Test location	/workspace/coverage/default/42.clkmgr_alert_test.2944218528
Short name	T833
Test name
Test status
Simulation time	17845496 ps
CPU time	0.87 seconds
Started	Mar 12 12:48:17 PM PDT 24
Finished	Mar 12 12:48:18 PM PDT 24
Peak memory	200884 kb
Host	smart-53bd937c-4d00-4a5e-975f-9335778cdf90
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944218528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk mgr_alert_test.2944218528
Directory	/workspace/42.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.512748566
Short name	T375
Test name
Test status
Simulation time	17274760 ps
CPU time	0.74 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	200664 kb
Host	smart-a20e127a-da91-4464-90f4-73f02a350386
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512748566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.512748566
Directory	/workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_status.2720535829
Short name	T760
Test name
Test status
Simulation time	13161222 ps
CPU time	0.72 seconds
Started	Mar 12 12:48:19 PM PDT 24
Finished	Mar 12 12:48:20 PM PDT 24
Peak memory	199756 kb
Host	smart-9e52aa43-5ce9-4fcd-bdf2-cdd261f57349
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720535829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.2720535829
Directory	/workspace/42.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/42.clkmgr_div_intersig_mubi.1144481739
Short name	T202
Test name
Test status
Simulation time	210445215 ps
CPU time	1.4 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200740 kb
Host	smart-45fb76a7-8e89-45c0-bc2d-52ece2bce6c2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144481739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.1144481739
Directory	/workspace/42.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_extclk.1640037266
Short name	T324
Test name
Test status
Simulation time	32638983 ps
CPU time	0.92 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200736 kb
Host	smart-c0b169e8-0cb0-4a11-880f-7fca43fa369d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640037266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1640037266
Directory	/workspace/42.clkmgr_extclk/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency.657359278
Short name	T578
Test name
Test status
Simulation time	1880903825 ps
CPU time	13.97 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:38 PM PDT 24
Peak memory	201020 kb
Host	smart-aa26c4a0-4932-40c6-a155-d8ea8681639c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657359278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.657359278
Directory	/workspace/42.clkmgr_frequency/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency_timeout.1502523838
Short name	T666
Test name
Test status
Simulation time	622550717 ps
CPU time	3.65 seconds
Started	Mar 12 12:48:21 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200844 kb
Host	smart-845e7e51-6656-48f1-8725-ab979351597d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502523838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t imeout.1502523838
Directory	/workspace/42.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/42.clkmgr_idle_intersig_mubi.3902662507
Short name	T551
Test name
Test status
Simulation time	16524074 ps
CPU time	0.77 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200788 kb
Host	smart-553047c0-b4d7-4a9c-959b-2f406f9a48b9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902662507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.3902662507
Directory	/workspace/42.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.4083636908
Short name	T777
Test name
Test status
Simulation time	40535929 ps
CPU time	0.81 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200816 kb
Host	smart-b91e131d-63bc-482e-95b5-bba1aabbed9b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083636908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 42.clkmgr_lc_clk_byp_req_intersig_mubi.4083636908
Directory	/workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.1495647938
Short name	T836
Test name
Test status
Simulation time	46973884 ps
CPU time	0.97 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200784 kb
Host	smart-8e03d28b-21b8-4138-975b-dd1cddaa7e91
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495647938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 42.clkmgr_lc_ctrl_intersig_mubi.1495647938
Directory	/workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_peri.3444530370
Short name	T242
Test name
Test status
Simulation time	37422566 ps
CPU time	0.86 seconds
Started	Mar 12 12:48:15 PM PDT 24
Finished	Mar 12 12:48:16 PM PDT 24
Peak memory	200788 kb
Host	smart-567d10d4-8fdd-4a63-8890-776e7e8911ab
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444530370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.3444530370
Directory	/workspace/42.clkmgr_peri/latest

Test location	/workspace/coverage/default/42.clkmgr_regwen.1102718452
Short name	T616
Test name
Test status
Simulation time	577276518 ps
CPU time	2.86 seconds
Started	Mar 12 12:48:20 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200824 kb
Host	smart-5f952ff9-5b14-451b-8643-04f0913bd1cc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102718452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.1102718452
Directory	/workspace/42.clkmgr_regwen/latest

Test location	/workspace/coverage/default/42.clkmgr_smoke.1362856035
Short name	T8
Test name
Test status
Simulation time	17414498 ps
CPU time	0.81 seconds
Started	Mar 12 12:48:15 PM PDT 24
Finished	Mar 12 12:48:16 PM PDT 24
Peak memory	200804 kb
Host	smart-81c84507-5b9c-4f9e-b9f6-6540335222c9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362856035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.1362856035
Directory	/workspace/42.clkmgr_smoke/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all.409723075
Short name	T514
Test name
Test status
Simulation time	1269658805 ps
CPU time	8.25 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:30 PM PDT 24
Peak memory	201072 kb
Host	smart-34bd0bd2-95b6-4f75-999a-fda8902abacd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409723075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.409723075
Directory	/workspace/42.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.1016756415
Short name	T481
Test name
Test status
Simulation time	40580941842 ps
CPU time	537.22 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:57:23 PM PDT 24
Peak memory	217608 kb
Host	smart-999e324e-af70-4697-b312-0105fce61a4d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1016756415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.1016756415
Directory	/workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.clkmgr_trans.3271258965
Short name	T236
Test name
Test status
Simulation time	24327592 ps
CPU time	0.77 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	200696 kb
Host	smart-58fa0537-c180-4940-8496-fed69484235d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271258965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.3271258965
Directory	/workspace/42.clkmgr_trans/latest

Test location	/workspace/coverage/default/43.clkmgr_alert_test.3643890405
Short name	T622
Test name
Test status
Simulation time	79232976 ps
CPU time	0.95 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200888 kb
Host	smart-4c20bf82-4ce0-4ae9-a3c3-385ecb4f559d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643890405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk mgr_alert_test.3643890405
Directory	/workspace/43.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.4117824170
Short name	T172
Test name
Test status
Simulation time	34666322 ps
CPU time	0.88 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:23 PM PDT 24
Peak memory	200568 kb
Host	smart-ceb0a1cb-6ebe-4ace-bac2-727d497c5c71
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117824170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.4117824170
Directory	/workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_status.2961322502
Short name	T287
Test name
Test status
Simulation time	13059056 ps
CPU time	0.71 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	199764 kb
Host	smart-c61d2648-965b-4ea0-b1c9-400ea1d70588
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961322502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.2961322502
Directory	/workspace/43.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/43.clkmgr_div_intersig_mubi.2259196734
Short name	T329
Test name
Test status
Simulation time	204658583 ps
CPU time	1.42 seconds
Started	Mar 12 12:48:21 PM PDT 24
Finished	Mar 12 12:48:23 PM PDT 24
Peak memory	200692 kb
Host	smart-4c127cd1-ce4a-4dce-8771-2ba3fad9e33a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259196734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.2259196734
Directory	/workspace/43.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_extclk.1742786588
Short name	T227
Test name
Test status
Simulation time	19443983 ps
CPU time	0.81 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200728 kb
Host	smart-1a3073d6-dadd-46ee-8077-0b790b63e04a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742786588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.1742786588
Directory	/workspace/43.clkmgr_extclk/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency.2018748856
Short name	T330
Test name
Test status
Simulation time	620944121 ps
CPU time	2.98 seconds
Started	Mar 12 12:48:18 PM PDT 24
Finished	Mar 12 12:48:21 PM PDT 24
Peak memory	200844 kb
Host	smart-db4bc1e9-0c31-4d1d-82c0-050ea62b7b75
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018748856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.2018748856
Directory	/workspace/43.clkmgr_frequency/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency_timeout.2631562290
Short name	T638
Test name
Test status
Simulation time	616307865 ps
CPU time	4.72 seconds
Started	Mar 12 12:48:26 PM PDT 24
Finished	Mar 12 12:48:32 PM PDT 24
Peak memory	200876 kb
Host	smart-cc797448-6138-4fe0-96fb-f7f8c0fb83ac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631562290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t imeout.2631562290
Directory	/workspace/43.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/43.clkmgr_idle_intersig_mubi.2298744271
Short name	T299
Test name
Test status
Simulation time	43321994 ps
CPU time	0.85 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200836 kb
Host	smart-8b06a02b-3b09-4adb-b197-15796bb223b3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298744271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.2298744271
Directory	/workspace/43.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.1497448981
Short name	T176
Test name
Test status
Simulation time	47538135 ps
CPU time	0.81 seconds
Started	Mar 12 12:48:16 PM PDT 24
Finished	Mar 12 12:48:17 PM PDT 24
Peak memory	200820 kb
Host	smart-b55d4b43-7c49-412a-9a8a-7de838de887f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497448981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.clkmgr_lc_clk_byp_req_intersig_mubi.1497448981
Directory	/workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.3791004771
Short name	T688
Test name
Test status
Simulation time	63909114 ps
CPU time	0.96 seconds
Started	Mar 12 12:48:18 PM PDT 24
Finished	Mar 12 12:48:19 PM PDT 24
Peak memory	200808 kb
Host	smart-9c317f92-9e9f-49c7-af89-ae2277f81fd5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791004771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.clkmgr_lc_ctrl_intersig_mubi.3791004771
Directory	/workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_peri.3838118934
Short name	T437
Test name
Test status
Simulation time	93966682 ps
CPU time	0.94 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200612 kb
Host	smart-05c720d1-1011-4592-900b-3dc2a14ba1de
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838118934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.3838118934
Directory	/workspace/43.clkmgr_peri/latest

Test location	/workspace/coverage/default/43.clkmgr_regwen.2237841086
Short name	T620
Test name
Test status
Simulation time	1198263121 ps
CPU time	4.46 seconds
Started	Mar 12 12:48:21 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	200980 kb
Host	smart-fa1f3fbe-c92a-41ca-8edf-ca53cd80162c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237841086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.2237841086
Directory	/workspace/43.clkmgr_regwen/latest

Test location	/workspace/coverage/default/43.clkmgr_smoke.3380993088
Short name	T528
Test name
Test status
Simulation time	45372507 ps
CPU time	0.86 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200756 kb
Host	smart-8b94a0ce-f3aa-4df0-9143-7ee4729b1ccb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380993088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.3380993088
Directory	/workspace/43.clkmgr_smoke/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all.2768901956
Short name	T277
Test name
Test status
Simulation time	5425332676 ps
CPU time	22.81 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:46 PM PDT 24
Peak memory	201232 kb
Host	smart-8ffb5b00-f2d2-484c-8ccf-86f18936cf13
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768901956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.2768901956
Directory	/workspace/43.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.1636756552
Short name	T580
Test name
Test status
Simulation time	43872512404 ps
CPU time	406.57 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:55:11 PM PDT 24
Peak memory	209528 kb
Host	smart-e5d1b509-0349-47c8-bf93-d92ebcb2a385
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1636756552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.1636756552
Directory	/workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.clkmgr_trans.1444915748
Short name	T680
Test name
Test status
Simulation time	15256004 ps
CPU time	0.73 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	200772 kb
Host	smart-51d5d0a7-1577-4017-aa27-1f17de824738
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444915748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.1444915748
Directory	/workspace/43.clkmgr_trans/latest

Test location	/workspace/coverage/default/44.clkmgr_alert_test.3400996776
Short name	T44
Test name
Test status
Simulation time	84240333 ps
CPU time	0.92 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	200884 kb
Host	smart-d6031456-0452-4d88-85b3-8221afeca6ca
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400996776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk mgr_alert_test.3400996776
Directory	/workspace/44.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1424257767
Short name	T517
Test name
Test status
Simulation time	20595951 ps
CPU time	0.8 seconds
Started	Mar 12 12:48:26 PM PDT 24
Finished	Mar 12 12:48:27 PM PDT 24
Peak memory	200800 kb
Host	smart-d09d1562-f2ce-4d09-a6ac-4806a5e263a0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424257767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.1424257767
Directory	/workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_status.3909339580
Short name	T243
Test name
Test status
Simulation time	60819442 ps
CPU time	0.84 seconds
Started	Mar 12 12:48:18 PM PDT 24
Finished	Mar 12 12:48:19 PM PDT 24
Peak memory	199760 kb
Host	smart-689160e0-3a33-4009-878f-4f829693b6fa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909339580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.3909339580
Directory	/workspace/44.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/44.clkmgr_div_intersig_mubi.838213965
Short name	T392
Test name
Test status
Simulation time	29724596 ps
CPU time	0.73 seconds
Started	Mar 12 12:48:20 PM PDT 24
Finished	Mar 12 12:48:21 PM PDT 24
Peak memory	200808 kb
Host	smart-564d9d89-ff9c-49c6-ae75-fd82f24fb669
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838213965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.clkmgr_div_intersig_mubi.838213965
Directory	/workspace/44.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_extclk.145278262
Short name	T368
Test name
Test status
Simulation time	97574827 ps
CPU time	1.13 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	200716 kb
Host	smart-e36335e6-36c2-4c75-a0f7-6f4920ee6754
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145278262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.145278262
Directory	/workspace/44.clkmgr_extclk/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency.2102204223
Short name	T603
Test name
Test status
Simulation time	2273719167 ps
CPU time	10.17 seconds
Started	Mar 12 12:48:32 PM PDT 24
Finished	Mar 12 12:48:43 PM PDT 24
Peak memory	200956 kb
Host	smart-db773651-dbba-4d99-a1ea-d640de66d963
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102204223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2102204223
Directory	/workspace/44.clkmgr_frequency/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency_timeout.1193528101
Short name	T420
Test name
Test status
Simulation time	2536048993 ps
CPU time	9.74 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:34 PM PDT 24
Peak memory	201160 kb
Host	smart-668e824c-e46b-465e-9d82-d1f3876b2370
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193528101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t imeout.1193528101
Directory	/workspace/44.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/44.clkmgr_idle_intersig_mubi.55051548
Short name	T315
Test name
Test status
Simulation time	60793372 ps
CPU time	0.99 seconds
Started	Mar 12 12:48:30 PM PDT 24
Finished	Mar 12 12:48:31 PM PDT 24
Peak memory	200816 kb
Host	smart-ec9efe0f-b211-40d3-8034-7bd193994577
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55051548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44 .clkmgr_idle_intersig_mubi.55051548
Directory	/workspace/44.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.2356175139
Short name	T781
Test name
Test status
Simulation time	21504359 ps
CPU time	0.83 seconds
Started	Mar 12 12:48:26 PM PDT 24
Finished	Mar 12 12:48:27 PM PDT 24
Peak memory	200640 kb
Host	smart-be1cb976-e2d2-4114-aafa-ea894caff0e4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356175139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.clkmgr_lc_clk_byp_req_intersig_mubi.2356175139
Directory	/workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.3425743954
Short name	T725
Test name
Test status
Simulation time	42416197 ps
CPU time	0.93 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200764 kb
Host	smart-78285c31-3e88-49c7-8076-e735f41991a9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425743954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.clkmgr_lc_ctrl_intersig_mubi.3425743954
Directory	/workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_peri.2465247700
Short name	T646
Test name
Test status
Simulation time	13663860 ps
CPU time	0.73 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	200780 kb
Host	smart-266c64a2-32e0-4bb1-a3ec-3ebd7710ed98
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465247700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.2465247700
Directory	/workspace/44.clkmgr_peri/latest

Test location	/workspace/coverage/default/44.clkmgr_regwen.443416704
Short name	T391
Test name
Test status
Simulation time	623764834 ps
CPU time	3.79 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:28 PM PDT 24
Peak memory	201012 kb
Host	smart-070edf20-9c3d-47bd-bf58-b69247c86262
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443416704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.443416704
Directory	/workspace/44.clkmgr_regwen/latest

Test location	/workspace/coverage/default/44.clkmgr_smoke.2996465827
Short name	T652
Test name
Test status
Simulation time	14951212 ps
CPU time	0.77 seconds
Started	Mar 12 12:48:20 PM PDT 24
Finished	Mar 12 12:48:21 PM PDT 24
Peak memory	200824 kb
Host	smart-b04d461f-1c14-47c3-b713-edb007b8bd5c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996465827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.2996465827
Directory	/workspace/44.clkmgr_smoke/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all.1323685256
Short name	T711
Test name
Test status
Simulation time	2189936165 ps
CPU time	8.85 seconds
Started	Mar 12 12:48:26 PM PDT 24
Finished	Mar 12 12:48:36 PM PDT 24
Peak memory	201100 kb
Host	smart-526d35c2-53d4-490d-9681-e97fb786388f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323685256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.1323685256
Directory	/workspace/44.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.1778027254
Short name	T156
Test name
Test status
Simulation time	160867136722 ps
CPU time	1069.46 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 01:06:12 PM PDT 24
Peak memory	215532 kb
Host	smart-d011c7a2-dd72-476a-94ec-7d6c5c99f792
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1778027254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.1778027254
Directory	/workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.clkmgr_trans.386638016
Short name	T449
Test name
Test status
Simulation time	26370987 ps
CPU time	0.89 seconds
Started	Mar 12 12:48:21 PM PDT 24
Finished	Mar 12 12:48:22 PM PDT 24
Peak memory	200776 kb
Host	smart-39e97340-61e4-4a01-a7b1-444d0bf18e01
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386638016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.386638016
Directory	/workspace/44.clkmgr_trans/latest

Test location	/workspace/coverage/default/45.clkmgr_alert_test.3733890750
Short name	T656
Test name
Test status
Simulation time	15938327 ps
CPU time	0.76 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200904 kb
Host	smart-f561d72a-5b5f-4d75-a53d-3ed24e77a520
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733890750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk mgr_alert_test.3733890750
Directory	/workspace/45.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.4083985622
Short name	T69
Test name
Test status
Simulation time	27773640 ps
CPU time	0.91 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:23 PM PDT 24
Peak memory	200808 kb
Host	smart-bdcd776c-4c18-4d2e-ac6c-8f935eaf2e4c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083985622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.4083985622
Directory	/workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_status.1512511562
Short name	T624
Test name
Test status
Simulation time	14080246 ps
CPU time	0.7 seconds
Started	Mar 12 12:48:28 PM PDT 24
Finished	Mar 12 12:48:29 PM PDT 24
Peak memory	199636 kb
Host	smart-6a9bed8b-868c-491c-979d-9f8d6d3d1679
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512511562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1512511562
Directory	/workspace/45.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/45.clkmgr_div_intersig_mubi.3001404750
Short name	T130
Test name
Test status
Simulation time	75551827 ps
CPU time	0.93 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	200780 kb
Host	smart-67b3c9df-3721-4454-960e-d704ceb7006c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001404750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.3001404750
Directory	/workspace/45.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_extclk.4005806953
Short name	T188
Test name
Test status
Simulation time	17550161 ps
CPU time	0.77 seconds
Started	Mar 12 12:48:18 PM PDT 24
Finished	Mar 12 12:48:19 PM PDT 24
Peak memory	200700 kb
Host	smart-a034e3a1-39cb-443c-ae65-9c5b8bd0b7eb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005806953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.4005806953
Directory	/workspace/45.clkmgr_extclk/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency.342227471
Short name	T104
Test name
Test status
Simulation time	1561265262 ps
CPU time	7.76 seconds
Started	Mar 12 12:48:21 PM PDT 24
Finished	Mar 12 12:48:30 PM PDT 24
Peak memory	200812 kb
Host	smart-66d5fbfd-0d6d-4a7b-8c0c-f80e346300d8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342227471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.342227471
Directory	/workspace/45.clkmgr_frequency/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency_timeout.329654867
Short name	T128
Test name
Test status
Simulation time	503768859 ps
CPU time	3.08 seconds
Started	Mar 12 12:48:20 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200872 kb
Host	smart-9aaca8ef-d4ea-4aac-b122-acbb223de2d6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329654867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_ti meout.329654867
Directory	/workspace/45.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/45.clkmgr_idle_intersig_mubi.486182334
Short name	T167
Test name
Test status
Simulation time	79779241 ps
CPU time	1.08 seconds
Started	Mar 12 12:48:25 PM PDT 24
Finished	Mar 12 12:48:27 PM PDT 24
Peak memory	200812 kb
Host	smart-1be984be-7390-4372-a8db-4dcc4686b9a9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486182334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.clkmgr_idle_intersig_mubi.486182334
Directory	/workspace/45.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.404752096
Short name	T275
Test name
Test status
Simulation time	19537990 ps
CPU time	0.82 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:23 PM PDT 24
Peak memory	200640 kb
Host	smart-626622c5-fd50-4078-8fe7-d285e2e932f8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404752096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.clkmgr_lc_clk_byp_req_intersig_mubi.404752096
Directory	/workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.3517364337
Short name	T733
Test name
Test status
Simulation time	18534146 ps
CPU time	0.77 seconds
Started	Mar 12 12:48:26 PM PDT 24
Finished	Mar 12 12:48:27 PM PDT 24
Peak memory	200808 kb
Host	smart-6953e864-5ced-44a3-8e96-81e24a5d6940
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517364337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.clkmgr_lc_ctrl_intersig_mubi.3517364337
Directory	/workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_peri.748467496
Short name	T595
Test name
Test status
Simulation time	34018567 ps
CPU time	0.75 seconds
Started	Mar 12 12:48:27 PM PDT 24
Finished	Mar 12 12:48:28 PM PDT 24
Peak memory	200548 kb
Host	smart-585459ff-abd6-4611-a5a0-682306bcd1f0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748467496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.748467496
Directory	/workspace/45.clkmgr_peri/latest

Test location	/workspace/coverage/default/45.clkmgr_regwen.696069253
Short name	T495
Test name
Test status
Simulation time	290864557 ps
CPU time	1.91 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200728 kb
Host	smart-e39dc674-4b0f-4606-9614-400634cc426b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696069253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.696069253
Directory	/workspace/45.clkmgr_regwen/latest

Test location	/workspace/coverage/default/45.clkmgr_smoke.3254842515
Short name	T764
Test name
Test status
Simulation time	23654212 ps
CPU time	0.84 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200820 kb
Host	smart-2f942cea-2de8-4b10-b947-97e624b6a2c6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254842515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.3254842515
Directory	/workspace/45.clkmgr_smoke/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all.1897052299
Short name	T279
Test name
Test status
Simulation time	2907859110 ps
CPU time	16.99 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:39 PM PDT 24
Peak memory	201096 kb
Host	smart-696f3a09-bc03-4125-9d9f-5fc83159ee6e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897052299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.1897052299
Directory	/workspace/45.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.1267488294
Short name	T451
Test name
Test status
Simulation time	12112897728 ps
CPU time	182.27 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:51:27 PM PDT 24
Peak memory	209504 kb
Host	smart-745ad474-c0cb-47bd-bdf9-3266f4feadc9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1267488294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.1267488294
Directory	/workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.clkmgr_trans.977858406
Short name	T838
Test name
Test status
Simulation time	41839723 ps
CPU time	1.09 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200780 kb
Host	smart-83079449-7abc-47fa-afa6-c31ffd43594e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977858406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.977858406
Directory	/workspace/45.clkmgr_trans/latest

Test location	/workspace/coverage/default/46.clkmgr_alert_test.713705516
Short name	T194
Test name
Test status
Simulation time	46642248 ps
CPU time	0.78 seconds
Started	Mar 12 12:48:28 PM PDT 24
Finished	Mar 12 12:48:29 PM PDT 24
Peak memory	200848 kb
Host	smart-f755cc5a-8767-4cd8-9888-eb980dfc255f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713705516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkm gr_alert_test.713705516
Directory	/workspace/46.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1797283581
Short name	T84
Test name
Test status
Simulation time	29972933 ps
CPU time	0.83 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:24 PM PDT 24
Peak memory	200736 kb
Host	smart-c642dae7-b991-46d8-8261-88326de1ba8d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797283581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.1797283581
Directory	/workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_status.3149963972
Short name	T144
Test name
Test status
Simulation time	36709844 ps
CPU time	0.76 seconds
Started	Mar 12 12:48:25 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200764 kb
Host	smart-a26939b4-5534-436f-84f3-56636673f4c2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149963972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.3149963972
Directory	/workspace/46.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/46.clkmgr_div_intersig_mubi.1730888731
Short name	T482
Test name
Test status
Simulation time	17949972 ps
CPU time	0.79 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:23 PM PDT 24
Peak memory	200808 kb
Host	smart-51df102a-dc72-44e2-885b-6e4e8900f3cc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730888731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.1730888731
Directory	/workspace/46.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_extclk.3590977507
Short name	T524
Test name
Test status
Simulation time	20163009 ps
CPU time	0.82 seconds
Started	Mar 12 12:48:21 PM PDT 24
Finished	Mar 12 12:48:22 PM PDT 24
Peak memory	200820 kb
Host	smart-a1f0b3da-3e62-432b-aab3-60363722cd44
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590977507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.3590977507
Directory	/workspace/46.clkmgr_extclk/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency.37263645
Short name	T837
Test name
Test status
Simulation time	1320312669 ps
CPU time	4.72 seconds
Started	Mar 12 12:48:21 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200796 kb
Host	smart-1b297e85-0f4a-44a9-bc8c-367562f8c96e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37263645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.37263645
Directory	/workspace/46.clkmgr_frequency/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency_timeout.752368971
Short name	T748
Test name
Test status
Simulation time	2182551058 ps
CPU time	10.82 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:36 PM PDT 24
Peak memory	201144 kb
Host	smart-3034c67a-1f6e-497c-82bb-c5564b9d3dcf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752368971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_ti meout.752368971
Directory	/workspace/46.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/46.clkmgr_idle_intersig_mubi.324715129
Short name	T177
Test name
Test status
Simulation time	54149306 ps
CPU time	0.84 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200824 kb
Host	smart-07eb114d-7447-42d1-b7d0-3f94993a2b5a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324715129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.clkmgr_idle_intersig_mubi.324715129
Directory	/workspace/46.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.1836893117
Short name	T745
Test name
Test status
Simulation time	23442396 ps
CPU time	0.82 seconds
Started	Mar 12 12:48:25 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200820 kb
Host	smart-922707b8-062e-4c50-911a-eeafbf74554e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836893117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_clk_byp_req_intersig_mubi.1836893117
Directory	/workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.720877116
Short name	T594
Test name
Test status
Simulation time	25235652 ps
CPU time	0.93 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200776 kb
Host	smart-cff8eb50-62b6-4ba2-8ffa-16a34f030444
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720877116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.clkmgr_lc_ctrl_intersig_mubi.720877116
Directory	/workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_peri.4005121385
Short name	T431
Test name
Test status
Simulation time	32629279 ps
CPU time	0.77 seconds
Started	Mar 12 12:48:25 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200784 kb
Host	smart-5481bd32-8ce9-42c5-9a70-87a8a6b80d2e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005121385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.4005121385
Directory	/workspace/46.clkmgr_peri/latest

Test location	/workspace/coverage/default/46.clkmgr_regwen.2052748646
Short name	T545
Test name
Test status
Simulation time	88092662 ps
CPU time	1.04 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	200808 kb
Host	smart-9a6f6644-622b-4022-9a4d-3e2d6aef6fbd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052748646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.2052748646
Directory	/workspace/46.clkmgr_regwen/latest

Test location	/workspace/coverage/default/46.clkmgr_smoke.3235511350
Short name	T708
Test name
Test status
Simulation time	26755554 ps
CPU time	0.8 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:23 PM PDT 24
Peak memory	200784 kb
Host	smart-65f25135-7635-4a26-a938-cc7e7bc3a6ae
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235511350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.3235511350
Directory	/workspace/46.clkmgr_smoke/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all.706522541
Short name	T383
Test name
Test status
Simulation time	12937556298 ps
CPU time	50.1 seconds
Started	Mar 12 12:48:30 PM PDT 24
Finished	Mar 12 12:49:20 PM PDT 24
Peak memory	201168 kb
Host	smart-65d58da6-b10a-42a7-9032-0c4b6d66ef07
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706522541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.706522541
Directory	/workspace/46.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.2598950149
Short name	T14
Test name
Test status
Simulation time	40130631197 ps
CPU time	230.61 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:52:13 PM PDT 24
Peak memory	216344 kb
Host	smart-4912a722-61b4-49fd-aa86-9fffd174dff3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2598950149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.2598950149
Directory	/workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.clkmgr_trans.1796109128
Short name	T349
Test name
Test status
Simulation time	19378011 ps
CPU time	0.79 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200804 kb
Host	smart-bf01b0dc-4100-4a62-864f-6aefa6efe414
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796109128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.1796109128
Directory	/workspace/46.clkmgr_trans/latest

Test location	/workspace/coverage/default/47.clkmgr_alert_test.552430415
Short name	T607
Test name
Test status
Simulation time	16535763 ps
CPU time	0.74 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200860 kb
Host	smart-518d470f-dd70-4144-8c58-7ca881a57080
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552430415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkm gr_alert_test.552430415
Directory	/workspace/47.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.3949527382
Short name	T439
Test name
Test status
Simulation time	62103322 ps
CPU time	1.02 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200848 kb
Host	smart-31f75af1-8e46-4941-8d5d-7d297a97cc47
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949527382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.3949527382
Directory	/workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_status.1874734965
Short name	T423
Test name
Test status
Simulation time	13803827 ps
CPU time	0.7 seconds
Started	Mar 12 12:48:23 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	199792 kb
Host	smart-b3f5cb18-b908-4885-aced-ca3a0d88bfcd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874734965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.1874734965
Directory	/workspace/47.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/47.clkmgr_div_intersig_mubi.1155598799
Short name	T81
Test name
Test status
Simulation time	21644802 ps
CPU time	0.84 seconds
Started	Mar 12 12:48:29 PM PDT 24
Finished	Mar 12 12:48:30 PM PDT 24
Peak memory	200812 kb
Host	smart-712a6638-201d-46a3-8717-80efa7eeb739
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155598799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.1155598799
Directory	/workspace/47.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_extclk.4009754935
Short name	T582
Test name
Test status
Simulation time	26966208 ps
CPU time	0.89 seconds
Started	Mar 12 12:48:20 PM PDT 24
Finished	Mar 12 12:48:22 PM PDT 24
Peak memory	200720 kb
Host	smart-35b5c91d-5a76-427e-8134-04469dc0cf27
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009754935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.4009754935
Directory	/workspace/47.clkmgr_extclk/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency.2237529941
Short name	T366
Test name
Test status
Simulation time	1495352083 ps
CPU time	5.4 seconds
Started	Mar 12 12:48:28 PM PDT 24
Finished	Mar 12 12:48:34 PM PDT 24
Peak memory	200788 kb
Host	smart-3933795a-c4e2-4b05-8fc5-51d22635c29c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237529941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.2237529941
Directory	/workspace/47.clkmgr_frequency/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency_timeout.3350544212
Short name	T645
Test name
Test status
Simulation time	1944792026 ps
CPU time	10.45 seconds
Started	Mar 12 12:48:25 PM PDT 24
Finished	Mar 12 12:48:36 PM PDT 24
Peak memory	200872 kb
Host	smart-9d19f874-df48-4874-a705-899b991280de
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350544212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t imeout.3350544212
Directory	/workspace/47.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3247040699
Short name	T166
Test name
Test status
Simulation time	27538327 ps
CPU time	0.94 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:23 PM PDT 24
Peak memory	200820 kb
Host	smart-0947d7b0-e502-4897-b9c3-3c5fdfb9e71c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247040699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.3247040699
Directory	/workspace/47.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.1242925271
Short name	T791
Test name
Test status
Simulation time	48828793 ps
CPU time	0.82 seconds
Started	Mar 12 12:48:25 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200760 kb
Host	smart-2c84ddc5-1ef1-4d66-9d04-a46619d4b619
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242925271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_clk_byp_req_intersig_mubi.1242925271
Directory	/workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.157370524
Short name	T544
Test name
Test status
Simulation time	29201971 ps
CPU time	0.8 seconds
Started	Mar 12 12:48:27 PM PDT 24
Finished	Mar 12 12:48:28 PM PDT 24
Peak memory	200848 kb
Host	smart-7491b171-62cc-4927-8db0-ae2176a82608
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157370524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.clkmgr_lc_ctrl_intersig_mubi.157370524
Directory	/workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_peri.4090625519
Short name	T766
Test name
Test status
Simulation time	18855817 ps
CPU time	0.84 seconds
Started	Mar 12 12:48:27 PM PDT 24
Finished	Mar 12 12:48:28 PM PDT 24
Peak memory	200636 kb
Host	smart-cb36e5d4-645e-4f07-9e3a-c452cd1e1401
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090625519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.4090625519
Directory	/workspace/47.clkmgr_peri/latest

Test location	/workspace/coverage/default/47.clkmgr_regwen.2154793105
Short name	T709
Test name
Test status
Simulation time	329298149 ps
CPU time	1.63 seconds
Started	Mar 12 12:48:22 PM PDT 24
Finished	Mar 12 12:48:25 PM PDT 24
Peak memory	200792 kb
Host	smart-15aa3e24-4c22-4b51-a618-e9d289b177a3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154793105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.2154793105
Directory	/workspace/47.clkmgr_regwen/latest

Test location	/workspace/coverage/default/47.clkmgr_smoke.1332659072
Short name	T472
Test name
Test status
Simulation time	20489518 ps
CPU time	0.87 seconds
Started	Mar 12 12:48:28 PM PDT 24
Finished	Mar 12 12:48:29 PM PDT 24
Peak memory	200776 kb
Host	smart-15c4a04f-c217-456f-8343-5377da597946
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332659072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.1332659072
Directory	/workspace/47.clkmgr_smoke/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all.349094791
Short name	T486
Test name
Test status
Simulation time	496058975 ps
CPU time	3.51 seconds
Started	Mar 12 12:48:33 PM PDT 24
Finished	Mar 12 12:48:37 PM PDT 24
Peak memory	201120 kb
Host	smart-307fbab9-c74c-4cdd-9e65-a10874d7165c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349094791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.349094791
Directory	/workspace/47.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.3591075966
Short name	T750
Test name
Test status
Simulation time	70406592050 ps
CPU time	679.59 seconds
Started	Mar 12 12:48:21 PM PDT 24
Finished	Mar 12 12:59:41 PM PDT 24
Peak memory	217712 kb
Host	smart-7f4122e4-7b63-4981-b4b7-05623a85b0f2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3591075966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.3591075966
Directory	/workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.clkmgr_trans.234358753
Short name	T179
Test name
Test status
Simulation time	24207319 ps
CPU time	0.85 seconds
Started	Mar 12 12:48:24 PM PDT 24
Finished	Mar 12 12:48:26 PM PDT 24
Peak memory	200796 kb
Host	smart-d997e476-0e2c-4bde-83bc-0340207599a9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234358753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.234358753
Directory	/workspace/47.clkmgr_trans/latest

Test location	/workspace/coverage/default/48.clkmgr_alert_test.1457796407
Short name	T280
Test name
Test status
Simulation time	40503436 ps
CPU time	0.82 seconds
Started	Mar 12 12:48:27 PM PDT 24
Finished	Mar 12 12:48:28 PM PDT 24
Peak memory	200876 kb
Host	smart-abc55371-ae93-4c2a-8504-6aace1463a16
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457796407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk mgr_alert_test.1457796407
Directory	/workspace/48.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.1896636602
Short name	T312
Test name
Test status
Simulation time	147722134 ps
CPU time	1.13 seconds
Started	Mar 12 12:48:29 PM PDT 24
Finished	Mar 12 12:48:30 PM PDT 24
Peak memory	200812 kb
Host	smart-7f76b932-bebf-4985-8f94-48bfb0f28d1b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896636602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.1896636602
Directory	/workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_status.1292071414
Short name	T397
Test name
Test status
Simulation time	35656520 ps
CPU time	0.73 seconds
Started	Mar 12 12:48:52 PM PDT 24
Finished	Mar 12 12:48:53 PM PDT 24
Peak memory	199736 kb
Host	smart-98444cf4-8348-4194-a553-0dae248b9874
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292071414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.1292071414
Directory	/workspace/48.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/48.clkmgr_div_intersig_mubi.899838730
Short name	T807
Test name
Test status
Simulation time	101541034 ps
CPU time	1.07 seconds
Started	Mar 12 12:48:33 PM PDT 24
Finished	Mar 12 12:48:34 PM PDT 24
Peak memory	200752 kb
Host	smart-e5a4b381-dae9-43b0-af08-7785f192a9a9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899838730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.clkmgr_div_intersig_mubi.899838730
Directory	/workspace/48.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_extclk.492981320
Short name	T516
Test name
Test status
Simulation time	53425598 ps
CPU time	0.86 seconds
Started	Mar 12 12:48:28 PM PDT 24
Finished	Mar 12 12:48:29 PM PDT 24
Peak memory	200776 kb
Host	smart-3eacaa76-28df-49d6-a2fc-c45fd696bc6d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492981320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.492981320
Directory	/workspace/48.clkmgr_extclk/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency.3086953162
Short name	T719
Test name
Test status
Simulation time	2482678496 ps
CPU time	18.51 seconds
Started	Mar 12 12:48:29 PM PDT 24
Finished	Mar 12 12:48:48 PM PDT 24
Peak memory	201084 kb
Host	smart-db8286c2-8ccd-4846-885f-90458ae06c95
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086953162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.3086953162
Directory	/workspace/48.clkmgr_frequency/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency_timeout.1983138134
Short name	T445
Test name
Test status
Simulation time	2183897305 ps
CPU time	10.89 seconds
Started	Mar 12 12:48:28 PM PDT 24
Finished	Mar 12 12:48:39 PM PDT 24
Peak memory	201112 kb
Host	smart-2c47ef8f-4d41-47dd-952c-b56b714d4699
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983138134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t imeout.1983138134
Directory	/workspace/48.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/48.clkmgr_idle_intersig_mubi.1333124359
Short name	T198
Test name
Test status
Simulation time	33302347 ps
CPU time	0.96 seconds
Started	Mar 12 12:48:31 PM PDT 24
Finished	Mar 12 12:48:32 PM PDT 24
Peak memory	200812 kb
Host	smart-78b64c56-150f-4d6a-9c3a-21fad792db60
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333124359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.1333124359
Directory	/workspace/48.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.3191422153
Short name	T221
Test name
Test status
Simulation time	49035667 ps
CPU time	0.85 seconds
Started	Mar 12 12:48:33 PM PDT 24
Finished	Mar 12 12:48:34 PM PDT 24
Peak memory	200824 kb
Host	smart-fdb8ae3d-dc21-4943-ac97-f53dfe9c7274
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191422153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_clk_byp_req_intersig_mubi.3191422153
Directory	/workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.502098830
Short name	T238
Test name
Test status
Simulation time	42907486 ps
CPU time	0.94 seconds
Started	Mar 12 12:48:34 PM PDT 24
Finished	Mar 12 12:48:35 PM PDT 24
Peak memory	200736 kb
Host	smart-be717c29-fbcf-49cb-b653-6ef19d708bbf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502098830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.clkmgr_lc_ctrl_intersig_mubi.502098830
Directory	/workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_peri.3963132738
Short name	T763
Test name
Test status
Simulation time	15407662 ps
CPU time	0.73 seconds
Started	Mar 12 12:48:31 PM PDT 24
Finished	Mar 12 12:48:33 PM PDT 24
Peak memory	200660 kb
Host	smart-820066e1-5c13-4a06-ac4f-9c6d7d3a1d61
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963132738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.3963132738
Directory	/workspace/48.clkmgr_peri/latest

Test location	/workspace/coverage/default/48.clkmgr_regwen.1180737484
Short name	T824
Test name
Test status
Simulation time	365337393 ps
CPU time	2.51 seconds
Started	Mar 12 12:48:31 PM PDT 24
Finished	Mar 12 12:48:33 PM PDT 24
Peak memory	200760 kb
Host	smart-a4a9117a-475c-415b-b6da-e96b378c7502
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180737484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.1180737484
Directory	/workspace/48.clkmgr_regwen/latest

Test location	/workspace/coverage/default/48.clkmgr_smoke.2398507998
Short name	T240
Test name
Test status
Simulation time	29976692 ps
CPU time	0.85 seconds
Started	Mar 12 12:48:33 PM PDT 24
Finished	Mar 12 12:48:34 PM PDT 24
Peak memory	200816 kb
Host	smart-db464c0c-4ab7-4aaf-8d68-d287ba7db67c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398507998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2398507998
Directory	/workspace/48.clkmgr_smoke/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all.3424242313
Short name	T488
Test name
Test status
Simulation time	13569426549 ps
CPU time	47.86 seconds
Started	Mar 12 12:48:31 PM PDT 24
Finished	Mar 12 12:49:19 PM PDT 24
Peak memory	201144 kb
Host	smart-f8e5b0c4-0af1-48d9-a797-d7a71a461070
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424242313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.3424242313
Directory	/workspace/48.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.4186588473
Short name	T234
Test name
Test status
Simulation time	176501755389 ps
CPU time	954.33 seconds
Started	Mar 12 12:48:34 PM PDT 24
Finished	Mar 12 01:04:28 PM PDT 24
Peak memory	209428 kb
Host	smart-cd8192c7-98cb-42d8-919b-da7e8ea47863
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4186588473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.4186588473
Directory	/workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.clkmgr_trans.2000797558
Short name	T362
Test name
Test status
Simulation time	59079207 ps
CPU time	0.84 seconds
Started	Mar 12 12:48:29 PM PDT 24
Finished	Mar 12 12:48:30 PM PDT 24
Peak memory	200808 kb
Host	smart-b4a893fe-5bc2-4153-812b-73e653c00f0e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000797558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.2000797558
Directory	/workspace/48.clkmgr_trans/latest

Test location	/workspace/coverage/default/49.clkmgr_alert_test.4268275019
Short name	T707
Test name
Test status
Simulation time	14920500 ps
CPU time	0.73 seconds
Started	Mar 12 12:48:27 PM PDT 24
Finished	Mar 12 12:48:28 PM PDT 24
Peak memory	200668 kb
Host	smart-b3f1bdec-b353-421d-a7aa-96619304c615
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268275019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk mgr_alert_test.4268275019
Directory	/workspace/49.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.1233125677
Short name	T191
Test name
Test status
Simulation time	18927893 ps
CPU time	0.75 seconds
Started	Mar 12 12:48:29 PM PDT 24
Finished	Mar 12 12:48:30 PM PDT 24
Peak memory	200724 kb
Host	smart-fcbc23e9-1790-4de6-a903-61b67c954de3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233125677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.1233125677
Directory	/workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_status.2054867720
Short name	T35
Test name
Test status
Simulation time	12967330 ps
CPU time	0.67 seconds
Started	Mar 12 12:48:31 PM PDT 24
Finished	Mar 12 12:48:33 PM PDT 24
Peak memory	199760 kb
Host	smart-057b24d0-7c99-4b47-9614-a0506d143730
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054867720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.2054867720
Directory	/workspace/49.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/49.clkmgr_div_intersig_mubi.4193112965
Short name	T367
Test name
Test status
Simulation time	45497042 ps
CPU time	0.96 seconds
Started	Mar 12 12:48:29 PM PDT 24
Finished	Mar 12 12:48:30 PM PDT 24
Peak memory	200724 kb
Host	smart-b90038c3-ed4d-451f-9357-3c02dbc14a81
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193112965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.4193112965
Directory	/workspace/49.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_extclk.3015806425
Short name	T565
Test name
Test status
Simulation time	100066252 ps
CPU time	0.97 seconds
Started	Mar 12 12:48:34 PM PDT 24
Finished	Mar 12 12:48:35 PM PDT 24
Peak memory	200724 kb
Host	smart-226f6343-8c89-4542-91e3-7fa517acc00b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015806425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.3015806425
Directory	/workspace/49.clkmgr_extclk/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency.684582740
Short name	T298
Test name
Test status
Simulation time	796341113 ps
CPU time	6.55 seconds
Started	Mar 12 12:48:29 PM PDT 24
Finished	Mar 12 12:48:36 PM PDT 24
Peak memory	200740 kb
Host	smart-9d963575-6ca1-4d96-aeb4-7bca3d419b88
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684582740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.684582740
Directory	/workspace/49.clkmgr_frequency/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency_timeout.750788949
Short name	T372
Test name
Test status
Simulation time	150122755 ps
CPU time	1.32 seconds
Started	Mar 12 12:48:29 PM PDT 24
Finished	Mar 12 12:48:31 PM PDT 24
Peak memory	200892 kb
Host	smart-0836a898-ca86-4d2a-8805-f6c0ab98256d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750788949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_ti meout.750788949
Directory	/workspace/49.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/49.clkmgr_idle_intersig_mubi.2012803969
Short name	T321
Test name
Test status
Simulation time	52839438 ps
CPU time	0.98 seconds
Started	Mar 12 12:48:30 PM PDT 24
Finished	Mar 12 12:48:32 PM PDT 24
Peak memory	200812 kb
Host	smart-96d5e740-3a46-44f3-b259-918908674328
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012803969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.2012803969
Directory	/workspace/49.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.1849670407
Short name	T800
Test name
Test status
Simulation time	22733622 ps
CPU time	0.9 seconds
Started	Mar 12 12:48:30 PM PDT 24
Finished	Mar 12 12:48:31 PM PDT 24
Peak memory	200792 kb
Host	smart-cb62b05b-d8d2-4cf1-ae6d-e3551e94862a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849670407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.clkmgr_lc_clk_byp_req_intersig_mubi.1849670407
Directory	/workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.2560946855
Short name	T637
Test name
Test status
Simulation time	127635907 ps
CPU time	1.06 seconds
Started	Mar 12 12:48:47 PM PDT 24
Finished	Mar 12 12:48:49 PM PDT 24
Peak memory	200752 kb
Host	smart-dcdb2cb1-29fc-4ef1-87b7-8ae583be93bd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560946855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.clkmgr_lc_ctrl_intersig_mubi.2560946855
Directory	/workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_peri.1334660233
Short name	T765
Test name
Test status
Simulation time	17545047 ps
CPU time	0.76 seconds
Started	Mar 12 12:48:28 PM PDT 24
Finished	Mar 12 12:48:29 PM PDT 24
Peak memory	200804 kb
Host	smart-6d82e86b-8a06-4e76-9e31-4e9543e96a03
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334660233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.1334660233
Directory	/workspace/49.clkmgr_peri/latest

Test location	/workspace/coverage/default/49.clkmgr_smoke.200600752
Short name	T520
Test name
Test status
Simulation time	17328954 ps
CPU time	0.8 seconds
Started	Mar 12 12:48:27 PM PDT 24
Finished	Mar 12 12:48:28 PM PDT 24
Peak memory	200804 kb
Host	smart-6aa2ff21-e2e7-4c25-91b6-7b5cbd339802
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200600752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.200600752
Directory	/workspace/49.clkmgr_smoke/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all.4009712561
Short name	T3
Test name
Test status
Simulation time	10769451299 ps
CPU time	34.63 seconds
Started	Mar 12 12:48:34 PM PDT 24
Finished	Mar 12 12:49:09 PM PDT 24
Peak memory	201108 kb
Host	smart-9df64b08-c43c-4c94-8620-0ec534d4f8ba
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009712561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.4009712561
Directory	/workspace/49.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.2502950970
Short name	T17
Test name
Test status
Simulation time	109412676328 ps
CPU time	443 seconds
Started	Mar 12 12:48:28 PM PDT 24
Finished	Mar 12 12:55:51 PM PDT 24
Peak memory	209564 kb
Host	smart-17fc2254-7c5c-416d-ab38-8c6bc544cbb4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2502950970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.2502950970
Directory	/workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.clkmgr_trans.4219742992
Short name	T549
Test name
Test status
Simulation time	31328064 ps
CPU time	0.73 seconds
Started	Mar 12 12:48:32 PM PDT 24
Finished	Mar 12 12:48:32 PM PDT 24
Peak memory	200840 kb
Host	smart-b4292acd-dbcc-4c1a-8e64-90ff447a1d07
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219742992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.4219742992
Directory	/workspace/49.clkmgr_trans/latest

Test location	/workspace/coverage/default/5.clkmgr_alert_test.3866283635
Short name	T754
Test name
Test status
Simulation time	22658802 ps
CPU time	0.75 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	200820 kb
Host	smart-46023629-7bbb-471a-9d5c-315551f92db3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866283635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm gr_alert_test.3866283635
Directory	/workspace/5.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.1646643822
Short name	T521
Test name
Test status
Simulation time	14515641 ps
CPU time	0.73 seconds
Started	Mar 12 12:46:35 PM PDT 24
Finished	Mar 12 12:46:36 PM PDT 24
Peak memory	200824 kb
Host	smart-2ef58c89-02c5-4c97-9263-caec0870e6fe
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646643822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.1646643822
Directory	/workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_status.1259324932
Short name	T644
Test name
Test status
Simulation time	34038338 ps
CPU time	0.74 seconds
Started	Mar 12 12:46:36 PM PDT 24
Finished	Mar 12 12:46:37 PM PDT 24
Peak memory	200728 kb
Host	smart-5124e986-5a78-45b7-a735-48b66d0a9b66
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259324932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.1259324932
Directory	/workspace/5.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/5.clkmgr_div_intersig_mubi.2224609824
Short name	T267
Test name
Test status
Simulation time	17833485 ps
CPU time	0.8 seconds
Started	Mar 12 12:46:36 PM PDT 24
Finished	Mar 12 12:46:37 PM PDT 24
Peak memory	200824 kb
Host	smart-5c958766-ce03-43ea-b5b7-628ec366d6a0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224609824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.2224609824
Directory	/workspace/5.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_extclk.1066434991
Short name	T586
Test name
Test status
Simulation time	17040576 ps
CPU time	0.78 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	200736 kb
Host	smart-22bab6bf-2da7-46d0-ad23-5afeecc6dd14
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066434991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.1066434991
Directory	/workspace/5.clkmgr_extclk/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency.1490888384
Short name	T522
Test name
Test status
Simulation time	1433570459 ps
CPU time	5.85 seconds
Started	Mar 12 12:46:35 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	200860 kb
Host	smart-6780c02c-7f6f-4dbf-a2fd-1de1dc070775
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490888384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.1490888384
Directory	/workspace/5.clkmgr_frequency/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency_timeout.3894206394
Short name	T795
Test name
Test status
Simulation time	891506198 ps
CPU time	3.45 seconds
Started	Mar 12 12:46:34 PM PDT 24
Finished	Mar 12 12:46:38 PM PDT 24
Peak memory	200876 kb
Host	smart-145aaf0c-1524-432a-8326-e31aecebcd37
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894206394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti meout.3894206394
Directory	/workspace/5.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/5.clkmgr_idle_intersig_mubi.2810833940
Short name	T292
Test name
Test status
Simulation time	78301322 ps
CPU time	1 seconds
Started	Mar 12 12:46:29 PM PDT 24
Finished	Mar 12 12:46:31 PM PDT 24
Peak memory	200848 kb
Host	smart-0e78a353-36be-4e0e-86e6-0632a690afab
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810833940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.2810833940
Directory	/workspace/5.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.4021285079
Short name	T263
Test name
Test status
Simulation time	60798654 ps
CPU time	0.93 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:46:45 PM PDT 24
Peak memory	200812 kb
Host	smart-9ac930ac-1bb3-4e4b-aeb9-35b26dc337e2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021285079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_clk_byp_req_intersig_mubi.4021285079
Directory	/workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.1311597617
Short name	T246
Test name
Test status
Simulation time	92189400 ps
CPU time	1.01 seconds
Started	Mar 12 12:46:33 PM PDT 24
Finished	Mar 12 12:46:34 PM PDT 24
Peak memory	200640 kb
Host	smart-622cbe9f-25ba-4c80-9f1d-b8ca269ef511
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311597617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_ctrl_intersig_mubi.1311597617
Directory	/workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_peri.291573682
Short name	T525
Test name
Test status
Simulation time	40334834 ps
CPU time	0.78 seconds
Started	Mar 12 12:46:31 PM PDT 24
Finished	Mar 12 12:46:32 PM PDT 24
Peak memory	200636 kb
Host	smart-3a2d43cc-7246-46b2-8147-678c3a74f073
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291573682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.291573682
Directory	/workspace/5.clkmgr_peri/latest

Test location	/workspace/coverage/default/5.clkmgr_regwen.507126604
Short name	T801
Test name
Test status
Simulation time	389273515 ps
CPU time	2.67 seconds
Started	Mar 12 12:46:36 PM PDT 24
Finished	Mar 12 12:46:40 PM PDT 24
Peak memory	200768 kb
Host	smart-63863839-8fe9-419d-8e43-73cd98a99e7d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507126604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.507126604
Directory	/workspace/5.clkmgr_regwen/latest

Test location	/workspace/coverage/default/5.clkmgr_smoke.3397843743
Short name	T369
Test name
Test status
Simulation time	22744258 ps
CPU time	0.9 seconds
Started	Mar 12 12:46:29 PM PDT 24
Finished	Mar 12 12:46:31 PM PDT 24
Peak memory	200852 kb
Host	smart-29b63c74-f921-4fc2-a37a-2938a778f03a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397843743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.3397843743
Directory	/workspace/5.clkmgr_smoke/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all.2314725822
Short name	T327
Test name
Test status
Simulation time	4113300145 ps
CPU time	19.17 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:47:03 PM PDT 24
Peak memory	201044 kb
Host	smart-7cfb68b6-ff24-419d-bcee-9780fd9496f3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314725822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.2314725822
Directory	/workspace/5.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.731027688
Short name	T66
Test name
Test status
Simulation time	83124245066 ps
CPU time	513.24 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:55:13 PM PDT 24
Peak memory	209512 kb
Host	smart-4de1512f-a521-4cbd-ab45-400f2aac6ecb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=731027688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.731027688
Directory	/workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.clkmgr_trans.1905356077
Short name	T590
Test name
Test status
Simulation time	441932777 ps
CPU time	2.23 seconds
Started	Mar 12 12:46:34 PM PDT 24
Finished	Mar 12 12:46:36 PM PDT 24
Peak memory	200788 kb
Host	smart-65fef2cb-8c84-4b7e-8aa3-a24494bd7eb9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905356077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.1905356077
Directory	/workspace/5.clkmgr_trans/latest

Test location	/workspace/coverage/default/6.clkmgr_alert_test.1725026308
Short name	T337
Test name
Test status
Simulation time	21514484 ps
CPU time	0.84 seconds
Started	Mar 12 12:46:35 PM PDT 24
Finished	Mar 12 12:46:36 PM PDT 24
Peak memory	200800 kb
Host	smart-e017fd07-a48c-47d5-ad66-8ef3967c9a81
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725026308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm gr_alert_test.1725026308
Directory	/workspace/6.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.920666722
Short name	T512
Test name
Test status
Simulation time	108319055 ps
CPU time	1.1 seconds
Started	Mar 12 12:46:29 PM PDT 24
Finished	Mar 12 12:46:31 PM PDT 24
Peak memory	200848 kb
Host	smart-16e0fea4-d0f4-4f59-ad5a-61a0ed51e517
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920666722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.920666722
Directory	/workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_status.1256656686
Short name	T557
Test name
Test status
Simulation time	24528167 ps
CPU time	0.84 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	199744 kb
Host	smart-7797acbd-8888-4b18-ab18-2cf09b041e13
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256656686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.1256656686
Directory	/workspace/6.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/6.clkmgr_div_intersig_mubi.1041852748
Short name	T270
Test name
Test status
Simulation time	49056167 ps
CPU time	0.94 seconds
Started	Mar 12 12:46:34 PM PDT 24
Finished	Mar 12 12:46:35 PM PDT 24
Peak memory	200820 kb
Host	smart-08635df7-76b8-44d6-bf40-252d82ee2e2b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041852748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.1041852748
Directory	/workspace/6.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_extclk.4166163314
Short name	T823
Test name
Test status
Simulation time	60393370 ps
CPU time	0.93 seconds
Started	Mar 12 12:46:36 PM PDT 24
Finished	Mar 12 12:46:38 PM PDT 24
Peak memory	200840 kb
Host	smart-f404d66b-1c05-4529-b4a2-ad42ed6b2871
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166163314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.4166163314
Directory	/workspace/6.clkmgr_extclk/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency.31588644
Short name	T581
Test name
Test status
Simulation time	1282202391 ps
CPU time	9.88 seconds
Started	Mar 12 12:46:32 PM PDT 24
Finished	Mar 12 12:46:42 PM PDT 24
Peak memory	200776 kb
Host	smart-4e2be1d7-f452-4352-823a-02dfd828bf50
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31588644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.31588644
Directory	/workspace/6.clkmgr_frequency/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency_timeout.87896511
Short name	T553
Test name
Test status
Simulation time	1841104806 ps
CPU time	6.86 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:46:50 PM PDT 24
Peak memory	200924 kb
Host	smart-6056d96a-28b5-4d0d-9a59-d756de72b187
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87896511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_time out.87896511
Directory	/workspace/6.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/6.clkmgr_idle_intersig_mubi.1907650044
Short name	T268
Test name
Test status
Simulation time	41158115 ps
CPU time	0.98 seconds
Started	Mar 12 12:46:37 PM PDT 24
Finished	Mar 12 12:46:39 PM PDT 24
Peak memory	200824 kb
Host	smart-e674b605-a8dc-44b6-babc-5322b9f76b9a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907650044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.1907650044
Directory	/workspace/6.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.974838285
Short name	T633
Test name
Test status
Simulation time	53087547 ps
CPU time	0.88 seconds
Started	Mar 12 12:46:33 PM PDT 24
Finished	Mar 12 12:46:34 PM PDT 24
Peak memory	200576 kb
Host	smart-78a10545-0aef-4523-9edb-c31946b40c04
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974838285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.clkmgr_lc_clk_byp_req_intersig_mubi.974838285
Directory	/workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.499678691
Short name	T415
Test name
Test status
Simulation time	73999767 ps
CPU time	0.95 seconds
Started	Mar 12 12:46:39 PM PDT 24
Finished	Mar 12 12:46:43 PM PDT 24
Peak memory	200800 kb
Host	smart-e75e6e0a-d857-448e-b62f-7ab0acb75f83
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499678691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.clkmgr_lc_ctrl_intersig_mubi.499678691
Directory	/workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_peri.2105052093
Short name	T589
Test name
Test status
Simulation time	19028567 ps
CPU time	0.78 seconds
Started	Mar 12 12:46:43 PM PDT 24
Finished	Mar 12 12:46:45 PM PDT 24
Peak memory	200792 kb
Host	smart-22e13e23-e4e8-4e7d-9352-4dcaff705a8c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105052093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.2105052093
Directory	/workspace/6.clkmgr_peri/latest

Test location	/workspace/coverage/default/6.clkmgr_regwen.605491339
Short name	T210
Test name
Test status
Simulation time	252998447 ps
CPU time	1.58 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	200764 kb
Host	smart-b8943b9a-c501-4e49-9619-be8c8003d118
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605491339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.605491339
Directory	/workspace/6.clkmgr_regwen/latest

Test location	/workspace/coverage/default/6.clkmgr_smoke.900405253
Short name	T365
Test name
Test status
Simulation time	14466908 ps
CPU time	0.8 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:46:44 PM PDT 24
Peak memory	200708 kb
Host	smart-16273129-97f1-4d93-bd3a-28090486326a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900405253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.900405253
Directory	/workspace/6.clkmgr_smoke/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all.2611562036
Short name	T456
Test name
Test status
Simulation time	5518550229 ps
CPU time	23.11 seconds
Started	Mar 12 12:46:39 PM PDT 24
Finished	Mar 12 12:47:04 PM PDT 24
Peak memory	201200 kb
Host	smart-b541f1e5-2518-4e0a-be58-24a19a1a4a81
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611562036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.2611562036
Directory	/workspace/6.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.690819781
Short name	T619
Test name
Test status
Simulation time	41829236574 ps
CPU time	387.63 seconds
Started	Mar 12 12:46:37 PM PDT 24
Finished	Mar 12 12:53:07 PM PDT 24
Peak memory	209584 kb
Host	smart-50484f7c-3e2a-4c24-906b-c6ac6dcdbe36
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=690819781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.690819781
Directory	/workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.clkmgr_trans.3614642279
Short name	T374
Test name
Test status
Simulation time	26860939 ps
CPU time	0.86 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	200812 kb
Host	smart-210438c5-5680-4223-87e8-fe92f709f4d0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614642279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.3614642279
Directory	/workspace/6.clkmgr_trans/latest

Test location	/workspace/coverage/default/7.clkmgr_alert_test.29673437
Short name	T602
Test name
Test status
Simulation time	17246497 ps
CPU time	0.74 seconds
Started	Mar 12 12:46:43 PM PDT 24
Finished	Mar 12 12:46:44 PM PDT 24
Peak memory	200836 kb
Host	smart-cc66cbb9-50dc-404b-b8ad-0a04869a7508
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29673437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr _alert_test.29673437
Directory	/workspace/7.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.3727077667
Short name	T502
Test name
Test status
Simulation time	17366946 ps
CPU time	0.76 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:46:44 PM PDT 24
Peak memory	200848 kb
Host	smart-756b401e-5d56-4fe8-957e-3ecd23186edd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727077667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.3727077667
Directory	/workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_status.3010526024
Short name	T441
Test name
Test status
Simulation time	13563395 ps
CPU time	0.68 seconds
Started	Mar 12 12:46:41 PM PDT 24
Finished	Mar 12 12:46:43 PM PDT 24
Peak memory	199800 kb
Host	smart-b6772236-0d99-4209-8887-9573a78a55c7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010526024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.3010526024
Directory	/workspace/7.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/7.clkmgr_div_intersig_mubi.2871102925
Short name	T664
Test name
Test status
Simulation time	44821245 ps
CPU time	0.86 seconds
Started	Mar 12 12:46:41 PM PDT 24
Finished	Mar 12 12:46:43 PM PDT 24
Peak memory	200768 kb
Host	smart-f4f9817c-df61-4b26-b09f-8b62cfa3b36a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871102925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.2871102925
Directory	/workspace/7.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_extclk.3331008690
Short name	T508
Test name
Test status
Simulation time	124926684 ps
CPU time	1.09 seconds
Started	Mar 12 12:46:35 PM PDT 24
Finished	Mar 12 12:46:36 PM PDT 24
Peak memory	200704 kb
Host	smart-323cd730-2ad4-4f5a-bac6-c23544ac1e96
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331008690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.3331008690
Directory	/workspace/7.clkmgr_extclk/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency.1184322922
Short name	T305
Test name
Test status
Simulation time	918946422 ps
CPU time	4.1 seconds
Started	Mar 12 12:46:46 PM PDT 24
Finished	Mar 12 12:46:51 PM PDT 24
Peak memory	200724 kb
Host	smart-3366223d-8d63-4322-96e8-af34403da950
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184322922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.1184322922
Directory	/workspace/7.clkmgr_frequency/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency_timeout.2937044242
Short name	T232
Test name
Test status
Simulation time	857125326 ps
CPU time	6.58 seconds
Started	Mar 12 12:46:40 PM PDT 24
Finished	Mar 12 12:46:48 PM PDT 24
Peak memory	200880 kb
Host	smart-8235c85f-1b07-4282-9473-a9a6ca7ded4b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937044242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti meout.2937044242
Directory	/workspace/7.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/7.clkmgr_idle_intersig_mubi.1120274512
Short name	T409
Test name
Test status
Simulation time	38508205 ps
CPU time	1.09 seconds
Started	Mar 12 12:46:46 PM PDT 24
Finished	Mar 12 12:46:47 PM PDT 24
Peak memory	200740 kb
Host	smart-d69f33f5-a2a1-4b48-93ec-bbb8221fe437
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120274512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.1120274512
Directory	/workspace/7.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.3756552226
Short name	T320
Test name
Test status
Simulation time	19562539 ps
CPU time	0.85 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:40 PM PDT 24
Peak memory	200776 kb
Host	smart-193aa008-8e30-4d56-bbb2-3523cad8b961
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756552226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 7.clkmgr_lc_clk_byp_req_intersig_mubi.3756552226
Directory	/workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.675600764
Short name	T282
Test name
Test status
Simulation time	23979488 ps
CPU time	0.79 seconds
Started	Mar 12 12:46:46 PM PDT 24
Finished	Mar 12 12:46:48 PM PDT 24
Peak memory	200856 kb
Host	smart-ea05fcc3-ae92-4575-a78b-572cdfb1c0f0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675600764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.clkmgr_lc_ctrl_intersig_mubi.675600764
Directory	/workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_peri.2484037256
Short name	T499
Test name
Test status
Simulation time	55880190 ps
CPU time	0.89 seconds
Started	Mar 12 12:46:44 PM PDT 24
Finished	Mar 12 12:46:45 PM PDT 24
Peak memory	200548 kb
Host	smart-99cfe34b-b6f5-430b-8292-aa4dcd3144ac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484037256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.2484037256
Directory	/workspace/7.clkmgr_peri/latest

Test location	/workspace/coverage/default/7.clkmgr_regwen.1729330118
Short name	T309
Test name
Test status
Simulation time	1345238429 ps
CPU time	7.43 seconds
Started	Mar 12 12:46:39 PM PDT 24
Finished	Mar 12 12:46:49 PM PDT 24
Peak memory	200928 kb
Host	smart-b6379e37-272f-4b78-afe4-237ff180e4b3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729330118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.1729330118
Directory	/workspace/7.clkmgr_regwen/latest

Test location	/workspace/coverage/default/7.clkmgr_smoke.2907256100
Short name	T835
Test name
Test status
Simulation time	73557896 ps
CPU time	1.06 seconds
Started	Mar 12 12:46:37 PM PDT 24
Finished	Mar 12 12:46:39 PM PDT 24
Peak memory	200800 kb
Host	smart-47ffd501-f929-4a8e-8c30-ee6d8cb74b2a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907256100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.2907256100
Directory	/workspace/7.clkmgr_smoke/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all.3231805628
Short name	T126
Test name
Test status
Simulation time	3008537301 ps
CPU time	22.64 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:47:05 PM PDT 24
Peak memory	201096 kb
Host	smart-11763126-0de8-428f-9b3d-71884d2000bc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231805628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.3231805628
Directory	/workspace/7.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.518442051
Short name	T136
Test name
Test status
Simulation time	65210998918 ps
CPU time	583.15 seconds
Started	Mar 12 12:46:47 PM PDT 24
Finished	Mar 12 12:56:30 PM PDT 24
Peak memory	211368 kb
Host	smart-d6a1999e-b2e5-4eaf-ac57-4d1ab7be031a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=518442051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.518442051
Directory	/workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.clkmgr_trans.3714825263
Short name	T569
Test name
Test status
Simulation time	43602398 ps
CPU time	0.81 seconds
Started	Mar 12 12:46:43 PM PDT 24
Finished	Mar 12 12:46:44 PM PDT 24
Peak memory	200796 kb
Host	smart-c821e917-da23-4558-a831-5192fdfa11e5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714825263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.3714825263
Directory	/workspace/7.clkmgr_trans/latest

Test location	/workspace/coverage/default/8.clkmgr_alert_test.1702936232
Short name	T47
Test name
Test status
Simulation time	33970884 ps
CPU time	0.81 seconds
Started	Mar 12 12:46:46 PM PDT 24
Finished	Mar 12 12:46:48 PM PDT 24
Peak memory	200784 kb
Host	smart-bceba0c5-1599-4ca0-8224-2b05e95c140e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702936232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm gr_alert_test.1702936232
Directory	/workspace/8.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.3254050717
Short name	T90
Test name
Test status
Simulation time	27797326 ps
CPU time	1.04 seconds
Started	Mar 12 12:46:46 PM PDT 24
Finished	Mar 12 12:46:48 PM PDT 24
Peak memory	200728 kb
Host	smart-47c42e2f-c4ba-4227-8c8a-16290ed6603a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254050717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.3254050717
Directory	/workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_status.3521619470
Short name	T36
Test name
Test status
Simulation time	23937197 ps
CPU time	0.7 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:46:44 PM PDT 24
Peak memory	200712 kb
Host	smart-c668bde3-205e-457e-ae30-24a3f2d5ce3f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521619470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.3521619470
Directory	/workspace/8.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/8.clkmgr_div_intersig_mubi.3153233160
Short name	T131
Test name
Test status
Simulation time	392055351 ps
CPU time	1.9 seconds
Started	Mar 12 12:46:41 PM PDT 24
Finished	Mar 12 12:46:45 PM PDT 24
Peak memory	200788 kb
Host	smart-99cc3b3d-5ad5-4e7e-abb0-e3dc69909cfc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153233160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.3153233160
Directory	/workspace/8.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_extclk.2032879948
Short name	T505
Test name
Test status
Simulation time	58129977 ps
CPU time	0.9 seconds
Started	Mar 12 12:46:37 PM PDT 24
Finished	Mar 12 12:46:39 PM PDT 24
Peak memory	200724 kb
Host	smart-d7721a1a-0c72-49f1-982a-9388917b0879
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032879948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.2032879948
Directory	/workspace/8.clkmgr_extclk/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency.1076984444
Short name	T394
Test name
Test status
Simulation time	498164159 ps
CPU time	2.51 seconds
Started	Mar 12 12:46:47 PM PDT 24
Finished	Mar 12 12:46:50 PM PDT 24
Peak memory	200728 kb
Host	smart-4b081f15-3c98-4864-b9d7-9903cd78df63
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076984444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.1076984444
Directory	/workspace/8.clkmgr_frequency/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency_timeout.1033132883
Short name	T726
Test name
Test status
Simulation time	1466145232 ps
CPU time	8.34 seconds
Started	Mar 12 12:46:40 PM PDT 24
Finished	Mar 12 12:46:50 PM PDT 24
Peak memory	200896 kb
Host	smart-8cf54b1b-b253-4bd4-82c3-ffb629774e64
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033132883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti meout.1033132883
Directory	/workspace/8.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/8.clkmgr_idle_intersig_mubi.3085118725
Short name	T158
Test name
Test status
Simulation time	28049031 ps
CPU time	0.89 seconds
Started	Mar 12 12:46:46 PM PDT 24
Finished	Mar 12 12:46:48 PM PDT 24
Peak memory	200720 kb
Host	smart-d7295e55-6be6-4e23-8e88-2aefcd628914
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085118725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.3085118725
Directory	/workspace/8.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.3957996783
Short name	T667
Test name
Test status
Simulation time	65473022 ps
CPU time	0.92 seconds
Started	Mar 12 12:46:41 PM PDT 24
Finished	Mar 12 12:46:44 PM PDT 24
Peak memory	200736 kb
Host	smart-7b6f94ac-6b4e-4b17-bd69-e13d6af13e20
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957996783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_clk_byp_req_intersig_mubi.3957996783
Directory	/workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.2488423328
Short name	T562
Test name
Test status
Simulation time	25531958 ps
CPU time	0.92 seconds
Started	Mar 12 12:46:46 PM PDT 24
Finished	Mar 12 12:46:48 PM PDT 24
Peak memory	200652 kb
Host	smart-b4e4f3fe-7f96-4f2c-8938-9b38bd8ba872
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488423328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_ctrl_intersig_mubi.2488423328
Directory	/workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_peri.512253448
Short name	T503
Test name
Test status
Simulation time	21185228 ps
CPU time	0.74 seconds
Started	Mar 12 12:46:39 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	200700 kb
Host	smart-130f43b3-de2b-4284-9df2-fdfcdb9c5cb5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512253448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.512253448
Directory	/workspace/8.clkmgr_peri/latest

Test location	/workspace/coverage/default/8.clkmgr_regwen.3760031683
Short name	T540
Test name
Test status
Simulation time	652924991 ps
CPU time	3.11 seconds
Started	Mar 12 12:46:39 PM PDT 24
Finished	Mar 12 12:46:45 PM PDT 24
Peak memory	200956 kb
Host	smart-2a12bf91-56ae-4ece-a024-d5ac61c8c069
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760031683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.3760031683
Directory	/workspace/8.clkmgr_regwen/latest

Test location	/workspace/coverage/default/8.clkmgr_smoke.3977836403
Short name	T787
Test name
Test status
Simulation time	20337388 ps
CPU time	0.83 seconds
Started	Mar 12 12:46:48 PM PDT 24
Finished	Mar 12 12:46:49 PM PDT 24
Peak memory	200804 kb
Host	smart-e06dd825-116e-4b61-b6f8-77970f870d35
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977836403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.3977836403
Directory	/workspace/8.clkmgr_smoke/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all.3515052639
Short name	T229
Test name
Test status
Simulation time	160746262 ps
CPU time	1.38 seconds
Started	Mar 12 12:46:37 PM PDT 24
Finished	Mar 12 12:46:40 PM PDT 24
Peak memory	200704 kb
Host	smart-8e9ead01-01f9-461e-88a5-3ea9a2bca2aa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515052639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.3515052639
Directory	/workspace/8.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.307377281
Short name	T550
Test name
Test status
Simulation time	50695075265 ps
CPU time	527.31 seconds
Started	Mar 12 12:46:43 PM PDT 24
Finished	Mar 12 12:55:31 PM PDT 24
Peak memory	209508 kb
Host	smart-fb3346b1-dcf0-4755-994d-91b6def0f969
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=307377281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.307377281
Directory	/workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.clkmgr_trans.2274239691
Short name	T623
Test name
Test status
Simulation time	57261341 ps
CPU time	0.91 seconds
Started	Mar 12 12:46:39 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	200804 kb
Host	smart-e0df0438-cfeb-439b-94f6-b48a3c7d81a2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274239691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2274239691
Directory	/workspace/8.clkmgr_trans/latest

Test location	/workspace/coverage/default/9.clkmgr_alert_test.2483953967
Short name	T21
Test name
Test status
Simulation time	48524317 ps
CPU time	0.88 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	200856 kb
Host	smart-1bf93122-b8fc-4d28-b22c-eaa1c6af74c6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483953967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm gr_alert_test.2483953967
Directory	/workspace/9.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.1374867985
Short name	T20
Test name
Test status
Simulation time	21225398 ps
CPU time	0.83 seconds
Started	Mar 12 12:46:51 PM PDT 24
Finished	Mar 12 12:46:52 PM PDT 24
Peak memory	200756 kb
Host	smart-542d54ca-3563-4cd9-8e46-4f0a922d1b8f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374867985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.1374867985
Directory	/workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_status.4131284382
Short name	T839
Test name
Test status
Simulation time	12244418 ps
CPU time	0.69 seconds
Started	Mar 12 12:46:40 PM PDT 24
Finished	Mar 12 12:46:42 PM PDT 24
Peak memory	199752 kb
Host	smart-5dbce729-b546-4a4a-a07c-3a338c015360
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131284382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.4131284382
Directory	/workspace/9.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/9.clkmgr_div_intersig_mubi.3243654783
Short name	T492
Test name
Test status
Simulation time	13322966 ps
CPU time	0.7 seconds
Started	Mar 12 12:46:45 PM PDT 24
Finished	Mar 12 12:46:47 PM PDT 24
Peak memory	200664 kb
Host	smart-dcc319d4-0554-48c7-a5fb-6bb27e4918d1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243654783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.3243654783
Directory	/workspace/9.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_extclk.1035052927
Short name	T359
Test name
Test status
Simulation time	16197973 ps
CPU time	0.73 seconds
Started	Mar 12 12:46:45 PM PDT 24
Finished	Mar 12 12:46:46 PM PDT 24
Peak memory	200856 kb
Host	smart-5c7323bc-a633-4715-bde2-e28a083a5023
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035052927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.1035052927
Directory	/workspace/9.clkmgr_extclk/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency.1216391319
Short name	T658
Test name
Test status
Simulation time	1798619086 ps
CPU time	7.99 seconds
Started	Mar 12 12:46:46 PM PDT 24
Finished	Mar 12 12:46:55 PM PDT 24
Peak memory	200876 kb
Host	smart-f840b22f-050b-4192-a779-c3d45f33154f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216391319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.1216391319
Directory	/workspace/9.clkmgr_frequency/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency_timeout.3400453382
Short name	T463
Test name
Test status
Simulation time	298418477 ps
CPU time	1.72 seconds
Started	Mar 12 12:46:40 PM PDT 24
Finished	Mar 12 12:46:43 PM PDT 24
Peak memory	200896 kb
Host	smart-fe743979-77e2-4891-bd85-2a4fd93a7c73
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400453382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti meout.3400453382
Directory	/workspace/9.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/9.clkmgr_idle_intersig_mubi.1175151846
Short name	T376
Test name
Test status
Simulation time	228122357 ps
CPU time	1.49 seconds
Started	Mar 12 12:46:46 PM PDT 24
Finished	Mar 12 12:46:49 PM PDT 24
Peak memory	200808 kb
Host	smart-4abb7077-8ae1-4b9e-bb34-2ae899c9895e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175151846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.1175151846
Directory	/workspace/9.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.2279081561
Short name	T308
Test name
Test status
Simulation time	58734162 ps
CPU time	0.91 seconds
Started	Mar 12 12:46:38 PM PDT 24
Finished	Mar 12 12:46:41 PM PDT 24
Peak memory	200768 kb
Host	smart-2f3b3307-d15c-4e37-a05a-a9660d665221
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279081561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.clkmgr_lc_clk_byp_req_intersig_mubi.2279081561
Directory	/workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.1068485763
Short name	T753
Test name
Test status
Simulation time	14097539 ps
CPU time	0.73 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:46:44 PM PDT 24
Peak memory	200684 kb
Host	smart-e9011d37-6057-40bc-bd44-8223662d50db
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068485763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.clkmgr_lc_ctrl_intersig_mubi.1068485763
Directory	/workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_peri.619668299
Short name	T790
Test name
Test status
Simulation time	15862674 ps
CPU time	0.79 seconds
Started	Mar 12 12:46:40 PM PDT 24
Finished	Mar 12 12:46:42 PM PDT 24
Peak memory	200676 kb
Host	smart-1cd61326-98b0-48a2-8149-9a9eb95a9a23
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619668299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.619668299
Directory	/workspace/9.clkmgr_peri/latest

Test location	/workspace/coverage/default/9.clkmgr_regwen.2068628657
Short name	T526
Test name
Test status
Simulation time	165199657 ps
CPU time	1.27 seconds
Started	Mar 12 12:46:46 PM PDT 24
Finished	Mar 12 12:46:48 PM PDT 24
Peak memory	200660 kb
Host	smart-b7ea0ca6-b4e1-47c5-bcc4-283abe6dd86d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068628657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.2068628657
Directory	/workspace/9.clkmgr_regwen/latest

Test location	/workspace/coverage/default/9.clkmgr_smoke.2758150650
Short name	T702
Test name
Test status
Simulation time	43026238 ps
CPU time	0.89 seconds
Started	Mar 12 12:46:41 PM PDT 24
Finished	Mar 12 12:46:44 PM PDT 24
Peak memory	200772 kb
Host	smart-a39391d8-c595-4b87-be13-35494de6496a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758150650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.2758150650
Directory	/workspace/9.clkmgr_smoke/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all.1357547262
Short name	T224
Test name
Test status
Simulation time	2057302562 ps
CPU time	8.26 seconds
Started	Mar 12 12:46:47 PM PDT 24
Finished	Mar 12 12:46:55 PM PDT 24
Peak memory	201056 kb
Host	smart-35740b8c-c687-433e-abd0-65b1cc8a5370
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357547262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.1357547262
Directory	/workspace/9.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.2326084193
Short name	T360
Test name
Test status
Simulation time	30769883710 ps
CPU time	320.45 seconds
Started	Mar 12 12:46:42 PM PDT 24
Finished	Mar 12 12:52:03 PM PDT 24
Peak memory	209540 kb
Host	smart-0d8af0ab-cc78-4762-91d9-20a222798e8e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2326084193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.2326084193
Directory	/workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.clkmgr_trans.1309601724
Short name	T527
Test name
Test status
Simulation time	79722744 ps
CPU time	1.09 seconds
Started	Mar 12 12:46:39 PM PDT 24
Finished	Mar 12 12:46:42 PM PDT 24
Peak memory	200812 kb
Host	smart-25da463c-1a49-40b5-b797-50934bffcb2f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309601724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.1309601724
Directory	/workspace/9.clkmgr_trans/latest

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