Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	645988	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3682806

1

T7

5

T8

14

T9

204

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1064337	1			T7	4		T8	16		T9	269
values[0x0]	1501686	1			T7	7		T8	20		T9	173
values[0x1]	1762771	1			T7	2		T8	13		T9	168

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	356855	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3971939

1

T7

5

T8

19

T9

265

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16246	1			T4	1		T30	1		T6	1
valid_sources[0x01]	17306	1			T4	1		T31	1		T6	3
valid_sources[0x02]	18605	1			T9	4		T4	2		T6	1
valid_sources[0x03]	16889	1			T4	6		T31	1		T6	3
valid_sources[0x04]	17407	1			T9	2		T4	3		T6	3
valid_sources[0x05]	15727	1			T4	3		T30	1		T6	1
valid_sources[0x06]	17459	1			T9	1		T4	6		T30	1
valid_sources[0x07]	16121	1			T9	1		T4	3		T6	2
valid_sources[0x08]	17256	1			T9	2		T4	2		T6	2
valid_sources[0x09]	16479	1			T8	8		T4	6		T6	2
valid_sources[0x0a]	16094	1			T9	11		T27	1		T4	2
valid_sources[0x0b]	16779	1			T4	1		T30	1		T31	1
valid_sources[0x0c]	16567	1			T4	2		T6	3		T1	1
valid_sources[0x0d]	16827	1			T9	14		T4	2		T6	2
valid_sources[0x0e]	17541	1			T4	3		T31	1		T6	1
valid_sources[0x0f]	16420	1			T4	3		T31	1		T1	1
valid_sources[0x10]	17333	1			T9	1		T4	1		T30	1
valid_sources[0x11]	17938	1			T9	12		T4	5		T6	7
valid_sources[0x12]	17552	1			T8	1		T4	2		T30	2
valid_sources[0x13]	15728	1			T9	9		T4	1		T30	1
valid_sources[0x14]	17339	1			T4	4		T31	1		T6	7
valid_sources[0x15]	17409	1			T9	1		T4	3		T6	3
valid_sources[0x16]	16505	1			T27	1		T4	1		T30	1
valid_sources[0x17]	17025	1			T4	2		T6	4		T3	4
valid_sources[0x18]	16175	1			T4	3		T6	2		T1	4
valid_sources[0x19]	17345	1			T4	1		T30	2		T1	1
valid_sources[0x1a]	16108	1			T4	1		T30	1		T6	3
valid_sources[0x1b]	17340	1			T4	4		T30	1		T6	2
valid_sources[0x1c]	15573	1			T8	1		T9	1		T6	1
valid_sources[0x1d]	16559	1			T9	25		T4	4		T6	3
valid_sources[0x1e]	16840	1			T4	3		T6	2		T1	1
valid_sources[0x1f]	16172	1			T4	1		T31	2		T6	4
valid_sources[0x20]	17209	1			T9	5		T4	5		T30	1
valid_sources[0x21]	15706	1			T4	3		T30	1		T6	7
valid_sources[0x22]	16828	1			T9	11		T4	2		T30	1
valid_sources[0x23]	17747	1			T8	1		T1	1		T20	1
valid_sources[0x24]	17933	1			T9	1		T4	2		T6	1
valid_sources[0x25]	18432	1			T9	11		T4	3		T6	5
valid_sources[0x26]	17236	1			T8	1		T9	11		T4	6
valid_sources[0x27]	17559	1			T9	7		T4	2		T30	2
valid_sources[0x28]	16599	1			T4	1		T1	2		T12	276
valid_sources[0x29]	17563	1			T4	2		T30	1		T31	2
valid_sources[0x2a]	16600	1			T8	2		T9	1		T3	1
valid_sources[0x2b]	16813	1			T4	4		T1	2		T19	1
valid_sources[0x2c]	17351	1			T4	1		T30	1		T31	1
valid_sources[0x2d]	16700	1			T9	1		T4	3		T6	7
valid_sources[0x2e]	18327	1			T30	1		T31	2		T6	2
valid_sources[0x2f]	16002	1			T4	5		T6	2		T19	1
valid_sources[0x30]	16616	1			T4	2		T1	3		T26	1
valid_sources[0x31]	15906	1			T4	4		T6	2		T1	1
valid_sources[0x32]	17327	1			T9	2		T4	6		T30	1
valid_sources[0x33]	15588	1			T4	3		T6	3		T1	1
valid_sources[0x34]	17589	1			T4	2		T30	1		T31	1
valid_sources[0x35]	17876	1			T8	1		T4	3		T6	2
valid_sources[0x36]	17021	1			T8	2		T9	1		T4	2
valid_sources[0x37]	16340	1			T4	2		T31	1		T6	2
valid_sources[0x38]	16671	1			T9	2		T4	2		T6	5
valid_sources[0x39]	16444	1			T8	1		T6	2		T1	3
valid_sources[0x3a]	16055	1			T8	1		T9	1		T27	1
valid_sources[0x3b]	16206	1			T30	1		T6	1		T1	1
valid_sources[0x3c]	16618	1			T4	1		T30	2		T31	1
valid_sources[0x3d]	16649	1			T4	1		T30	1		T31	1
valid_sources[0x3e]	17839	1			T8	1		T27	1		T4	3
valid_sources[0x3f]	17255	1			T9	4		T4	1		T31	1
valid_sources[0x40]	15961	1			T4	2		T30	1		T31	1
valid_sources[0x41]	16069	1			T4	2		T6	4		T20	3
valid_sources[0x42]	17817	1			T30	1		T1	3		T12	322
valid_sources[0x43]	17422	1			T6	7		T12	330		T13	6
valid_sources[0x44]	16786	1			T9	12		T4	3		T31	3
valid_sources[0x45]	16471	1			T9	4		T4	7		T31	1
valid_sources[0x46]	18031	1			T9	12		T4	5		T6	1
valid_sources[0x47]	16730	1			T4	2		T6	2		T1	1
valid_sources[0x48]	17059	1			T4	5		T6	3		T22	2
valid_sources[0x49]	17388	1			T9	6		T4	2		T6	3
valid_sources[0x4a]	17865	1			T4	2		T31	1		T6	1
valid_sources[0x4b]	16939	1			T9	11		T30	1		T6	4
valid_sources[0x4c]	15226	1			T8	1		T9	1		T4	1
valid_sources[0x4d]	16645	1			T4	3		T30	1		T6	3
valid_sources[0x4e]	16380	1			T4	1		T30	1		T6	4
valid_sources[0x4f]	16348	1			T4	2		T6	1		T1	1
valid_sources[0x50]	15798	1			T9	3		T4	3		T6	6
valid_sources[0x51]	16129	1			T4	2		T6	1		T1	2
valid_sources[0x52]	16121	1			T9	9		T4	2		T1	2
valid_sources[0x53]	17949	1			T9	9		T4	2		T30	1
valid_sources[0x54]	16832	1			T4	3		T6	2		T26	2
valid_sources[0x55]	16684	1			T9	1		T4	1		T6	1
valid_sources[0x56]	15107	1			T9	2		T6	4		T1	2
valid_sources[0x57]	17542	1			T9	13		T4	5		T30	3
valid_sources[0x58]	16953	1			T8	1		T9	4		T4	2
valid_sources[0x59]	20569	1			T8	1		T9	4		T4	2
valid_sources[0x5a]	16125	1			T4	5		T31	1		T6	3
valid_sources[0x5b]	16682	1			T4	3		T6	4		T1	2
valid_sources[0x5c]	17364	1			T9	4		T4	2		T31	1
valid_sources[0x5d]	17954	1			T4	1		T31	2		T6	1
valid_sources[0x5e]	16744	1			T9	2		T4	2		T31	1
valid_sources[0x5f]	16796	1			T8	1		T9	7		T4	1
valid_sources[0x60]	17557	1			T4	1		T30	2		T6	4
valid_sources[0x61]	16727	1			T4	1		T30	2		T6	3
valid_sources[0x62]	17709	1			T4	1		T31	2		T1	2
valid_sources[0x63]	16523	1			T8	1		T4	3		T30	1
valid_sources[0x64]	18296	1			T4	1		T6	1		T1	1
valid_sources[0x65]	18571	1			T9	3		T6	3		T1	1
valid_sources[0x66]	15832	1			T9	1		T4	2		T6	1
valid_sources[0x67]	16813	1			T30	1		T1	1		T22	7
valid_sources[0x68]	17312	1			T4	1		T30	3		T6	6
valid_sources[0x69]	16737	1			T9	1		T4	2		T31	1
valid_sources[0x6a]	16868	1			T6	4		T1	2		T26	7
valid_sources[0x6b]	17841	1			T9	4		T4	3		T6	4
valid_sources[0x6c]	14727	1			T4	1		T6	2		T1	3
valid_sources[0x6d]	15526	1			T9	2		T4	1		T30	1
valid_sources[0x6e]	17335	1			T4	3		T6	2		T1	1
valid_sources[0x6f]	16686	1			T9	13		T4	2		T31	1
valid_sources[0x70]	16755	1			T9	15		T4	5		T30	1
valid_sources[0x71]	15560	1			T9	3		T4	1		T6	1
valid_sources[0x72]	15792	1			T4	4		T31	1		T1	1
valid_sources[0x73]	17197	1			T9	5		T4	3		T30	1
valid_sources[0x74]	16138	1			T27	1		T30	1		T6	3
valid_sources[0x75]	16556	1			T6	4		T22	2		T3	1
valid_sources[0x76]	16324	1			T4	1		T30	1		T6	6
valid_sources[0x77]	18130	1			T30	1		T1	5		T26	1
valid_sources[0x78]	16392	1			T8	1		T9	1		T4	3
valid_sources[0x79]	15464	1			T9	18		T4	1		T30	3
valid_sources[0x7a]	17618	1			T4	2		T30	1		T6	7
valid_sources[0x7b]	15170	1			T9	1		T4	3		T6	6
valid_sources[0x7c]	16793	1			T4	7		T6	1		T1	3
valid_sources[0x7d]	15942	1			T4	3		T6	4		T22	4
valid_sources[0x7e]	16094	1			T4	3		T6	3		T1	3
valid_sources[0x7f]	16827	1			T9	3		T4	2		T6	6
valid_sources[0x80]	16476	1			T9	2		T4	3		T30	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

930082

1

T7

2

T8

9

T9

126

values[0x0]

all_enables

biggest_size

1402760

1

T7

3

T8

3

T9

50

values[0x1]

all_enables

biggest_size

1349964

1

T8

2

T9

28

T28

2