Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	805003810	71889	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805003810	71889	0	0
T1	890820	288	0	0
T2	810080	368	0	0
T3	0	177	0	0
T12	0	1182	0	0
T13	0	354	0	0
T14	0	429	0	0
T15	0	117	0	0
T16	0	1835	0	0
T17	0	894	0	0
T18	0	77	0	0
T19	8155	0	0	0
T20	8915	0	0	0
T21	191265	0	0	0
T22	25135	0	0	0
T23	94875	0	0	0
T24	8755	0	0	0
T25	10555	0	0	0
T26	218065	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161000762	10838	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161000762	10838	0	0
T1	178164	37	0	0
T2	162016	58	0	0
T3	0	25	0	0
T12	0	200	0	0
T13	0	58	0	0
T14	0	69	0	0
T15	0	17	0	0
T16	0	242	0	0
T17	0	115	0	0
T18	0	14	0	0
T19	1631	0	0	0
T20	1783	0	0	0
T21	38253	0	0	0
T22	5027	0	0	0
T23	18975	0	0	0
T24	1751	0	0	0
T25	2111	0	0	0
T26	43613	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161000762	14493	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161000762	14493	0	0
T1	178164	62	0	0
T2	162016	74	0	0
T3	0	34	0	0
T12	0	242	0	0
T13	0	72	0	0
T14	0	87	0	0
T15	0	23	0	0
T16	0	372	0	0
T17	0	175	0	0
T18	0	15	0	0
T19	1631	0	0	0
T20	1783	0	0	0
T21	38253	0	0	0
T22	5027	0	0	0
T23	18975	0	0	0
T24	1751	0	0	0
T25	2111	0	0	0
T26	43613	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161000762	21463	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161000762	21463	0	0
T1	178164	94	0	0
T2	162016	104	0	0
T3	0	53	0	0
T12	0	303	0	0
T13	0	96	0	0
T14	0	119	0	0
T15	0	37	0	0
T16	0	615	0	0
T17	0	298	0	0
T18	0	19	0	0
T19	1631	0	0	0
T20	1783	0	0	0
T21	38253	0	0	0
T22	5027	0	0	0
T23	18975	0	0	0
T24	1751	0	0	0
T25	2111	0	0	0
T26	43613	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161000762	10631	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161000762	10631	0	0
T1	178164	37	0	0
T2	162016	58	0	0
T3	0	25	0	0
T12	0	200	0	0
T13	0	56	0	0
T14	0	67	0	0
T15	0	17	0	0
T16	0	234	0	0
T17	0	129	0	0
T18	0	14	0	0
T19	1631	0	0	0
T20	1783	0	0	0
T21	38253	0	0	0
T22	5027	0	0	0
T23	18975	0	0	0
T24	1751	0	0	0
T25	2111	0	0	0
T26	43613	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161000762	14464	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161000762	14464	0	0
T1	178164	58	0	0
T2	162016	74	0	0
T3	0	40	0	0
T12	0	237	0	0
T13	0	72	0	0
T14	0	87	0	0
T15	0	23	0	0
T16	0	372	0	0
T17	0	177	0	0
T18	0	15	0	0
T19	1631	0	0	0
T20	1783	0	0	0
T21	38253	0	0	0
T22	5027	0	0	0
T23	18975	0	0	0
T24	1751	0	0	0
T25	2111	0	0	0
T26	43613	0	0	0